1/* 2 * Support for PCI bridges found on Power Macintoshes. 3 * 4 * Copyright (C) 2003-2005 Benjamin Herrenschmuidt (benh@kernel.crashing.org) 5 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13#include <linux/kernel.h> 14#include <linux/pci.h> 15#include <linux/delay.h> 16#include <linux/string.h> 17#include <linux/init.h> 18#include <linux/bootmem.h> 19#include <linux/irq.h> 20 21#include <asm/sections.h> 22#include <asm/io.h> 23#include <asm/prom.h> 24#include <asm/pci-bridge.h> 25#include <asm/machdep.h> 26#include <asm/pmac_feature.h> 27#include <asm/grackle.h> 28#include <asm/ppc-pci.h> 29 30#undef DEBUG 31 32#ifdef DEBUG 33#define DBG(x...) printk(x) 34#else 35#define DBG(x...) 36#endif 37 38static int has_uninorth; 39#ifdef CONFIG_PPC64 40static struct pci_controller *u3_agp; 41#else 42static int has_second_ohare; 43#endif /* CONFIG_PPC64 */ 44 45extern int pcibios_assign_bus_offset; 46 47struct device_node *k2_skiplist[2]; 48 49/* 50 * Magic constants for enabling cache coherency in the bandit/PSX bridge. 51 */ 52#define BANDIT_DEVID_2 8 53#define BANDIT_REVID 3 54 55#define BANDIT_DEVNUM 11 56#define BANDIT_MAGIC 0x50 57#define BANDIT_COHERENT 0x40 58 59static int __init fixup_one_level_bus_range(struct device_node *node, int higher) 60{ 61 for (; node != 0;node = node->sibling) { 62 const int * bus_range; 63 const unsigned int *class_code; 64 int len; 65 66 /* For PCI<->PCI bridges or CardBus bridges, we go down */ 67 class_code = of_get_property(node, "class-code", NULL); 68 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && 69 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) 70 continue; 71 bus_range = of_get_property(node, "bus-range", &len); 72 if (bus_range != NULL && len > 2 * sizeof(int)) { 73 if (bus_range[1] > higher) 74 higher = bus_range[1]; 75 } 76 higher = fixup_one_level_bus_range(node->child, higher); 77 } 78 return higher; 79} 80 81/* This routine fixes the "bus-range" property of all bridges in the 82 * system since they tend to have their "last" member wrong on macs 83 * 84 * Note that the bus numbers manipulated here are OF bus numbers, they 85 * are not Linux bus numbers. 86 */ 87static void __init fixup_bus_range(struct device_node *bridge) 88{ 89 int *bus_range, len; 90 struct property *prop; 91 92 /* Lookup the "bus-range" property for the hose */ 93 prop = of_find_property(bridge, "bus-range", &len); 94 if (prop == NULL || prop->length < 2 * sizeof(int)) 95 return; 96 97 bus_range = prop->value; 98 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]); 99} 100 101/* 102 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers. 103 * 104 * The "Bandit" version is present in all early PCI PowerMacs, 105 * and up to the first ones using Grackle. Some machines may 106 * have 2 bandit controllers (2 PCI busses). 107 * 108 * "Chaos" is used in some "Bandit"-type machines as a bridge 109 * for the separate display bus. It is accessed the same 110 * way as bandit, but cannot be probed for devices. It therefore 111 * has its own config access functions. 112 * 113 * The "UniNorth" version is present in all Core99 machines 114 * (iBook, G4, new IMacs, and all the recent Apple machines). 115 * It contains 3 controllers in one ASIC. 116 * 117 * The U3 is the bridge used on G5 machines. It contains an 118 * AGP bus which is dealt with the old UniNorth access routines 119 * and a HyperTransport bus which uses its own set of access 120 * functions. 121 */ 122 123#define MACRISC_CFA0(devfn, off) \ 124 ((1 << (unsigned int)PCI_SLOT(dev_fn)) \ 125 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \ 126 | (((unsigned int)(off)) & 0xFCUL)) 127 128#define MACRISC_CFA1(bus, devfn, off) \ 129 ((((unsigned int)(bus)) << 16) \ 130 |(((unsigned int)(devfn)) << 8) \ 131 |(((unsigned int)(off)) & 0xFCUL) \ 132 |1UL) 133 134static volatile void __iomem *macrisc_cfg_access(struct pci_controller* hose, 135 u8 bus, u8 dev_fn, u8 offset) 136{ 137 unsigned int caddr; 138 139 if (bus == hose->first_busno) { 140 if (dev_fn < (11 << 3)) 141 return NULL; 142 caddr = MACRISC_CFA0(dev_fn, offset); 143 } else 144 caddr = MACRISC_CFA1(bus, dev_fn, offset); 145 146 /* Uninorth will return garbage if we don't read back the value ! */ 147 do { 148 out_le32(hose->cfg_addr, caddr); 149 } while (in_le32(hose->cfg_addr) != caddr); 150 151 offset &= has_uninorth ? 0x07 : 0x03; 152 return hose->cfg_data + offset; 153} 154 155static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn, 156 int offset, int len, u32 *val) 157{ 158 struct pci_controller *hose; 159 volatile void __iomem *addr; 160 161 hose = pci_bus_to_host(bus); 162 if (hose == NULL) 163 return PCIBIOS_DEVICE_NOT_FOUND; 164 if (offset >= 0x100) 165 return PCIBIOS_BAD_REGISTER_NUMBER; 166 addr = macrisc_cfg_access(hose, bus->number, devfn, offset); 167 if (!addr) 168 return PCIBIOS_DEVICE_NOT_FOUND; 169 /* 170 * Note: the caller has already checked that offset is 171 * suitably aligned and that len is 1, 2 or 4. 172 */ 173 switch (len) { 174 case 1: 175 *val = in_8(addr); 176 break; 177 case 2: 178 *val = in_le16(addr); 179 break; 180 default: 181 *val = in_le32(addr); 182 break; 183 } 184 return PCIBIOS_SUCCESSFUL; 185} 186 187static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn, 188 int offset, int len, u32 val) 189{ 190 struct pci_controller *hose; 191 volatile void __iomem *addr; 192 193 hose = pci_bus_to_host(bus); 194 if (hose == NULL) 195 return PCIBIOS_DEVICE_NOT_FOUND; 196 if (offset >= 0x100) 197 return PCIBIOS_BAD_REGISTER_NUMBER; 198 addr = macrisc_cfg_access(hose, bus->number, devfn, offset); 199 if (!addr) 200 return PCIBIOS_DEVICE_NOT_FOUND; 201 /* 202 * Note: the caller has already checked that offset is 203 * suitably aligned and that len is 1, 2 or 4. 204 */ 205 switch (len) { 206 case 1: 207 out_8(addr, val); 208 break; 209 case 2: 210 out_le16(addr, val); 211 break; 212 default: 213 out_le32(addr, val); 214 break; 215 } 216 return PCIBIOS_SUCCESSFUL; 217} 218 219static struct pci_ops macrisc_pci_ops = 220{ 221 .read = macrisc_read_config, 222 .write = macrisc_write_config, 223}; 224 225#ifdef CONFIG_PPC32 226/* 227 * Verify that a specific (bus, dev_fn) exists on chaos 228 */ 229static int chaos_validate_dev(struct pci_bus *bus, int devfn, int offset) 230{ 231 struct device_node *np; 232 const u32 *vendor, *device; 233 234 if (offset >= 0x100) 235 return PCIBIOS_BAD_REGISTER_NUMBER; 236 np = pci_busdev_to_OF_node(bus, devfn); 237 if (np == NULL) 238 return PCIBIOS_DEVICE_NOT_FOUND; 239 240 vendor = of_get_property(np, "vendor-id", NULL); 241 device = of_get_property(np, "device-id", NULL); 242 if (vendor == NULL || device == NULL) 243 return PCIBIOS_DEVICE_NOT_FOUND; 244 245 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10) 246 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24)) 247 return PCIBIOS_BAD_REGISTER_NUMBER; 248 249 return PCIBIOS_SUCCESSFUL; 250} 251 252static int 253chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 254 int len, u32 *val) 255{ 256 int result = chaos_validate_dev(bus, devfn, offset); 257 if (result == PCIBIOS_BAD_REGISTER_NUMBER) 258 *val = ~0U; 259 if (result != PCIBIOS_SUCCESSFUL) 260 return result; 261 return macrisc_read_config(bus, devfn, offset, len, val); 262} 263 264static int 265chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 266 int len, u32 val) 267{ 268 int result = chaos_validate_dev(bus, devfn, offset); 269 if (result != PCIBIOS_SUCCESSFUL) 270 return result; 271 return macrisc_write_config(bus, devfn, offset, len, val); 272} 273 274static struct pci_ops chaos_pci_ops = 275{ 276 .read = chaos_read_config, 277 .write = chaos_write_config, 278}; 279 280static void __init setup_chaos(struct pci_controller *hose, 281 struct resource *addr) 282{ 283 /* assume a `chaos' bridge */ 284 hose->ops = &chaos_pci_ops; 285 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 286 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 287} 288#endif /* CONFIG_PPC32 */ 289 290#ifdef CONFIG_PPC64 291/* 292 * These versions of U3 HyperTransport config space access ops do not 293 * implement self-view of the HT host yet 294 */ 295 296/* 297 * This function deals with some "special cases" devices. 298 * 299 * 0 -> No special case 300 * 1 -> Skip the device but act as if the access was successfull 301 * (return 0xff's on reads, eventually, cache config space 302 * accesses in a later version) 303 * -1 -> Hide the device (unsuccessful access) 304 */ 305static int u3_ht_skip_device(struct pci_controller *hose, 306 struct pci_bus *bus, unsigned int devfn) 307{ 308 struct device_node *busdn, *dn; 309 int i; 310 311 /* We only allow config cycles to devices that are in OF device-tree 312 * as we are apparently having some weird things going on with some 313 * revs of K2 on recent G5s, except for the host bridge itself, which 314 * is missing from the tree but we know we can probe. 315 */ 316 if (bus->self) 317 busdn = pci_device_to_OF_node(bus->self); 318 else if (devfn == 0) 319 return 0; 320 else 321 busdn = hose->dn; 322 for (dn = busdn->child; dn; dn = dn->sibling) 323 if (PCI_DN(dn) && PCI_DN(dn)->devfn == devfn) 324 break; 325 if (dn == NULL) 326 return -1; 327 328 /* 329 * When a device in K2 is powered down, we die on config 330 * cycle accesses. Fix that here. 331 */ 332 for (i=0; i<2; i++) 333 if (k2_skiplist[i] == dn) 334 return 1; 335 336 return 0; 337} 338 339#define U3_HT_CFA0(devfn, off) \ 340 ((((unsigned int)devfn) << 8) | offset) 341#define U3_HT_CFA1(bus, devfn, off) \ 342 (U3_HT_CFA0(devfn, off) \ 343 + (((unsigned int)bus) << 16) \ 344 + 0x01000000UL) 345 346static void __iomem *u3_ht_cfg_access(struct pci_controller *hose, u8 bus, 347 u8 devfn, u8 offset, int *swap) 348{ 349 *swap = 1; 350 if (bus == hose->first_busno) { 351 if (devfn != 0) 352 return hose->cfg_data + U3_HT_CFA0(devfn, offset); 353 *swap = 0; 354 return ((void __iomem *)hose->cfg_addr) + (offset << 2); 355 } else 356 return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset); 357} 358 359static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, 360 int offset, int len, u32 *val) 361{ 362 struct pci_controller *hose; 363 void __iomem *addr; 364 int swap; 365 366 hose = pci_bus_to_host(bus); 367 if (hose == NULL) 368 return PCIBIOS_DEVICE_NOT_FOUND; 369 if (offset >= 0x100) 370 return PCIBIOS_BAD_REGISTER_NUMBER; 371 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap); 372 if (!addr) 373 return PCIBIOS_DEVICE_NOT_FOUND; 374 375 switch (u3_ht_skip_device(hose, bus, devfn)) { 376 case 0: 377 break; 378 case 1: 379 switch (len) { 380 case 1: 381 *val = 0xff; break; 382 case 2: 383 *val = 0xffff; break; 384 default: 385 *val = 0xfffffffful; break; 386 } 387 return PCIBIOS_SUCCESSFUL; 388 default: 389 return PCIBIOS_DEVICE_NOT_FOUND; 390 } 391 392 /* 393 * Note: the caller has already checked that offset is 394 * suitably aligned and that len is 1, 2 or 4. 395 */ 396 switch (len) { 397 case 1: 398 *val = in_8(addr); 399 break; 400 case 2: 401 *val = swap ? in_le16(addr) : in_be16(addr); 402 break; 403 default: 404 *val = swap ? in_le32(addr) : in_be32(addr); 405 break; 406 } 407 return PCIBIOS_SUCCESSFUL; 408} 409 410static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, 411 int offset, int len, u32 val) 412{ 413 struct pci_controller *hose; 414 void __iomem *addr; 415 int swap; 416 417 hose = pci_bus_to_host(bus); 418 if (hose == NULL) 419 return PCIBIOS_DEVICE_NOT_FOUND; 420 if (offset >= 0x100) 421 return PCIBIOS_BAD_REGISTER_NUMBER; 422 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap); 423 if (!addr) 424 return PCIBIOS_DEVICE_NOT_FOUND; 425 426 switch (u3_ht_skip_device(hose, bus, devfn)) { 427 case 0: 428 break; 429 case 1: 430 return PCIBIOS_SUCCESSFUL; 431 default: 432 return PCIBIOS_DEVICE_NOT_FOUND; 433 } 434 435 /* 436 * Note: the caller has already checked that offset is 437 * suitably aligned and that len is 1, 2 or 4. 438 */ 439 switch (len) { 440 case 1: 441 out_8(addr, val); 442 break; 443 case 2: 444 swap ? out_le16(addr, val) : out_be16(addr, val); 445 break; 446 default: 447 swap ? out_le32(addr, val) : out_be32(addr, val); 448 break; 449 } 450 return PCIBIOS_SUCCESSFUL; 451} 452 453static struct pci_ops u3_ht_pci_ops = 454{ 455 .read = u3_ht_read_config, 456 .write = u3_ht_write_config, 457}; 458 459#define U4_PCIE_CFA0(devfn, off) \ 460 ((1 << ((unsigned int)PCI_SLOT(dev_fn))) \ 461 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \ 462 | ((((unsigned int)(off)) >> 8) << 28) \ 463 | (((unsigned int)(off)) & 0xfcU)) 464 465#define U4_PCIE_CFA1(bus, devfn, off) \ 466 ((((unsigned int)(bus)) << 16) \ 467 |(((unsigned int)(devfn)) << 8) \ 468 | ((((unsigned int)(off)) >> 8) << 28) \ 469 |(((unsigned int)(off)) & 0xfcU) \ 470 |1UL) 471 472static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose, 473 u8 bus, u8 dev_fn, int offset) 474{ 475 unsigned int caddr; 476 477 if (bus == hose->first_busno) { 478 caddr = U4_PCIE_CFA0(dev_fn, offset); 479 } else 480 caddr = U4_PCIE_CFA1(bus, dev_fn, offset); 481 482 /* Uninorth will return garbage if we don't read back the value ! */ 483 do { 484 out_le32(hose->cfg_addr, caddr); 485 } while (in_le32(hose->cfg_addr) != caddr); 486 487 offset &= 0x03; 488 return hose->cfg_data + offset; 489} 490 491static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn, 492 int offset, int len, u32 *val) 493{ 494 struct pci_controller *hose; 495 volatile void __iomem *addr; 496 497 hose = pci_bus_to_host(bus); 498 if (hose == NULL) 499 return PCIBIOS_DEVICE_NOT_FOUND; 500 if (offset >= 0x1000) 501 return PCIBIOS_BAD_REGISTER_NUMBER; 502 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); 503 if (!addr) 504 return PCIBIOS_DEVICE_NOT_FOUND; 505 /* 506 * Note: the caller has already checked that offset is 507 * suitably aligned and that len is 1, 2 or 4. 508 */ 509 switch (len) { 510 case 1: 511 *val = in_8(addr); 512 break; 513 case 2: 514 *val = in_le16(addr); 515 break; 516 default: 517 *val = in_le32(addr); 518 break; 519 } 520 return PCIBIOS_SUCCESSFUL; 521} 522 523static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 524 int offset, int len, u32 val) 525{ 526 struct pci_controller *hose; 527 volatile void __iomem *addr; 528 529 hose = pci_bus_to_host(bus); 530 if (hose == NULL) 531 return PCIBIOS_DEVICE_NOT_FOUND; 532 if (offset >= 0x1000) 533 return PCIBIOS_BAD_REGISTER_NUMBER; 534 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); 535 if (!addr) 536 return PCIBIOS_DEVICE_NOT_FOUND; 537 /* 538 * Note: the caller has already checked that offset is 539 * suitably aligned and that len is 1, 2 or 4. 540 */ 541 switch (len) { 542 case 1: 543 out_8(addr, val); 544 break; 545 case 2: 546 out_le16(addr, val); 547 break; 548 default: 549 out_le32(addr, val); 550 break; 551 } 552 return PCIBIOS_SUCCESSFUL; 553} 554 555static struct pci_ops u4_pcie_pci_ops = 556{ 557 .read = u4_pcie_read_config, 558 .write = u4_pcie_write_config, 559}; 560 561#endif /* CONFIG_PPC64 */ 562 563#ifdef CONFIG_PPC32 564/* 565 * For a bandit bridge, turn on cache coherency if necessary. 566 * N.B. we could clean this up using the hose ops directly. 567 */ 568static void __init init_bandit(struct pci_controller *bp) 569{ 570 unsigned int vendev, magic; 571 int rev; 572 573 /* read the word at offset 0 in config space for device 11 */ 574 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID); 575 udelay(2); 576 vendev = in_le32(bp->cfg_data); 577 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) + 578 PCI_VENDOR_ID_APPLE) { 579 /* read the revision id */ 580 out_le32(bp->cfg_addr, 581 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID); 582 udelay(2); 583 rev = in_8(bp->cfg_data); 584 if (rev != BANDIT_REVID) 585 printk(KERN_WARNING 586 "Unknown revision %d for bandit\n", rev); 587 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) { 588 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev); 589 return; 590 } 591 592 /* read the word at offset 0x50 */ 593 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC); 594 udelay(2); 595 magic = in_le32(bp->cfg_data); 596 if ((magic & BANDIT_COHERENT) != 0) 597 return; 598 magic |= BANDIT_COHERENT; 599 udelay(2); 600 out_le32(bp->cfg_data, magic); 601 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n"); 602} 603 604/* 605 * Tweak the PCI-PCI bridge chip on the blue & white G3s. 606 */ 607static void __init init_p2pbridge(void) 608{ 609 struct device_node *p2pbridge; 610 struct pci_controller* hose; 611 u8 bus, devfn; 612 u16 val; 613 614 p2pbridge = of_find_node_by_name(NULL, "pci-bridge"); 615 if (p2pbridge == NULL 616 || p2pbridge->parent == NULL 617 || strcmp(p2pbridge->parent->name, "pci") != 0) 618 goto done; 619 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) { 620 DBG("Can't find PCI infos for PCI<->PCI bridge\n"); 621 goto done; 622 } 623 /* Warning: At this point, we have not yet renumbered all busses. 624 * So we must use OF walking to find out hose 625 */ 626 hose = pci_find_hose_for_OF_device(p2pbridge); 627 if (!hose) { 628 DBG("Can't find hose for PCI<->PCI bridge\n"); 629 goto done; 630 } 631 if (early_read_config_word(hose, bus, devfn, 632 PCI_BRIDGE_CONTROL, &val) < 0) { 633 printk(KERN_ERR "init_p2pbridge: couldn't read bridge" 634 " control\n"); 635 goto done; 636 } 637 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT; 638 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val); 639done: 640 of_node_put(p2pbridge); 641} 642 643static void __init init_second_ohare(void) 644{ 645 struct device_node *np = of_find_node_by_name(NULL, "pci106b,7"); 646 unsigned char bus, devfn; 647 unsigned short cmd; 648 649 if (np == NULL) 650 return; 651 652 /* This must run before we initialize the PICs since the second 653 * ohare hosts a PIC that will be accessed there. 654 */ 655 if (pci_device_from_OF_node(np, &bus, &devfn) == 0) { 656 struct pci_controller* hose = 657 pci_find_hose_for_OF_device(np); 658 if (!hose) { 659 printk(KERN_ERR "Can't find PCI hose for OHare2 !\n"); 660 of_node_put(np); 661 return; 662 } 663 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd); 664 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 665 cmd &= ~PCI_COMMAND_IO; 666 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd); 667 } 668 has_second_ohare = 1; 669 of_node_put(np); 670} 671 672/* 673 * Some Apple desktop machines have a NEC PD720100A USB2 controller 674 * on the motherboard. Open Firmware, on these, will disable the 675 * EHCI part of it so it behaves like a pair of OHCI's. This fixup 676 * code re-enables it ;) 677 */ 678static void __init fixup_nec_usb2(void) 679{ 680 struct device_node *nec; 681 682 for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) { 683 struct pci_controller *hose; 684 u32 data; 685 const u32 *prop; 686 u8 bus, devfn; 687 688 prop = of_get_property(nec, "vendor-id", NULL); 689 if (prop == NULL) 690 continue; 691 if (0x1033 != *prop) 692 continue; 693 prop = of_get_property(nec, "device-id", NULL); 694 if (prop == NULL) 695 continue; 696 if (0x0035 != *prop) 697 continue; 698 prop = of_get_property(nec, "reg", NULL); 699 if (prop == NULL) 700 continue; 701 devfn = (prop[0] >> 8) & 0xff; 702 bus = (prop[0] >> 16) & 0xff; 703 if (PCI_FUNC(devfn) != 0) 704 continue; 705 hose = pci_find_hose_for_OF_device(nec); 706 if (!hose) 707 continue; 708 early_read_config_dword(hose, bus, devfn, 0xe4, &data); 709 if (data & 1UL) { 710 printk("Found NEC PD720100A USB2 chip with disabled" 711 " EHCI, fixing up...\n"); 712 data &= ~1UL; 713 early_write_config_dword(hose, bus, devfn, 0xe4, data); 714 } 715 } 716} 717 718static void __init setup_bandit(struct pci_controller *hose, 719 struct resource *addr) 720{ 721 hose->ops = ¯isc_pci_ops; 722 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 723 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 724 init_bandit(hose); 725} 726 727static int __init setup_uninorth(struct pci_controller *hose, 728 struct resource *addr) 729{ 730 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); 731 has_uninorth = 1; 732 hose->ops = ¯isc_pci_ops; 733 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 734 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 735 /* We "know" that the bridge at f2000000 has the PCI slots. */ 736 return addr->start == 0xf2000000; 737} 738#endif /* CONFIG_PPC32 */ 739 740#ifdef CONFIG_PPC64 741static void __init setup_u3_agp(struct pci_controller* hose) 742{ 743 /* On G5, we move AGP up to high bus number so we don't need 744 * to reassign bus numbers for HT. If we ever have P2P bridges 745 * on AGP, we'll have to move pci_assign_all_busses to the 746 * pci_controller structure so we enable it for AGP and not for 747 * HT childs. 748 * We hard code the address because of the different size of 749 * the reg address cell, we shall fix that by killing struct 750 * reg_property and using some accessor functions instead 751 */ 752 hose->first_busno = 0xf0; 753 hose->last_busno = 0xff; 754 has_uninorth = 1; 755 hose->ops = ¯isc_pci_ops; 756 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); 757 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); 758 u3_agp = hose; 759} 760 761static void __init setup_u4_pcie(struct pci_controller* hose) 762{ 763 /* We currently only implement the "non-atomic" config space, to 764 * be optimised later. 765 */ 766 hose->ops = &u4_pcie_pci_ops; 767 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); 768 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); 769 770 /* The bus contains a bridge from root -> device, we need to 771 * make it visible on bus 0 so that we pick the right type 772 * of config cycles. If we didn't, we would have to force all 773 * config cycles to be type 1. So we override the "bus-range" 774 * property here 775 */ 776 hose->first_busno = 0x00; 777 hose->last_busno = 0xff; 778} 779 780static void __init parse_region_decode(struct pci_controller *hose, 781 u32 decode) 782{ 783 unsigned long base, end, next = -1; 784 int i, cur = -1; 785 786 /* Iterate through all bits. We ignore the last bit as this region is 787 * reserved for the ROM among other niceties 788 */ 789 for (i = 0; i < 31; i++) { 790 if ((decode & (0x80000000 >> i)) == 0) 791 continue; 792 if (i < 16) { 793 base = 0xf0000000 | (((u32)i) << 24); 794 end = base + 0x00ffffff; 795 } else { 796 base = ((u32)i-16) << 28; 797 end = base + 0x0fffffff; 798 } 799 if (base != next) { 800 if (++cur >= 3) { 801 printk(KERN_WARNING "PCI: Too many ranges !\n"); 802 break; 803 } 804 hose->mem_resources[cur].flags = IORESOURCE_MEM; 805 hose->mem_resources[cur].name = hose->dn->full_name; 806 hose->mem_resources[cur].start = base; 807 hose->mem_resources[cur].end = end; 808 DBG(" %d: 0x%08lx-0x%08lx\n", cur, base, end); 809 } else { 810 DBG(" : -0x%08lx\n", end); 811 hose->mem_resources[cur].end = end; 812 } 813 next = end + 1; 814 } 815} 816 817static void __init setup_u3_ht(struct pci_controller* hose) 818{ 819 struct device_node *np = hose->dn; 820 struct resource cfg_res, self_res; 821 u32 decode; 822 823 hose->ops = &u3_ht_pci_ops; 824 825 /* Get base addresses from OF tree 826 */ 827 if (of_address_to_resource(np, 0, &cfg_res) || 828 of_address_to_resource(np, 1, &self_res)) { 829 printk(KERN_ERR "PCI: Failed to get U3/U4 HT resources !\n"); 830 return; 831 } 832 833 /* Map external cfg space access into cfg_data and self registers 834 * into cfg_addr 835 */ 836 hose->cfg_data = ioremap(cfg_res.start, 0x02000000); 837 hose->cfg_addr = ioremap(self_res.start, 838 self_res.end - self_res.start + 1); 839 840 /* 841 * /ht node doesn't expose a "ranges" property, we read the register 842 * that controls the decoding logic and use that for memory regions. 843 * The IO region is hard coded since it is fixed in HW as well. 844 */ 845 hose->io_base_phys = 0xf4000000; 846 hose->pci_io_size = 0x00400000; 847 hose->io_resource.name = np->full_name; 848 hose->io_resource.start = 0; 849 hose->io_resource.end = 0x003fffff; 850 hose->io_resource.flags = IORESOURCE_IO; 851 hose->pci_mem_offset = 0; 852 hose->first_busno = 0; 853 hose->last_busno = 0xef; 854 855 /* Note: fix offset when cfg_addr becomes a void * */ 856 decode = in_be32(hose->cfg_addr + 0x80); 857 858 DBG("PCI: Apple HT bridge decode register: 0x%08x\n", decode); 859 860 /* NOTE: The decode register setup is a bit weird... region 861 * 0xf8000000 for example is marked as enabled in there while it's 862 & actually the memory controller registers. 863 * That means that we are incorrectly attributing it to HT. 864 * 865 * In a similar vein, region 0xf4000000 is actually the HT IO space but 866 * also marked as enabled in here and 0xf9000000 is used by some other 867 * internal bits of the northbridge. 868 * 869 * Unfortunately, we can't just mask out those bit as we would end 870 * up with more regions than we can cope (linux can only cope with 871 * 3 memory regions for a PHB at this stage). 872 * 873 * So for now, we just do a little hack. We happen to -know- that 874 * Apple firmware doesn't assign things below 0xfa000000 for that 875 * bridge anyway so we mask out all bits we don't want. 876 */ 877 decode &= 0x003fffff; 878 879 /* Now parse the resulting bits and build resources */ 880 parse_region_decode(hose, decode); 881} 882#endif /* CONFIG_PPC64 */ 883 884/* 885 * We assume that if we have a G3 powermac, we have one bridge called 886 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise, 887 * if we have one or more bandit or chaos bridges, we don't have a MPC106. 888 */ 889static int __init pmac_add_bridge(struct device_node *dev) 890{ 891 int len; 892 struct pci_controller *hose; 893 struct resource rsrc; 894 char *disp_name; 895 const int *bus_range; 896 int primary = 1, has_address = 0; 897 898 DBG("Adding PCI host bridge %s\n", dev->full_name); 899 900 /* Fetch host bridge registers address */ 901 has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); 902 903 /* Get bus range if any */ 904 bus_range = of_get_property(dev, "bus-range", &len); 905 if (bus_range == NULL || len < 2 * sizeof(int)) { 906 printk(KERN_WARNING "Can't get bus-range for %s, assume" 907 " bus 0\n", dev->full_name); 908 } 909 910 hose = pcibios_alloc_controller(dev); 911 if (!hose) 912 return -ENOMEM; 913 hose->first_busno = bus_range ? bus_range[0] : 0; 914 hose->last_busno = bus_range ? bus_range[1] : 0xff; 915 916 disp_name = NULL; 917 918 /* 64 bits only bridges */ 919#ifdef CONFIG_PPC64 920 if (of_device_is_compatible(dev, "u3-agp")) { 921 setup_u3_agp(hose); 922 disp_name = "U3-AGP"; 923 primary = 0; 924 } else if (of_device_is_compatible(dev, "u3-ht")) { 925 setup_u3_ht(hose); 926 disp_name = "U3-HT"; 927 primary = 1; 928 } else if (of_device_is_compatible(dev, "u4-pcie")) { 929 setup_u4_pcie(hose); 930 disp_name = "U4-PCIE"; 931 primary = 0; 932 } 933 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number:" 934 " %d->%d\n", disp_name, hose->first_busno, hose->last_busno); 935#endif /* CONFIG_PPC64 */ 936 937 /* 32 bits only bridges */ 938#ifdef CONFIG_PPC32 939 if (of_device_is_compatible(dev, "uni-north")) { 940 primary = setup_uninorth(hose, &rsrc); 941 disp_name = "UniNorth"; 942 } else if (strcmp(dev->name, "pci") == 0) { 943 setup_grackle(hose); 944 disp_name = "Grackle (MPC106)"; 945 } else if (strcmp(dev->name, "bandit") == 0) { 946 setup_bandit(hose, &rsrc); 947 disp_name = "Bandit"; 948 } else if (strcmp(dev->name, "chaos") == 0) { 949 setup_chaos(hose, &rsrc); 950 disp_name = "Chaos"; 951 primary = 0; 952 } 953 printk(KERN_INFO "Found %s PCI host bridge at 0x%016llx. " 954 "Firmware bus number: %d->%d\n", 955 disp_name, (unsigned long long)rsrc.start, hose->first_busno, 956 hose->last_busno); 957#endif /* CONFIG_PPC32 */ 958 959 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 960 hose, hose->cfg_addr, hose->cfg_data); 961 962 /* Interpret the "ranges" property */ 963 /* This also maps the I/O region and sets isa_io/mem_base */ 964 pci_process_bridge_OF_ranges(hose, dev, primary); 965 966 /* Fixup "bus-range" OF property */ 967 fixup_bus_range(dev); 968 969 return 0; 970} 971 972void __devinit pmac_pci_irq_fixup(struct pci_dev *dev) 973{ 974#ifdef CONFIG_PPC32 975 /* Fixup interrupt for the modem/ethernet combo controller. 976 * on machines with a second ohare chip. 977 * The number in the device tree (27) is bogus (correct for 978 * the ethernet-only board but not the combo ethernet/modem 979 * board). The real interrupt is 28 on the second controller 980 * -> 28+32 = 60. 981 */ 982 if (has_second_ohare && 983 dev->vendor == PCI_VENDOR_ID_DEC && 984 dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS) { 985 dev->irq = irq_create_mapping(NULL, 60); 986 set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); 987 } 988#endif /* CONFIG_PPC32 */ 989} 990 991void __init pmac_pci_init(void) 992{ 993 struct device_node *np, *root; 994 struct device_node *ht = NULL; 995 996 ppc_pci_set_flags(PPC_PCI_CAN_SKIP_ISA_ALIGN); 997 998 root = of_find_node_by_path("/"); 999 if (root == NULL) { 1000 printk(KERN_CRIT "pmac_pci_init: can't find root " 1001 "of device tree\n"); 1002 return; 1003 } 1004 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) { 1005 if (np->name == NULL) 1006 continue; 1007 if (strcmp(np->name, "bandit") == 0 1008 || strcmp(np->name, "chaos") == 0 1009 || strcmp(np->name, "pci") == 0) { 1010 if (pmac_add_bridge(np) == 0) 1011 of_node_get(np); 1012 } 1013 if (strcmp(np->name, "ht") == 0) { 1014 of_node_get(np); 1015 ht = np; 1016 } 1017 } 1018 of_node_put(root); 1019 1020#ifdef CONFIG_PPC64 1021 /* Probe HT last as it relies on the agp resources to be already 1022 * setup 1023 */ 1024 if (ht && pmac_add_bridge(ht) != 0) 1025 of_node_put(ht); 1026 1027 /* Setup the linkage between OF nodes and PHBs */ 1028 pci_devs_phb_init(); 1029 1030 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We 1031 * assume there is no P2P bridge on the AGP bus, which should be a 1032 * safe assumptions for now. We should do something better in the 1033 * future though 1034 */ 1035 if (u3_agp) { 1036 struct device_node *np = u3_agp->dn; 1037 PCI_DN(np)->busno = 0xf0; 1038 for (np = np->child; np; np = np->sibling) 1039 PCI_DN(np)->busno = 0xf0; 1040 } 1041 /* pmac_check_ht_link(); */ 1042 1043 /* We can allocate missing resources if any */ 1044 pci_probe_only = 0; 1045 1046#else /* CONFIG_PPC64 */ 1047 init_p2pbridge(); 1048 init_second_ohare(); 1049 fixup_nec_usb2(); 1050 1051 /* We are still having some issues with the Xserve G4, enabling 1052 * some offset between bus number and domains for now when we 1053 * assign all busses should help for now 1054 */ 1055 if (ppc_pci_has_flag(PPC_PCI_REASSIGN_ALL_BUS)) 1056 pcibios_assign_bus_offset = 0x10; 1057#endif 1058} 1059 1060#ifdef CONFIG_PPC32 1061int pmac_pci_enable_device_hook(struct pci_dev *dev) 1062{ 1063 struct device_node* node; 1064 int updatecfg = 0; 1065 int uninorth_child; 1066 1067 node = pci_device_to_OF_node(dev); 1068 1069 /* We don't want to enable USB controllers absent from the OF tree 1070 * (iBook second controller) 1071 */ 1072 if (dev->vendor == PCI_VENDOR_ID_APPLE 1073 && dev->class == PCI_CLASS_SERIAL_USB_OHCI 1074 && !node) { 1075 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n", 1076 pci_name(dev)); 1077 return -EINVAL; 1078 } 1079 1080 if (!node) 1081 return 0; 1082 1083 uninorth_child = node->parent && 1084 of_device_is_compatible(node->parent, "uni-north"); 1085 1086 /* Firewire & GMAC were disabled after PCI probe, the driver is 1087 * claiming them, we must re-enable them now. 1088 */ 1089 if (uninorth_child && !strcmp(node->name, "firewire") && 1090 (of_device_is_compatible(node, "pci106b,18") || 1091 of_device_is_compatible(node, "pci106b,30") || 1092 of_device_is_compatible(node, "pci11c1,5811"))) { 1093 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1); 1094 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1); 1095 updatecfg = 1; 1096 } 1097 if (uninorth_child && !strcmp(node->name, "ethernet") && 1098 of_device_is_compatible(node, "gmac")) { 1099 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1); 1100 updatecfg = 1; 1101 } 1102 1103 /* 1104 * Fixup various header fields on 32 bits. We don't do that on 1105 * 64 bits as some of these have strange values behind the HT 1106 * bridge and we must not, for example, enable MWI or set the 1107 * cache line size on them. 1108 */ 1109 if (updatecfg) { 1110 u16 cmd; 1111 1112 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1113 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER 1114 | PCI_COMMAND_INVALIDATE; 1115 pci_write_config_word(dev, PCI_COMMAND, cmd); 1116 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16); 1117 1118 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 1119 L1_CACHE_BYTES >> 2); 1120 } 1121 1122 return 0; 1123} 1124 1125void __devinit pmac_pci_fixup_ohci(struct pci_dev *dev) 1126{ 1127 struct device_node *node = pci_device_to_OF_node(dev); 1128 1129 /* We don't want to assign resources to USB controllers 1130 * absent from the OF tree (iBook second controller) 1131 */ 1132 if (dev->class == PCI_CLASS_SERIAL_USB_OHCI && !node) 1133 dev->resource[0].flags = 0; 1134} 1135DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, PCI_ANY_ID, pmac_pci_fixup_ohci); 1136 1137/* We power down some devices after they have been probed. They'll 1138 * be powered back on later on 1139 */ 1140void __init pmac_pcibios_after_init(void) 1141{ 1142 struct device_node* nd; 1143 1144 for_each_node_by_name(nd, "firewire") { 1145 if (nd->parent && (of_device_is_compatible(nd, "pci106b,18") || 1146 of_device_is_compatible(nd, "pci106b,30") || 1147 of_device_is_compatible(nd, "pci11c1,5811")) 1148 && of_device_is_compatible(nd->parent, "uni-north")) { 1149 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0); 1150 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0); 1151 } 1152 } 1153 for_each_node_by_name(nd, "ethernet") { 1154 if (nd->parent && of_device_is_compatible(nd, "gmac") 1155 && of_device_is_compatible(nd->parent, "uni-north")) 1156 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0); 1157 } 1158} 1159 1160void pmac_pci_fixup_cardbus(struct pci_dev* dev) 1161{ 1162 if (!machine_is(powermac)) 1163 return; 1164 /* 1165 * Fix the interrupt routing on the various cardbus bridges 1166 * used on powerbooks 1167 */ 1168 if (dev->vendor != PCI_VENDOR_ID_TI) 1169 return; 1170 if (dev->device == PCI_DEVICE_ID_TI_1130 || 1171 dev->device == PCI_DEVICE_ID_TI_1131) { 1172 u8 val; 1173 /* Enable PCI interrupt */ 1174 if (pci_read_config_byte(dev, 0x91, &val) == 0) 1175 pci_write_config_byte(dev, 0x91, val | 0x30); 1176 /* Disable ISA interrupt mode */ 1177 if (pci_read_config_byte(dev, 0x92, &val) == 0) 1178 pci_write_config_byte(dev, 0x92, val & ~0x06); 1179 } 1180 if (dev->device == PCI_DEVICE_ID_TI_1210 || 1181 dev->device == PCI_DEVICE_ID_TI_1211 || 1182 dev->device == PCI_DEVICE_ID_TI_1410 || 1183 dev->device == PCI_DEVICE_ID_TI_1510) { 1184 u8 val; 1185 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA 1186 signal out the MFUNC0 pin */ 1187 if (pci_read_config_byte(dev, 0x8c, &val) == 0) 1188 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2); 1189 /* Disable ISA interrupt mode */ 1190 if (pci_read_config_byte(dev, 0x92, &val) == 0) 1191 pci_write_config_byte(dev, 0x92, val & ~0x06); 1192 } 1193} 1194 1195DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus); 1196 1197void pmac_pci_fixup_pciata(struct pci_dev* dev) 1198{ 1199 u8 progif = 0; 1200 1201 /* 1202 * On PowerMacs, we try to switch any PCI ATA controller to 1203 * fully native mode 1204 */ 1205 if (!machine_is(powermac)) 1206 return; 1207 1208 /* Some controllers don't have the class IDE */ 1209 if (dev->vendor == PCI_VENDOR_ID_PROMISE) 1210 switch(dev->device) { 1211 case PCI_DEVICE_ID_PROMISE_20246: 1212 case PCI_DEVICE_ID_PROMISE_20262: 1213 case PCI_DEVICE_ID_PROMISE_20263: 1214 case PCI_DEVICE_ID_PROMISE_20265: 1215 case PCI_DEVICE_ID_PROMISE_20267: 1216 case PCI_DEVICE_ID_PROMISE_20268: 1217 case PCI_DEVICE_ID_PROMISE_20269: 1218 case PCI_DEVICE_ID_PROMISE_20270: 1219 case PCI_DEVICE_ID_PROMISE_20271: 1220 case PCI_DEVICE_ID_PROMISE_20275: 1221 case PCI_DEVICE_ID_PROMISE_20276: 1222 case PCI_DEVICE_ID_PROMISE_20277: 1223 goto good; 1224 } 1225 /* Others, check PCI class */ 1226 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) 1227 return; 1228 good: 1229 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1230 if ((progif & 5) != 5) { 1231 printk(KERN_INFO "PCI: %s Forcing PCI IDE into native mode\n", 1232 pci_name(dev)); 1233 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); 1234 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || 1235 (progif & 5) != 5) 1236 printk(KERN_ERR "Rewrite of PROGIF failed !\n"); 1237 else { 1238 /* Clear IO BARs, they will be reassigned */ 1239 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0); 1240 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0); 1241 pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, 0); 1242 pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, 0); 1243 } 1244 } 1245} 1246DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata); 1247#endif /* CONFIG_PPC32 */ 1248 1249/* 1250 * Disable second function on K2-SATA, it's broken 1251 * and disable IO BARs on first one 1252 */ 1253static void fixup_k2_sata(struct pci_dev* dev) 1254{ 1255 int i; 1256 u16 cmd; 1257 1258 if (PCI_FUNC(dev->devfn) > 0) { 1259 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1260 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 1261 pci_write_config_word(dev, PCI_COMMAND, cmd); 1262 for (i = 0; i < 6; i++) { 1263 dev->resource[i].start = dev->resource[i].end = 0; 1264 dev->resource[i].flags = 0; 1265 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 1266 0); 1267 } 1268 } else { 1269 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1270 cmd &= ~PCI_COMMAND_IO; 1271 pci_write_config_word(dev, PCI_COMMAND, cmd); 1272 for (i = 0; i < 5; i++) { 1273 dev->resource[i].start = dev->resource[i].end = 0; 1274 dev->resource[i].flags = 0; 1275 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 1276 0); 1277 } 1278 } 1279} 1280DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata); 1281 1282/* 1283 * On U4 (aka CPC945) the PCIe root complex "P2P" bridge resource ranges aren't 1284 * configured by the firmware. The bridge itself seems to ignore them but it 1285 * causes problems with Linux which then re-assigns devices below the bridge, 1286 * thus changing addresses of those devices from what was in the device-tree, 1287 * which sucks when those are video cards using offb 1288 * 1289 * We could just mark it transparent but I prefer fixing up the resources to 1290 * properly show what's going on here, as I have some doubts about having them 1291 * badly configured potentially being an issue for DMA. 1292 * 1293 * We leave PIO alone, it seems to be fine 1294 * 1295 * Oh and there's another funny bug. The OF properties advertize the region 1296 * 0xf1000000..0xf1ffffff as being forwarded as memory space. But that's 1297 * actually not true, this region is the memory mapped config space. So we 1298 * also need to filter it out or we'll map things in the wrong place. 1299 */ 1300static void fixup_u4_pcie(struct pci_dev* dev) 1301{ 1302 struct pci_controller *host = pci_bus_to_host(dev->bus); 1303 struct resource *region = NULL; 1304 u32 reg; 1305 int i; 1306 1307 /* Only do that on PowerMac */ 1308 if (!machine_is(powermac)) 1309 return; 1310 1311 /* Find the largest MMIO region */ 1312 for (i = 0; i < 3; i++) { 1313 struct resource *r = &host->mem_resources[i]; 1314 if (!(r->flags & IORESOURCE_MEM)) 1315 continue; 1316 /* Skip the 0xf0xxxxxx..f2xxxxxx regions, we know they 1317 * are reserved by HW for other things 1318 */ 1319 if (r->start >= 0xf0000000 && r->start < 0xf3000000) 1320 continue; 1321 if (!region || (r->end - r->start) > 1322 (region->end - region->start)) 1323 region = r; 1324 } 1325 /* Nothing found, bail */ 1326 if (region == 0) 1327 return; 1328 1329 /* Print things out */ 1330 printk(KERN_INFO "PCI: Fixup U4 PCIe bridge range: %pR\n", region); 1331 1332 /* Fixup bridge config space. We know it's a Mac, resource aren't 1333 * offset so let's just blast them as-is. We also know that they 1334 * fit in 32 bits 1335 */ 1336 reg = ((region->start >> 16) & 0xfff0) | (region->end & 0xfff00000); 1337 pci_write_config_dword(dev, PCI_MEMORY_BASE, reg); 1338 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0); 1339 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0); 1340 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0); 1341} 1342DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_U4_PCIE, fixup_u4_pcie); 1343