1/** 2 * MPC86xx Internal Memory Map 3 * 4 * Authors: Jeff Brown 5 * Timur Tabi <timur@freescale.com> 6 * 7 * Copyright 2004,2007 Freescale Semiconductor, Inc 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * This header file defines structures for various 86xx SOC devices that are 15 * used by multiple source files. 16 */ 17 18#ifndef __ASM_POWERPC_IMMAP_86XX_H__ 19#define __ASM_POWERPC_IMMAP_86XX_H__ 20#ifdef __KERNEL__ 21 22/* Global Utility Registers */ 23struct ccsr_guts { 24 __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ 25 __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ 26 __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */ 27 __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */ 28 __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ 29 u8 res1[0x20 - 0x14]; 30 __be32 porcir; /* 0x.0020 - POR Configuration Information Register */ 31 u8 res2[0x30 - 0x24]; 32 __be32 gpiocr; /* 0x.0030 - GPIO Control Register */ 33 u8 res3[0x40 - 0x34]; 34 __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */ 35 u8 res4[0x50 - 0x44]; 36 __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */ 37 u8 res5[0x60 - 0x54]; 38 __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */ 39 u8 res6[0x70 - 0x64]; 40 __be32 devdisr; /* 0x.0070 - Device Disable Control */ 41 __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */ 42 u8 res7[0x80 - 0x78]; 43 __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */ 44 u8 res8[0x90 - 0x84]; 45 __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */ 46 __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */ 47 u8 res9[0xA0 - 0x98]; 48 __be32 pvr; /* 0x.00a0 - Processor Version Register */ 49 __be32 svr; /* 0x.00a4 - System Version Register */ 50 u8 res10[0xB0 - 0xA8]; 51 __be32 rstcr; /* 0x.00b0 - Reset Control Register */ 52 u8 res11[0xC0 - 0xB4]; 53 __be32 elbcvselcr; /* 0x.00c0 - eLBC Voltage Select Ctrl Reg */ 54 u8 res12[0x800 - 0xC4]; 55 __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */ 56 u8 res13[0x900 - 0x804]; 57 __be32 ircr; /* 0x.0900 - Infrared Control Register */ 58 u8 res14[0x908 - 0x904]; 59 __be32 dmacr; /* 0x.0908 - DMA Control Register */ 60 u8 res15[0x914 - 0x90C]; 61 __be32 elbccr; /* 0x.0914 - eLBC Control Register */ 62 u8 res16[0xB20 - 0x918]; 63 __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */ 64 __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */ 65 __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */ 66 u8 res17[0xE00 - 0xB2C]; 67 __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */ 68 u8 res18[0xE10 - 0xE04]; 69 __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */ 70 u8 res19[0xE20 - 0xE14]; 71 __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */ 72 u8 res20[0xF04 - 0xE24]; 73 __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */ 74 __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */ 75 u8 res21[0xF40 - 0xF0C]; 76 __be32 srds2cr0; /* 0x.0f40 - SerDes1 Control Register 0 */ 77 __be32 srds2cr1; /* 0x.0f44 - SerDes1 Control Register 0 */ 78} __attribute__ ((packed)); 79 80#define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */ 81#define CCSR_GUTS_DMACR_DEV_IR 1 /* DMA controller/channel set to IR */ 82 83/* 84 * Set the DMACR register in the GUTS 85 * 86 * The DMACR register determines the source of initiated transfers for each 87 * channel on each DMA controller. Rather than have a bunch of repetitive 88 * macros for the bit patterns, we just have a function that calculates 89 * them. 90 * 91 * guts: Pointer to GUTS structure 92 * co: The DMA controller (0 or 1) 93 * ch: The channel on the DMA controller (0, 1, 2, or 3) 94 * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx) 95 */ 96static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts, 97 unsigned int co, unsigned int ch, unsigned int device) 98{ 99 unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch)); 100 101 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift); 102} 103 104#define CCSR_GUTS_PMUXCR_LDPSEL 0x00010000 105#define CCSR_GUTS_PMUXCR_SSI1_MASK 0x0000C000 /* Bitmask for SSI1 */ 106#define CCSR_GUTS_PMUXCR_SSI1_LA 0x00000000 /* Latched address */ 107#define CCSR_GUTS_PMUXCR_SSI1_HI 0x00004000 /* High impedance */ 108#define CCSR_GUTS_PMUXCR_SSI1_SSI 0x00008000 /* Used for SSI1 */ 109#define CCSR_GUTS_PMUXCR_SSI2_MASK 0x00003000 /* Bitmask for SSI2 */ 110#define CCSR_GUTS_PMUXCR_SSI2_LA 0x00000000 /* Latched address */ 111#define CCSR_GUTS_PMUXCR_SSI2_HI 0x00001000 /* High impedance */ 112#define CCSR_GUTS_PMUXCR_SSI2_SSI 0x00002000 /* Used for SSI2 */ 113#define CCSR_GUTS_PMUXCR_LA_22_25_LA 0x00000000 /* Latched Address */ 114#define CCSR_GUTS_PMUXCR_LA_22_25_HI 0x00000400 /* High impedance */ 115#define CCSR_GUTS_PMUXCR_DBGDRV 0x00000200 /* Signals not driven */ 116#define CCSR_GUTS_PMUXCR_DMA2_0 0x00000008 117#define CCSR_GUTS_PMUXCR_DMA2_3 0x00000004 118#define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002 119#define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001 120 121/* 122 * Set the DMA external control bits in the GUTS 123 * 124 * The DMA external control bits in the PMUXCR are only meaningful for 125 * channels 0 and 3. Any other channels are ignored. 126 * 127 * guts: Pointer to GUTS structure 128 * co: The DMA controller (0 or 1) 129 * ch: The channel on the DMA controller (0, 1, 2, or 3) 130 * value: the new value for the bit (0 or 1) 131 */ 132static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts, 133 unsigned int co, unsigned int ch, unsigned int value) 134{ 135 if ((ch == 0) || (ch == 3)) { 136 unsigned int shift = 2 * (co + 1) - (ch & 1) - 1; 137 138 clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift); 139 } 140} 141 142#define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000 143#define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000 144#define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000 145#define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25 146#define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK 0x06000000 147#define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \ 148 (((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT) 149#define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT 16 150#define CCSR_GUTS_CLKDVDR_PXCLK_MASK 0x001F0000 151#define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT) 152#define CCSR_GUTS_CLKDVDR_SSICLK_MASK 0x000000FF 153#define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK) 154 155#endif /* __ASM_POWERPC_IMMAP_86XX_H__ */ 156#endif /* __KERNEL__ */ 157