1/* 2 * arch/powerpc/boot/wii-head.S 3 * 4 * Nintendo Wii bootwrapper entry. 5 * Copyright (C) 2008-2009 The GameCube Linux Team 6 * Copyright (C) 2008,2009 Albert Herranz 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 2 11 * of the License, or (at your option) any later version. 12 * 13 */ 14 15#include "ppc_asm.h" 16 17/* 18 * The entry code does no assumptions regarding: 19 * - if the data and instruction caches are enabled or not 20 * - if the MMU is enabled or not 21 * - if the high BATs are enabled or not 22 * 23 * We enable the high BATs, enable the caches if not already enabled, 24 * enable the MMU with an identity mapping scheme and jump to the start code. 25 */ 26 27 .text 28 29 .globl _zimage_start 30_zimage_start: 31 32 /* turn the MMU off */ 33 mfmsr 9 34 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */ 35 bcl 20, 31, 1f 361: 37 mflr 8 38 clrlwi 8, 8, 3 /* convert to a real address */ 39 addi 8, 8, _mmu_off - 1b 40 mtsrr0 8 41 mtsrr1 9 42 rfi 43_mmu_off: 44 /* MMU disabled */ 45 46 /* setup BATs */ 47 isync 48 li 8, 0 49 mtspr 0x210, 8 /* IBAT0U */ 50 mtspr 0x212, 8 /* IBAT1U */ 51 mtspr 0x214, 8 /* IBAT2U */ 52 mtspr 0x216, 8 /* IBAT3U */ 53 mtspr 0x218, 8 /* DBAT0U */ 54 mtspr 0x21a, 8 /* DBAT1U */ 55 mtspr 0x21c, 8 /* DBAT2U */ 56 mtspr 0x21e, 8 /* DBAT3U */ 57 58 mtspr 0x230, 8 /* IBAT4U */ 59 mtspr 0x232, 8 /* IBAT5U */ 60 mtspr 0x234, 8 /* IBAT6U */ 61 mtspr 0x236, 8 /* IBAT7U */ 62 mtspr 0x238, 8 /* DBAT4U */ 63 mtspr 0x23a, 8 /* DBAT5U */ 64 mtspr 0x23c, 8 /* DBAT6U */ 65 mtspr 0x23e, 8 /* DBAT7U */ 66 67 li 8, 0x01ff /* first 16MiB */ 68 li 9, 0x0002 /* rw */ 69 mtspr 0x211, 9 /* IBAT0L */ 70 mtspr 0x210, 8 /* IBAT0U */ 71 mtspr 0x219, 9 /* DBAT0L */ 72 mtspr 0x218, 8 /* DBAT0U */ 73 74 lis 8, 0x0c00 /* I/O mem */ 75 ori 8, 8, 0x3ff /* 32MiB */ 76 lis 9, 0x0c00 77 ori 9, 9, 0x002a /* uncached, guarded, rw */ 78 mtspr 0x21b, 9 /* DBAT1L */ 79 mtspr 0x21a, 8 /* DBAT1U */ 80 81 lis 8, 0x0100 /* next 8MiB */ 82 ori 8, 8, 0x00ff /* 8MiB */ 83 lis 9, 0x0100 84 ori 9, 9, 0x0002 /* rw */ 85 mtspr 0x215, 9 /* IBAT2L */ 86 mtspr 0x214, 8 /* IBAT2U */ 87 mtspr 0x21d, 9 /* DBAT2L */ 88 mtspr 0x21c, 8 /* DBAT2U */ 89 90 lis 8, 0x1000 /* MEM2 */ 91 ori 8, 8, 0x07ff /* 64MiB */ 92 lis 9, 0x1000 93 ori 9, 9, 0x0002 /* rw */ 94 mtspr 0x216, 8 /* IBAT3U */ 95 mtspr 0x217, 9 /* IBAT3L */ 96 mtspr 0x21e, 8 /* DBAT3U */ 97 mtspr 0x21f, 9 /* DBAT3L */ 98 99 /* enable the high BATs */ 100 mfspr 8, 0x3f3 /* HID4 */ 101 oris 8, 8, 0x0200 102 mtspr 0x3f3, 8 /* HID4 */ 103 104 /* enable and invalidate the caches if not already enabled */ 105 mfspr 8, 0x3f0 /* HID0 */ 106 andi. 0, 8, (1<<15) /* HID0_ICE */ 107 bne 1f 108 ori 8, 8, (1<<15)|(1<<11) /* HID0_ICE|HID0_ICFI*/ 1091: 110 andi. 0, 8, (1<<14) /* HID0_DCE */ 111 bne 1f 112 ori 8, 8, (1<<14)|(1<<10) /* HID0_DCE|HID0_DCFI*/ 1131: 114 mtspr 0x3f0, 8 /* HID0 */ 115 isync 116 117 /* initialize arguments */ 118 li 3, 0 119 li 4, 0 120 li 5, 0 121 122 /* turn the MMU on */ 123 bcl 20, 31, 1f 1241: 125 mflr 8 126 addi 8, 8, _mmu_on - 1b 127 mfmsr 9 128 ori 9, 9, (1<<4)|(1<<5) /* MSR_DR|MSR_IR */ 129 mtsrr0 8 130 mtsrr1 9 131 sync 132 rfi 133_mmu_on: 134 /* turn on the front blue led (aka: yay! we got here!) */ 135 lis 8, 0x0d00 136 ori 8, 8, 0x00c0 137 lwz 9, 0(8) 138 ori 9, 9, 0x20 139 stw 9, 0(8) 140 141 b _zimage_start_lib 142