1/* 2 * Code to handle x86 style IRQs plus some generic interrupt stuff. 3 * 4 * Copyright (C) 1992 Linus Torvalds 5 * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle 6 * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org) 7 * Copyright (C) 1999-2000 Grant Grundler 8 * Copyright (c) 2005 Matthew Wilcox 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2, or (at your option) 13 * any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24#include <linux/bitops.h> 25#include <linux/errno.h> 26#include <linux/init.h> 27#include <linux/interrupt.h> 28#include <linux/kernel_stat.h> 29#include <linux/seq_file.h> 30#include <linux/spinlock.h> 31#include <linux/types.h> 32#include <asm/io.h> 33 34#include <asm/smp.h> 35 36#undef PARISC_IRQ_CR16_COUNTS 37 38extern irqreturn_t timer_interrupt(int, void *); 39extern irqreturn_t ipi_interrupt(int, void *); 40 41#define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq)) 42 43/* Bits in EIEM correlate with cpu_irq_action[]. 44** Numbered *Big Endian*! (ie bit 0 is MSB) 45*/ 46static volatile unsigned long cpu_eiem = 0; 47 48/* 49** local ACK bitmap ... habitually set to 1, but reset to zero 50** between ->ack() and ->end() of the interrupt to prevent 51** re-interruption of a processing interrupt. 52*/ 53static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL; 54 55static void cpu_disable_irq(unsigned int irq) 56{ 57 unsigned long eirr_bit = EIEM_MASK(irq); 58 59 cpu_eiem &= ~eirr_bit; 60 /* Do nothing on the other CPUs. If they get this interrupt, 61 * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't 62 * handle it, and the set_eiem() at the bottom will ensure it 63 * then gets disabled */ 64} 65 66static void cpu_enable_irq(unsigned int irq) 67{ 68 unsigned long eirr_bit = EIEM_MASK(irq); 69 70 cpu_eiem |= eirr_bit; 71 72 /* This is just a simple NOP IPI. But what it does is cause 73 * all the other CPUs to do a set_eiem(cpu_eiem) at the end 74 * of the interrupt handler */ 75 smp_send_all_nop(); 76} 77 78static unsigned int cpu_startup_irq(unsigned int irq) 79{ 80 cpu_enable_irq(irq); 81 return 0; 82} 83 84void no_ack_irq(unsigned int irq) { } 85void no_end_irq(unsigned int irq) { } 86 87void cpu_ack_irq(unsigned int irq) 88{ 89 unsigned long mask = EIEM_MASK(irq); 90 int cpu = smp_processor_id(); 91 92 /* Clear in EIEM so we can no longer process */ 93 per_cpu(local_ack_eiem, cpu) &= ~mask; 94 95 /* disable the interrupt */ 96 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu)); 97 98 /* and now ack it */ 99 mtctl(mask, 23); 100} 101 102void cpu_end_irq(unsigned int irq) 103{ 104 unsigned long mask = EIEM_MASK(irq); 105 int cpu = smp_processor_id(); 106 107 /* set it in the eiems---it's no longer in process */ 108 per_cpu(local_ack_eiem, cpu) |= mask; 109 110 /* enable the interrupt */ 111 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu)); 112} 113 114#ifdef CONFIG_SMP 115int cpu_check_affinity(unsigned int irq, const struct cpumask *dest) 116{ 117 int cpu_dest; 118 119 /* timer and ipi have to always be received on all CPUs */ 120 if (CHECK_IRQ_PER_CPU(irq)) { 121 /* Bad linux design decision. The mask has already 122 * been set; we must reset it */ 123 cpumask_setall(irq_desc[irq].affinity); 124 return -EINVAL; 125 } 126 127 /* whatever mask they set, we just allow one CPU */ 128 cpu_dest = first_cpu(*dest); 129 130 return cpu_dest; 131} 132 133static int cpu_set_affinity_irq(unsigned int irq, const struct cpumask *dest) 134{ 135 int cpu_dest; 136 137 cpu_dest = cpu_check_affinity(irq, dest); 138 if (cpu_dest < 0) 139 return -1; 140 141 cpumask_copy(irq_desc[irq].affinity, dest); 142 143 return 0; 144} 145#endif 146 147static struct irq_chip cpu_interrupt_type = { 148 .name = "CPU", 149 .startup = cpu_startup_irq, 150 .shutdown = cpu_disable_irq, 151 .enable = cpu_enable_irq, 152 .disable = cpu_disable_irq, 153 .ack = cpu_ack_irq, 154 .end = cpu_end_irq, 155#ifdef CONFIG_SMP 156 .set_affinity = cpu_set_affinity_irq, 157#endif 158 .retrigger = NULL, 159}; 160 161int show_interrupts(struct seq_file *p, void *v) 162{ 163 int i = *(loff_t *) v, j; 164 unsigned long flags; 165 166 if (i == 0) { 167 seq_puts(p, " "); 168 for_each_online_cpu(j) 169 seq_printf(p, " CPU%d", j); 170 171#ifdef PARISC_IRQ_CR16_COUNTS 172 seq_printf(p, " [min/avg/max] (CPU cycle counts)"); 173#endif 174 seq_putc(p, '\n'); 175 } 176 177 if (i < NR_IRQS) { 178 struct irqaction *action; 179 180 raw_spin_lock_irqsave(&irq_desc[i].lock, flags); 181 action = irq_desc[i].action; 182 if (!action) 183 goto skip; 184 seq_printf(p, "%3d: ", i); 185#ifdef CONFIG_SMP 186 for_each_online_cpu(j) 187 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); 188#else 189 seq_printf(p, "%10u ", kstat_irqs(i)); 190#endif 191 192 seq_printf(p, " %14s", irq_desc[i].chip->name); 193#ifndef PARISC_IRQ_CR16_COUNTS 194 seq_printf(p, " %s", action->name); 195 196 while ((action = action->next)) 197 seq_printf(p, ", %s", action->name); 198#else 199 for ( ;action; action = action->next) { 200 unsigned int k, avg, min, max; 201 202 min = max = action->cr16_hist[0]; 203 204 for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) { 205 int hist = action->cr16_hist[k]; 206 207 if (hist) { 208 avg += hist; 209 } else 210 break; 211 212 if (hist > max) max = hist; 213 if (hist < min) min = hist; 214 } 215 216 avg /= k; 217 seq_printf(p, " %s[%d/%d/%d]", action->name, 218 min,avg,max); 219 } 220#endif 221 222 seq_putc(p, '\n'); 223 skip: 224 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); 225 } 226 227 return 0; 228} 229 230 231 232/* 233** The following form a "set": Virtual IRQ, Transaction Address, Trans Data. 234** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit. 235** 236** To use txn_XXX() interfaces, get a Virtual IRQ first. 237** Then use that to get the Transaction address and data. 238*/ 239 240int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data) 241{ 242 if (irq_desc[irq].action) 243 return -EBUSY; 244 if (irq_desc[irq].chip != &cpu_interrupt_type) 245 return -EBUSY; 246 247 if (type) { 248 irq_desc[irq].chip = type; 249 irq_desc[irq].chip_data = data; 250 cpu_interrupt_type.enable(irq); 251 } 252 return 0; 253} 254 255int txn_claim_irq(int irq) 256{ 257 return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq; 258} 259 260/* 261 * The bits_wide parameter accommodates the limitations of the HW/SW which 262 * use these bits: 263 * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register) 264 * V-class (EPIC): 6 bits 265 * N/L/A-class (iosapic): 8 bits 266 * PCI 2.2 MSI: 16 bits 267 * Some PCI devices: 32 bits (Symbios SCSI/ATM/HyperFabric) 268 * 269 * On the service provider side: 270 * o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register) 271 * o PA 2.0 wide mode 6-bits (per processor) 272 * o IA64 8-bits (0-256 total) 273 * 274 * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported 275 * by the processor...and the N/L-class I/O subsystem supports more bits than 276 * PA2.0 has. The first case is the problem. 277 */ 278int txn_alloc_irq(unsigned int bits_wide) 279{ 280 int irq; 281 282 /* never return irq 0 cause that's the interval timer */ 283 for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) { 284 if (cpu_claim_irq(irq, NULL, NULL) < 0) 285 continue; 286 if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide)) 287 continue; 288 return irq; 289 } 290 291 /* unlikely, but be prepared */ 292 return -1; 293} 294 295 296unsigned long txn_affinity_addr(unsigned int irq, int cpu) 297{ 298#ifdef CONFIG_SMP 299 cpumask_copy(irq_desc[irq].affinity, cpumask_of(cpu)); 300#endif 301 302 return per_cpu(cpu_data, cpu).txn_addr; 303} 304 305 306unsigned long txn_alloc_addr(unsigned int virt_irq) 307{ 308 static int next_cpu = -1; 309 310 next_cpu++; /* assign to "next" CPU we want this bugger on */ 311 312 /* validate entry */ 313 while ((next_cpu < nr_cpu_ids) && 314 (!per_cpu(cpu_data, next_cpu).txn_addr || 315 !cpu_online(next_cpu))) 316 next_cpu++; 317 318 if (next_cpu >= nr_cpu_ids) 319 next_cpu = 0; /* nothing else, assign monarch */ 320 321 return txn_affinity_addr(virt_irq, next_cpu); 322} 323 324 325unsigned int txn_alloc_data(unsigned int virt_irq) 326{ 327 return virt_irq - CPU_IRQ_BASE; 328} 329 330static inline int eirr_to_irq(unsigned long eirr) 331{ 332 int bit = fls_long(eirr); 333 return (BITS_PER_LONG - bit) + TIMER_IRQ; 334} 335 336/* ONLY called from entry.S:intr_extint() */ 337void do_cpu_irq_mask(struct pt_regs *regs) 338{ 339 struct pt_regs *old_regs; 340 unsigned long eirr_val; 341 int irq, cpu = smp_processor_id(); 342#ifdef CONFIG_SMP 343 cpumask_t dest; 344#endif 345 346 old_regs = set_irq_regs(regs); 347 local_irq_disable(); 348 irq_enter(); 349 350 eirr_val = mfctl(23) & cpu_eiem & per_cpu(local_ack_eiem, cpu); 351 if (!eirr_val) 352 goto set_out; 353 irq = eirr_to_irq(eirr_val); 354 355#ifdef CONFIG_SMP 356 cpumask_copy(&dest, irq_desc[irq].affinity); 357 if (CHECK_IRQ_PER_CPU(irq_desc[irq].status) && 358 !cpu_isset(smp_processor_id(), dest)) { 359 int cpu = first_cpu(dest); 360 361 printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n", 362 irq, smp_processor_id(), cpu); 363 gsc_writel(irq + CPU_IRQ_BASE, 364 per_cpu(cpu_data, cpu).hpa); 365 goto set_out; 366 } 367#endif 368 __do_IRQ(irq); 369 370 out: 371 irq_exit(); 372 set_irq_regs(old_regs); 373 return; 374 375 set_out: 376 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu)); 377 goto out; 378} 379 380static struct irqaction timer_action = { 381 .handler = timer_interrupt, 382 .name = "timer", 383 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_PERCPU | IRQF_IRQPOLL, 384}; 385 386#ifdef CONFIG_SMP 387static struct irqaction ipi_action = { 388 .handler = ipi_interrupt, 389 .name = "IPI", 390 .flags = IRQF_DISABLED | IRQF_PERCPU, 391}; 392#endif 393 394static void claim_cpu_irqs(void) 395{ 396 int i; 397 for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) { 398 irq_desc[i].chip = &cpu_interrupt_type; 399 } 400 401 irq_desc[TIMER_IRQ].action = &timer_action; 402 irq_desc[TIMER_IRQ].status = IRQ_PER_CPU; 403#ifdef CONFIG_SMP 404 irq_desc[IPI_IRQ].action = &ipi_action; 405 irq_desc[IPI_IRQ].status = IRQ_PER_CPU; 406#endif 407} 408 409void __init init_IRQ(void) 410{ 411 local_irq_disable(); /* PARANOID - should already be disabled */ 412 mtctl(~0UL, 23); /* EIRR : clear all pending external intr */ 413 claim_cpu_irqs(); 414#ifdef CONFIG_SMP 415 if (!cpu_eiem) 416 cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ); 417#else 418 cpu_eiem = EIEM_MASK(TIMER_IRQ); 419#endif 420 set_eiem(cpu_eiem); /* EIEM : enable all external intr */ 421 422} 423