1/* 2 * BRIEF MODULE DESCRIPTION 3 * PCI initialization for IDT EB434 board 4 * 5 * Copyright 2004 IDT Inc. (rischelp@idt.com) 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, write to the Free Software Foundation, Inc., 25 * 675 Mass Ave, Cambridge, MA 02139, USA. 26 */ 27 28#include <linux/types.h> 29#include <linux/pci.h> 30#include <linux/kernel.h> 31#include <linux/init.h> 32 33#include <asm/mach-rc32434/rc32434.h> 34#include <asm/mach-rc32434/pci.h> 35 36#define PCI_ACCESS_READ 0 37#define PCI_ACCESS_WRITE 1 38 39/* define an unsigned array for the PCI registers */ 40static unsigned int korina_cnfg_regs[25] = { 41 KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4, 42 KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8, 43 KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12, 44 KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16, 45 KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20, 46 KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24 47}; 48static struct resource rc32434_res_pci_mem1; 49static struct resource rc32434_res_pci_mem2; 50 51static struct resource rc32434_res_pci_mem1 = { 52 .name = "PCI MEM1", 53 .start = 0x50000000, 54 .end = 0x5FFFFFFF, 55 .flags = IORESOURCE_MEM, 56 .parent = &rc32434_res_pci_mem1, 57 .sibling = NULL, 58 .child = &rc32434_res_pci_mem2 59}; 60 61static struct resource rc32434_res_pci_mem2 = { 62 .name = "PCI Mem2", 63 .start = 0x60000000, 64 .end = 0x6FFFFFFF, 65 .flags = IORESOURCE_MEM, 66 .parent = &rc32434_res_pci_mem1, 67 .sibling = NULL, 68 .child = NULL 69}; 70 71static struct resource rc32434_res_pci_io1 = { 72 .name = "PCI I/O1", 73 .start = 0x18800000, 74 .end = 0x188FFFFF, 75 .flags = IORESOURCE_IO, 76}; 77 78extern struct pci_ops rc32434_pci_ops; 79 80#define PCI_MEM1_START PCI_ADDR_START 81#define PCI_MEM1_END (PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1) 82#define PCI_MEM2_START (PCI_ADDR_START + CPUTOPCI_MEM_WIN) 83#define PCI_MEM2_END (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) - 1) 84#define PCI_IO1_START (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN)) 85#define PCI_IO1_END \ 86 (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN - 1) 87#define PCI_IO2_START \ 88 (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN) 89#define PCI_IO2_END \ 90 (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) - 1) 91 92struct pci_controller rc32434_controller2; 93 94struct pci_controller rc32434_controller = { 95 .pci_ops = &rc32434_pci_ops, 96 .mem_resource = &rc32434_res_pci_mem1, 97 .io_resource = &rc32434_res_pci_io1, 98 .mem_offset = 0, 99 .io_offset = 0, 100 101}; 102 103#ifdef __MIPSEB__ 104#define PCI_ENDIAN_FLAG PCILBAC_sb_m 105#else 106#define PCI_ENDIAN_FLAG 0 107#endif 108 109static int __init rc32434_pcibridge_init(void) 110{ 111 unsigned int pcicvalue, pcicdata = 0; 112 unsigned int dummyread, pcicntlval; 113 int loopCount; 114 unsigned int pci_config_addr; 115 116 pcicvalue = rc32434_pci->pcic; 117 pcicvalue = (pcicvalue >> PCIM_SHFT) & PCIM_BIT_LEN; 118 if (!((pcicvalue == PCIM_H_EA) || 119 (pcicvalue == PCIM_H_IA_FIX) || 120 (pcicvalue == PCIM_H_IA_RR))) { 121 pr_err("PCI init error!!!\n"); 122 /* Not in Host Mode, return ERROR */ 123 return -1; 124 } 125 /* Enables the Idle Grant mode, Arbiter Parking */ 126 pcicdata |= (PCI_CTL_IGM | PCI_CTL_EAP | PCI_CTL_EN); 127 rc32434_pci->pcic = pcicdata; /* Enable the PCI bus Interface */ 128 /* Zero out the PCI status & PCI Status Mask */ 129 for (;;) { 130 pcicdata = rc32434_pci->pcis; 131 if (!(pcicdata & PCI_STAT_RIP)) 132 break; 133 } 134 135 rc32434_pci->pcis = 0; 136 rc32434_pci->pcism = 0xFFFFFFFF; 137 /* Zero out the PCI decoupled registers */ 138 rc32434_pci->pcidac = 0; /* 139 * disable PCI decoupled accesses at 140 * initialization 141 */ 142 rc32434_pci->pcidas = 0; /* clear the status */ 143 rc32434_pci->pcidasm = 0x0000007F; /* Mask all the interrupts */ 144 /* Mask PCI Messaging Interrupts */ 145 rc32434_pci_msg->pciiic = 0; 146 rc32434_pci_msg->pciiim = 0xFFFFFFFF; 147 rc32434_pci_msg->pciioic = 0; 148 rc32434_pci_msg->pciioim = 0; 149 150 151 /* Setup PCILB0 as Memory Window */ 152 rc32434_pci->pcilba[0].address = (unsigned int) (PCI_ADDR_START); 153 154 /* setup the PCI map address as same as the local address */ 155 156 rc32434_pci->pcilba[0].mapping = (unsigned int) (PCI_ADDR_START); 157 158 159 /* Setup PCILBA1 as MEM */ 160 rc32434_pci->pcilba[0].control = 161 (((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG); 162 dummyread = rc32434_pci->pcilba[0].control; /* flush the CPU write Buffers */ 163 rc32434_pci->pcilba[1].address = 0x60000000; 164 rc32434_pci->pcilba[1].mapping = 0x60000000; 165 166 /* setup PCILBA2 as IO Window */ 167 rc32434_pci->pcilba[1].control = 168 (((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG); 169 dummyread = rc32434_pci->pcilba[1].control; /* flush the CPU write Buffers */ 170 rc32434_pci->pcilba[2].address = 0x18C00000; 171 rc32434_pci->pcilba[2].mapping = 0x18FFFFFF; 172 173 /* setup PCILBA2 as IO Window */ 174 rc32434_pci->pcilba[2].control = 175 (((SIZE_4MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG); 176 dummyread = rc32434_pci->pcilba[2].control; /* flush the CPU write Buffers */ 177 178 /* Setup PCILBA3 as IO Window */ 179 rc32434_pci->pcilba[3].address = 0x18800000; 180 rc32434_pci->pcilba[3].mapping = 0x18800000; 181 rc32434_pci->pcilba[3].control = 182 ((((SIZE_1MB & 0x1ff) << PCI_LBAC_SIZE_BIT) | PCI_LBAC_MSI) | 183 PCI_ENDIAN_FLAG); 184 dummyread = rc32434_pci->pcilba[3].control; /* flush the CPU write Buffers */ 185 186 pci_config_addr = (unsigned int) (0x80000004); 187 for (loopCount = 0; loopCount < 24; loopCount++) { 188 rc32434_pci->pcicfga = pci_config_addr; 189 dummyread = rc32434_pci->pcicfga; 190 rc32434_pci->pcicfgd = korina_cnfg_regs[loopCount]; 191 dummyread = rc32434_pci->pcicfgd; 192 pci_config_addr += 4; 193 } 194 rc32434_pci->pcitc = 195 (unsigned int) ((PCITC_RTIMER_VAL & 0xff) << PCI_TC_RTIMER_BIT) | 196 ((PCITC_DTIMER_VAL & 0xff) << PCI_TC_DTIMER_BIT); 197 198 pcicntlval = rc32434_pci->pcic; 199 pcicntlval &= ~PCI_CTL_TNR; 200 rc32434_pci->pcic = pcicntlval; 201 pcicntlval = rc32434_pci->pcic; 202 203 return 0; 204} 205 206static int __init rc32434_pci_init(void) 207{ 208 void __iomem *io_map_base; 209 210 pr_info("PCI: Initializing PCI\n"); 211 212 ioport_resource.start = rc32434_res_pci_io1.start; 213 ioport_resource.end = rc32434_res_pci_io1.end; 214 215 rc32434_pcibridge_init(); 216 217 io_map_base = ioremap(rc32434_res_pci_io1.start, 218 rc32434_res_pci_io1.end - rc32434_res_pci_io1.start + 1); 219 220 if (!io_map_base) 221 return -ENOMEM; 222 223 rc32434_controller.io_map_base = 224 (unsigned long)io_map_base - rc32434_res_pci_io1.start; 225 226 register_pci_controller(&rc32434_controller); 227 rc32434_sync(); 228 229 return 0; 230} 231 232arch_initcall(rc32434_pci_init); 233