1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2005-2009, 2010 Cavium Networks 7 */ 8#include <linux/kernel.h> 9#include <linux/init.h> 10#include <linux/msi.h> 11#include <linux/spinlock.h> 12#include <linux/interrupt.h> 13 14#include <asm/octeon/octeon.h> 15#include <asm/octeon/cvmx-npi-defs.h> 16#include <asm/octeon/cvmx-pci-defs.h> 17#include <asm/octeon/cvmx-npei-defs.h> 18#include <asm/octeon/cvmx-pexp-defs.h> 19#include <asm/octeon/pci-octeon.h> 20 21/* 22 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is 23 * in use. 24 */ 25static u64 msi_free_irq_bitmask[4]; 26 27/* 28 * Each bit in msi_multiple_irq_bitmask tells that the device using 29 * this bit in msi_free_irq_bitmask is also using the next bit. This 30 * is used so we can disable all of the MSI interrupts when a device 31 * uses multiple. 32 */ 33static u64 msi_multiple_irq_bitmask[4]; 34 35/* 36 * This lock controls updates to msi_free_irq_bitmask and 37 * msi_multiple_irq_bitmask. 38 */ 39static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock); 40 41/* 42 * Number of MSI IRQs used. This variable is set up in 43 * the module init time. 44 */ 45static int msi_irq_size; 46 47/** 48 * Called when a driver request MSI interrupts instead of the 49 * legacy INT A-D. This routine will allocate multiple interrupts 50 * for MSI devices that support them. A device can override this by 51 * programming the MSI control bits [6:4] before calling 52 * pci_enable_msi(). 53 * 54 * @dev: Device requesting MSI interrupts 55 * @desc: MSI descriptor 56 * 57 * Returns 0 on success. 58 */ 59int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) 60{ 61 struct msi_msg msg; 62 u16 control; 63 int configured_private_bits; 64 int request_private_bits; 65 int irq = 0; 66 int irq_step; 67 u64 search_mask; 68 int index; 69 70 /* 71 * Read the MSI config to figure out how many IRQs this device 72 * wants. Most devices only want 1, which will give 73 * configured_private_bits and request_private_bits equal 0. 74 */ 75 pci_read_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS, 76 &control); 77 78 /* 79 * If the number of private bits has been configured then use 80 * that value instead of the requested number. This gives the 81 * driver the chance to override the number of interrupts 82 * before calling pci_enable_msi(). 83 */ 84 configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4; 85 if (configured_private_bits == 0) { 86 /* Nothing is configured, so use the hardware requested size */ 87 request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1; 88 } else { 89 /* 90 * Use the number of configured bits, assuming the 91 * driver wanted to override the hardware request 92 * value. 93 */ 94 request_private_bits = configured_private_bits; 95 } 96 97 /* 98 * The PCI 2.3 spec mandates that there are at most 32 99 * interrupts. If this device asks for more, only give it one. 100 */ 101 if (request_private_bits > 5) 102 request_private_bits = 0; 103 104try_only_one: 105 /* 106 * The IRQs have to be aligned on a power of two based on the 107 * number being requested. 108 */ 109 irq_step = 1 << request_private_bits; 110 111 /* Mask with one bit for each IRQ */ 112 search_mask = (1 << irq_step) - 1; 113 114 /* 115 * We're going to search msi_free_irq_bitmask_lock for zero 116 * bits. This represents an MSI interrupt number that isn't in 117 * use. 118 */ 119 spin_lock(&msi_free_irq_bitmask_lock); 120 for (index = 0; index < msi_irq_size/64; index++) { 121 for (irq = 0; irq < 64; irq += irq_step) { 122 if ((msi_free_irq_bitmask[index] & (search_mask << irq)) == 0) { 123 msi_free_irq_bitmask[index] |= search_mask << irq; 124 msi_multiple_irq_bitmask[index] |= (search_mask >> 1) << irq; 125 goto msi_irq_allocated; 126 } 127 } 128 } 129msi_irq_allocated: 130 spin_unlock(&msi_free_irq_bitmask_lock); 131 132 /* Make sure the search for available interrupts didn't fail */ 133 if (irq >= 64) { 134 if (request_private_bits) { 135 pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying just one", 136 1 << request_private_bits); 137 request_private_bits = 0; 138 goto try_only_one; 139 } else 140 panic("arch_setup_msi_irq: Unable to find a free MSI interrupt"); 141 } 142 143 /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */ 144 irq += index*64; 145 irq += OCTEON_IRQ_MSI_BIT0; 146 147 switch (octeon_dma_bar_type) { 148 case OCTEON_DMA_BAR_TYPE_SMALL: 149 /* When not using big bar, Bar 0 is based at 128MB */ 150 msg.address_lo = 151 ((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff; 152 msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32; 153 case OCTEON_DMA_BAR_TYPE_BIG: 154 /* When using big bar, Bar 0 is based at 0 */ 155 msg.address_lo = (0 + CVMX_PCI_MSI_RCV) & 0xffffffff; 156 msg.address_hi = (0 + CVMX_PCI_MSI_RCV) >> 32; 157 break; 158 case OCTEON_DMA_BAR_TYPE_PCIE: 159 /* When using PCIe, Bar 0 is based at 0 */ 160 msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff; 161 msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32; 162 break; 163 default: 164 panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type\n"); 165 } 166 msg.data = irq - OCTEON_IRQ_MSI_BIT0; 167 168 /* Update the number of IRQs the device has available to it */ 169 control &= ~PCI_MSI_FLAGS_QSIZE; 170 control |= request_private_bits << 4; 171 pci_write_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS, 172 control); 173 174 set_irq_msi(irq, desc); 175 write_msi_msg(irq, &msg); 176 return 0; 177} 178 179int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) 180{ 181 struct msi_desc *entry; 182 int ret; 183 184 /* 185 * MSI-X is not supported. 186 */ 187 if (type == PCI_CAP_ID_MSIX) 188 return -EINVAL; 189 190 /* 191 * If an architecture wants to support multiple MSI, it needs to 192 * override arch_setup_msi_irqs() 193 */ 194 if (type == PCI_CAP_ID_MSI && nvec > 1) 195 return 1; 196 197 list_for_each_entry(entry, &dev->msi_list, list) { 198 ret = arch_setup_msi_irq(dev, entry); 199 if (ret < 0) 200 return ret; 201 if (ret > 0) 202 return -ENOSPC; 203 } 204 205 return 0; 206} 207 208/** 209 * Called when a device no longer needs its MSI interrupts. All 210 * MSI interrupts for the device are freed. 211 * 212 * @irq: The devices first irq number. There may be multple in sequence. 213 */ 214void arch_teardown_msi_irq(unsigned int irq) 215{ 216 int number_irqs; 217 u64 bitmask; 218 int index = 0; 219 int irq0; 220 221 if ((irq < OCTEON_IRQ_MSI_BIT0) 222 || (irq > msi_irq_size + OCTEON_IRQ_MSI_BIT0)) 223 panic("arch_teardown_msi_irq: Attempted to teardown illegal " 224 "MSI interrupt (%d)", irq); 225 226 irq -= OCTEON_IRQ_MSI_BIT0; 227 index = irq / 64; 228 irq0 = irq % 64; 229 230 /* 231 * Count the number of IRQs we need to free by looking at the 232 * msi_multiple_irq_bitmask. Each bit set means that the next 233 * IRQ is also owned by this device. 234 */ 235 number_irqs = 0; 236 while ((irq0 + number_irqs < 64) && 237 (msi_multiple_irq_bitmask[index] 238 & (1ull << (irq0 + number_irqs)))) 239 number_irqs++; 240 number_irqs++; 241 /* Mask with one bit for each IRQ */ 242 bitmask = (1 << number_irqs) - 1; 243 /* Shift the mask to the correct bit location */ 244 bitmask <<= irq0; 245 if ((msi_free_irq_bitmask[index] & bitmask) != bitmask) 246 panic("arch_teardown_msi_irq: Attempted to teardown MSI " 247 "interrupt (%d) not in use", irq); 248 249 /* Checks are done, update the in use bitmask */ 250 spin_lock(&msi_free_irq_bitmask_lock); 251 msi_free_irq_bitmask[index] &= ~bitmask; 252 msi_multiple_irq_bitmask[index] &= ~bitmask; 253 spin_unlock(&msi_free_irq_bitmask_lock); 254} 255 256static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock); 257 258static u64 msi_rcv_reg[4]; 259static u64 mis_ena_reg[4]; 260 261static void octeon_irq_msi_enable_pcie(unsigned int irq) 262{ 263 u64 en; 264 unsigned long flags; 265 int msi_number = irq - OCTEON_IRQ_MSI_BIT0; 266 int irq_index = msi_number >> 6; 267 int irq_bit = msi_number & 0x3f; 268 269 raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags); 270 en = cvmx_read_csr(mis_ena_reg[irq_index]); 271 en |= 1ull << irq_bit; 272 cvmx_write_csr(mis_ena_reg[irq_index], en); 273 cvmx_read_csr(mis_ena_reg[irq_index]); 274 raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); 275} 276 277static void octeon_irq_msi_disable_pcie(unsigned int irq) 278{ 279 u64 en; 280 unsigned long flags; 281 int msi_number = irq - OCTEON_IRQ_MSI_BIT0; 282 int irq_index = msi_number >> 6; 283 int irq_bit = msi_number & 0x3f; 284 285 raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags); 286 en = cvmx_read_csr(mis_ena_reg[irq_index]); 287 en &= ~(1ull << irq_bit); 288 cvmx_write_csr(mis_ena_reg[irq_index], en); 289 cvmx_read_csr(mis_ena_reg[irq_index]); 290 raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); 291} 292 293static struct irq_chip octeon_irq_chip_msi_pcie = { 294 .name = "MSI", 295 .enable = octeon_irq_msi_enable_pcie, 296 .disable = octeon_irq_msi_disable_pcie, 297}; 298 299static void octeon_irq_msi_enable_pci(unsigned int irq) 300{ 301 /* 302 * Octeon PCI doesn't have the ability to mask/unmask MSI 303 * interrupts individually. Instead of masking/unmasking them 304 * in groups of 16, we simple assume MSI devices are well 305 * behaved. MSI interrupts are always enable and the ACK is 306 * assumed to be enough 307 */ 308} 309 310static void octeon_irq_msi_disable_pci(unsigned int irq) 311{ 312 /* See comment in enable */ 313} 314 315static struct irq_chip octeon_irq_chip_msi_pci = { 316 .name = "MSI", 317 .enable = octeon_irq_msi_enable_pci, 318 .disable = octeon_irq_msi_disable_pci, 319}; 320 321/* 322 * Called by the interrupt handling code when an MSI interrupt 323 * occurs. 324 */ 325static irqreturn_t __octeon_msi_do_interrupt(int index, u64 msi_bits) 326{ 327 int irq; 328 int bit; 329 330 bit = fls64(msi_bits); 331 if (bit) { 332 bit--; 333 /* Acknowledge it first. */ 334 cvmx_write_csr(msi_rcv_reg[index], 1ull << bit); 335 336 irq = bit + OCTEON_IRQ_MSI_BIT0 + 64 * index; 337 do_IRQ(irq); 338 return IRQ_HANDLED; 339 } 340 return IRQ_NONE; 341} 342 343#define OCTEON_MSI_INT_HANDLER_X(x) \ 344static irqreturn_t octeon_msi_interrupt##x(int cpl, void *dev_id) \ 345{ \ 346 u64 msi_bits = cvmx_read_csr(msi_rcv_reg[(x)]); \ 347 return __octeon_msi_do_interrupt((x), msi_bits); \ 348} 349 350/* 351 * Create octeon_msi_interrupt{0-3} function body 352 */ 353OCTEON_MSI_INT_HANDLER_X(0); 354OCTEON_MSI_INT_HANDLER_X(1); 355OCTEON_MSI_INT_HANDLER_X(2); 356OCTEON_MSI_INT_HANDLER_X(3); 357 358/* 359 * Initializes the MSI interrupt handling code 360 */ 361int __init octeon_msi_initialize(void) 362{ 363 int irq; 364 struct irq_chip *msi; 365 366 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) { 367 msi_rcv_reg[0] = CVMX_PEXP_NPEI_MSI_RCV0; 368 msi_rcv_reg[1] = CVMX_PEXP_NPEI_MSI_RCV1; 369 msi_rcv_reg[2] = CVMX_PEXP_NPEI_MSI_RCV2; 370 msi_rcv_reg[3] = CVMX_PEXP_NPEI_MSI_RCV3; 371 mis_ena_reg[0] = CVMX_PEXP_NPEI_MSI_ENB0; 372 mis_ena_reg[1] = CVMX_PEXP_NPEI_MSI_ENB1; 373 mis_ena_reg[2] = CVMX_PEXP_NPEI_MSI_ENB2; 374 mis_ena_reg[3] = CVMX_PEXP_NPEI_MSI_ENB3; 375 msi = &octeon_irq_chip_msi_pcie; 376 } else { 377 msi_rcv_reg[0] = CVMX_NPI_NPI_MSI_RCV; 378#define INVALID_GENERATE_ADE 0x8700000000000000ULL; 379 msi_rcv_reg[1] = INVALID_GENERATE_ADE; 380 msi_rcv_reg[2] = INVALID_GENERATE_ADE; 381 msi_rcv_reg[3] = INVALID_GENERATE_ADE; 382 mis_ena_reg[0] = INVALID_GENERATE_ADE; 383 mis_ena_reg[1] = INVALID_GENERATE_ADE; 384 mis_ena_reg[2] = INVALID_GENERATE_ADE; 385 mis_ena_reg[3] = INVALID_GENERATE_ADE; 386 msi = &octeon_irq_chip_msi_pci; 387 } 388 389 for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++) 390 set_irq_chip_and_handler(irq, msi, handle_simple_irq); 391 392 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) { 393 if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0, 394 0, "MSI[0:63]", octeon_msi_interrupt0)) 395 panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed"); 396 397 if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt1, 398 0, "MSI[64:127]", octeon_msi_interrupt1)) 399 panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed"); 400 401 if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt2, 402 0, "MSI[127:191]", octeon_msi_interrupt2)) 403 panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed"); 404 405 if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt3, 406 0, "MSI[192:255]", octeon_msi_interrupt3)) 407 panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed"); 408 409 msi_irq_size = 256; 410 } else if (octeon_is_pci_host()) { 411 if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0, 412 0, "MSI[0:15]", octeon_msi_interrupt0)) 413 panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed"); 414 415 if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt0, 416 0, "MSI[16:31]", octeon_msi_interrupt0)) 417 panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed"); 418 419 if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt0, 420 0, "MSI[32:47]", octeon_msi_interrupt0)) 421 panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed"); 422 423 if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt0, 424 0, "MSI[48:63]", octeon_msi_interrupt0)) 425 panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed"); 426 msi_irq_size = 64; 427 } 428 return 0; 429} 430subsys_initcall(octeon_msi_initialize); 431