1/***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2008 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28#ifndef __CVMX_PCIEEP_DEFS_H__ 29#define __CVMX_PCIEEP_DEFS_H__ 30 31#define CVMX_PCIEEP_CFG000 \ 32 (0x0000000000000000ull) 33#define CVMX_PCIEEP_CFG001 \ 34 (0x0000000000000004ull) 35#define CVMX_PCIEEP_CFG002 \ 36 (0x0000000000000008ull) 37#define CVMX_PCIEEP_CFG003 \ 38 (0x000000000000000Cull) 39#define CVMX_PCIEEP_CFG004 \ 40 (0x0000000000000010ull) 41#define CVMX_PCIEEP_CFG004_MASK \ 42 (0x0000000080000010ull) 43#define CVMX_PCIEEP_CFG005 \ 44 (0x0000000000000014ull) 45#define CVMX_PCIEEP_CFG005_MASK \ 46 (0x0000000080000014ull) 47#define CVMX_PCIEEP_CFG006 \ 48 (0x0000000000000018ull) 49#define CVMX_PCIEEP_CFG006_MASK \ 50 (0x0000000080000018ull) 51#define CVMX_PCIEEP_CFG007 \ 52 (0x000000000000001Cull) 53#define CVMX_PCIEEP_CFG007_MASK \ 54 (0x000000008000001Cull) 55#define CVMX_PCIEEP_CFG008 \ 56 (0x0000000000000020ull) 57#define CVMX_PCIEEP_CFG008_MASK \ 58 (0x0000000080000020ull) 59#define CVMX_PCIEEP_CFG009 \ 60 (0x0000000000000024ull) 61#define CVMX_PCIEEP_CFG009_MASK \ 62 (0x0000000080000024ull) 63#define CVMX_PCIEEP_CFG010 \ 64 (0x0000000000000028ull) 65#define CVMX_PCIEEP_CFG011 \ 66 (0x000000000000002Cull) 67#define CVMX_PCIEEP_CFG012 \ 68 (0x0000000000000030ull) 69#define CVMX_PCIEEP_CFG012_MASK \ 70 (0x0000000080000030ull) 71#define CVMX_PCIEEP_CFG013 \ 72 (0x0000000000000034ull) 73#define CVMX_PCIEEP_CFG015 \ 74 (0x000000000000003Cull) 75#define CVMX_PCIEEP_CFG016 \ 76 (0x0000000000000040ull) 77#define CVMX_PCIEEP_CFG017 \ 78 (0x0000000000000044ull) 79#define CVMX_PCIEEP_CFG020 \ 80 (0x0000000000000050ull) 81#define CVMX_PCIEEP_CFG021 \ 82 (0x0000000000000054ull) 83#define CVMX_PCIEEP_CFG022 \ 84 (0x0000000000000058ull) 85#define CVMX_PCIEEP_CFG023 \ 86 (0x000000000000005Cull) 87#define CVMX_PCIEEP_CFG028 \ 88 (0x0000000000000070ull) 89#define CVMX_PCIEEP_CFG029 \ 90 (0x0000000000000074ull) 91#define CVMX_PCIEEP_CFG030 \ 92 (0x0000000000000078ull) 93#define CVMX_PCIEEP_CFG031 \ 94 (0x000000000000007Cull) 95#define CVMX_PCIEEP_CFG032 \ 96 (0x0000000000000080ull) 97#define CVMX_PCIEEP_CFG033 \ 98 (0x0000000000000084ull) 99#define CVMX_PCIEEP_CFG034 \ 100 (0x0000000000000088ull) 101#define CVMX_PCIEEP_CFG037 \ 102 (0x0000000000000094ull) 103#define CVMX_PCIEEP_CFG038 \ 104 (0x0000000000000098ull) 105#define CVMX_PCIEEP_CFG039 \ 106 (0x000000000000009Cull) 107#define CVMX_PCIEEP_CFG040 \ 108 (0x00000000000000A0ull) 109#define CVMX_PCIEEP_CFG041 \ 110 (0x00000000000000A4ull) 111#define CVMX_PCIEEP_CFG042 \ 112 (0x00000000000000A8ull) 113#define CVMX_PCIEEP_CFG064 \ 114 (0x0000000000000100ull) 115#define CVMX_PCIEEP_CFG065 \ 116 (0x0000000000000104ull) 117#define CVMX_PCIEEP_CFG066 \ 118 (0x0000000000000108ull) 119#define CVMX_PCIEEP_CFG067 \ 120 (0x000000000000010Cull) 121#define CVMX_PCIEEP_CFG068 \ 122 (0x0000000000000110ull) 123#define CVMX_PCIEEP_CFG069 \ 124 (0x0000000000000114ull) 125#define CVMX_PCIEEP_CFG070 \ 126 (0x0000000000000118ull) 127#define CVMX_PCIEEP_CFG071 \ 128 (0x000000000000011Cull) 129#define CVMX_PCIEEP_CFG072 \ 130 (0x0000000000000120ull) 131#define CVMX_PCIEEP_CFG073 \ 132 (0x0000000000000124ull) 133#define CVMX_PCIEEP_CFG074 \ 134 (0x0000000000000128ull) 135#define CVMX_PCIEEP_CFG448 \ 136 (0x0000000000000700ull) 137#define CVMX_PCIEEP_CFG449 \ 138 (0x0000000000000704ull) 139#define CVMX_PCIEEP_CFG450 \ 140 (0x0000000000000708ull) 141#define CVMX_PCIEEP_CFG451 \ 142 (0x000000000000070Cull) 143#define CVMX_PCIEEP_CFG452 \ 144 (0x0000000000000710ull) 145#define CVMX_PCIEEP_CFG453 \ 146 (0x0000000000000714ull) 147#define CVMX_PCIEEP_CFG454 \ 148 (0x0000000000000718ull) 149#define CVMX_PCIEEP_CFG455 \ 150 (0x000000000000071Cull) 151#define CVMX_PCIEEP_CFG456 \ 152 (0x0000000000000720ull) 153#define CVMX_PCIEEP_CFG458 \ 154 (0x0000000000000728ull) 155#define CVMX_PCIEEP_CFG459 \ 156 (0x000000000000072Cull) 157#define CVMX_PCIEEP_CFG460 \ 158 (0x0000000000000730ull) 159#define CVMX_PCIEEP_CFG461 \ 160 (0x0000000000000734ull) 161#define CVMX_PCIEEP_CFG462 \ 162 (0x0000000000000738ull) 163#define CVMX_PCIEEP_CFG463 \ 164 (0x000000000000073Cull) 165#define CVMX_PCIEEP_CFG464 \ 166 (0x0000000000000740ull) 167#define CVMX_PCIEEP_CFG465 \ 168 (0x0000000000000744ull) 169#define CVMX_PCIEEP_CFG466 \ 170 (0x0000000000000748ull) 171#define CVMX_PCIEEP_CFG467 \ 172 (0x000000000000074Cull) 173#define CVMX_PCIEEP_CFG468 \ 174 (0x0000000000000750ull) 175#define CVMX_PCIEEP_CFG490 \ 176 (0x00000000000007A8ull) 177#define CVMX_PCIEEP_CFG491 \ 178 (0x00000000000007ACull) 179#define CVMX_PCIEEP_CFG492 \ 180 (0x00000000000007B0ull) 181#define CVMX_PCIEEP_CFG516 \ 182 (0x0000000000000810ull) 183#define CVMX_PCIEEP_CFG517 \ 184 (0x0000000000000814ull) 185 186union cvmx_pcieep_cfg000 { 187 uint32_t u32; 188 struct cvmx_pcieep_cfg000_s { 189 uint32_t devid:16; 190 uint32_t vendid:16; 191 } s; 192 struct cvmx_pcieep_cfg000_s cn52xx; 193 struct cvmx_pcieep_cfg000_s cn52xxp1; 194 struct cvmx_pcieep_cfg000_s cn56xx; 195 struct cvmx_pcieep_cfg000_s cn56xxp1; 196}; 197 198union cvmx_pcieep_cfg001 { 199 uint32_t u32; 200 struct cvmx_pcieep_cfg001_s { 201 uint32_t dpe:1; 202 uint32_t sse:1; 203 uint32_t rma:1; 204 uint32_t rta:1; 205 uint32_t sta:1; 206 uint32_t devt:2; 207 uint32_t mdpe:1; 208 uint32_t fbb:1; 209 uint32_t reserved_22_22:1; 210 uint32_t m66:1; 211 uint32_t cl:1; 212 uint32_t i_stat:1; 213 uint32_t reserved_11_18:8; 214 uint32_t i_dis:1; 215 uint32_t fbbe:1; 216 uint32_t see:1; 217 uint32_t ids_wcc:1; 218 uint32_t per:1; 219 uint32_t vps:1; 220 uint32_t mwice:1; 221 uint32_t scse:1; 222 uint32_t me:1; 223 uint32_t msae:1; 224 uint32_t isae:1; 225 } s; 226 struct cvmx_pcieep_cfg001_s cn52xx; 227 struct cvmx_pcieep_cfg001_s cn52xxp1; 228 struct cvmx_pcieep_cfg001_s cn56xx; 229 struct cvmx_pcieep_cfg001_s cn56xxp1; 230}; 231 232union cvmx_pcieep_cfg002 { 233 uint32_t u32; 234 struct cvmx_pcieep_cfg002_s { 235 uint32_t bcc:8; 236 uint32_t sc:8; 237 uint32_t pi:8; 238 uint32_t rid:8; 239 } s; 240 struct cvmx_pcieep_cfg002_s cn52xx; 241 struct cvmx_pcieep_cfg002_s cn52xxp1; 242 struct cvmx_pcieep_cfg002_s cn56xx; 243 struct cvmx_pcieep_cfg002_s cn56xxp1; 244}; 245 246union cvmx_pcieep_cfg003 { 247 uint32_t u32; 248 struct cvmx_pcieep_cfg003_s { 249 uint32_t bist:8; 250 uint32_t mfd:1; 251 uint32_t chf:7; 252 uint32_t lt:8; 253 uint32_t cls:8; 254 } s; 255 struct cvmx_pcieep_cfg003_s cn52xx; 256 struct cvmx_pcieep_cfg003_s cn52xxp1; 257 struct cvmx_pcieep_cfg003_s cn56xx; 258 struct cvmx_pcieep_cfg003_s cn56xxp1; 259}; 260 261union cvmx_pcieep_cfg004 { 262 uint32_t u32; 263 struct cvmx_pcieep_cfg004_s { 264 uint32_t lbab:18; 265 uint32_t reserved_4_13:10; 266 uint32_t pf:1; 267 uint32_t typ:2; 268 uint32_t mspc:1; 269 } s; 270 struct cvmx_pcieep_cfg004_s cn52xx; 271 struct cvmx_pcieep_cfg004_s cn52xxp1; 272 struct cvmx_pcieep_cfg004_s cn56xx; 273 struct cvmx_pcieep_cfg004_s cn56xxp1; 274}; 275 276union cvmx_pcieep_cfg004_mask { 277 uint32_t u32; 278 struct cvmx_pcieep_cfg004_mask_s { 279 uint32_t lmask:31; 280 uint32_t enb:1; 281 } s; 282 struct cvmx_pcieep_cfg004_mask_s cn52xx; 283 struct cvmx_pcieep_cfg004_mask_s cn52xxp1; 284 struct cvmx_pcieep_cfg004_mask_s cn56xx; 285 struct cvmx_pcieep_cfg004_mask_s cn56xxp1; 286}; 287 288union cvmx_pcieep_cfg005 { 289 uint32_t u32; 290 struct cvmx_pcieep_cfg005_s { 291 uint32_t ubab:32; 292 } s; 293 struct cvmx_pcieep_cfg005_s cn52xx; 294 struct cvmx_pcieep_cfg005_s cn52xxp1; 295 struct cvmx_pcieep_cfg005_s cn56xx; 296 struct cvmx_pcieep_cfg005_s cn56xxp1; 297}; 298 299union cvmx_pcieep_cfg005_mask { 300 uint32_t u32; 301 struct cvmx_pcieep_cfg005_mask_s { 302 uint32_t umask:32; 303 } s; 304 struct cvmx_pcieep_cfg005_mask_s cn52xx; 305 struct cvmx_pcieep_cfg005_mask_s cn52xxp1; 306 struct cvmx_pcieep_cfg005_mask_s cn56xx; 307 struct cvmx_pcieep_cfg005_mask_s cn56xxp1; 308}; 309 310union cvmx_pcieep_cfg006 { 311 uint32_t u32; 312 struct cvmx_pcieep_cfg006_s { 313 uint32_t lbab:6; 314 uint32_t reserved_4_25:22; 315 uint32_t pf:1; 316 uint32_t typ:2; 317 uint32_t mspc:1; 318 } s; 319 struct cvmx_pcieep_cfg006_s cn52xx; 320 struct cvmx_pcieep_cfg006_s cn52xxp1; 321 struct cvmx_pcieep_cfg006_s cn56xx; 322 struct cvmx_pcieep_cfg006_s cn56xxp1; 323}; 324 325union cvmx_pcieep_cfg006_mask { 326 uint32_t u32; 327 struct cvmx_pcieep_cfg006_mask_s { 328 uint32_t lmask:31; 329 uint32_t enb:1; 330 } s; 331 struct cvmx_pcieep_cfg006_mask_s cn52xx; 332 struct cvmx_pcieep_cfg006_mask_s cn52xxp1; 333 struct cvmx_pcieep_cfg006_mask_s cn56xx; 334 struct cvmx_pcieep_cfg006_mask_s cn56xxp1; 335}; 336 337union cvmx_pcieep_cfg007 { 338 uint32_t u32; 339 struct cvmx_pcieep_cfg007_s { 340 uint32_t ubab:32; 341 } s; 342 struct cvmx_pcieep_cfg007_s cn52xx; 343 struct cvmx_pcieep_cfg007_s cn52xxp1; 344 struct cvmx_pcieep_cfg007_s cn56xx; 345 struct cvmx_pcieep_cfg007_s cn56xxp1; 346}; 347 348union cvmx_pcieep_cfg007_mask { 349 uint32_t u32; 350 struct cvmx_pcieep_cfg007_mask_s { 351 uint32_t umask:32; 352 } s; 353 struct cvmx_pcieep_cfg007_mask_s cn52xx; 354 struct cvmx_pcieep_cfg007_mask_s cn52xxp1; 355 struct cvmx_pcieep_cfg007_mask_s cn56xx; 356 struct cvmx_pcieep_cfg007_mask_s cn56xxp1; 357}; 358 359union cvmx_pcieep_cfg008 { 360 uint32_t u32; 361 struct cvmx_pcieep_cfg008_s { 362 uint32_t reserved_4_31:28; 363 uint32_t pf:1; 364 uint32_t typ:2; 365 uint32_t mspc:1; 366 } s; 367 struct cvmx_pcieep_cfg008_s cn52xx; 368 struct cvmx_pcieep_cfg008_s cn52xxp1; 369 struct cvmx_pcieep_cfg008_s cn56xx; 370 struct cvmx_pcieep_cfg008_s cn56xxp1; 371}; 372 373union cvmx_pcieep_cfg008_mask { 374 uint32_t u32; 375 struct cvmx_pcieep_cfg008_mask_s { 376 uint32_t lmask:31; 377 uint32_t enb:1; 378 } s; 379 struct cvmx_pcieep_cfg008_mask_s cn52xx; 380 struct cvmx_pcieep_cfg008_mask_s cn52xxp1; 381 struct cvmx_pcieep_cfg008_mask_s cn56xx; 382 struct cvmx_pcieep_cfg008_mask_s cn56xxp1; 383}; 384 385union cvmx_pcieep_cfg009 { 386 uint32_t u32; 387 struct cvmx_pcieep_cfg009_s { 388 uint32_t ubab:25; 389 uint32_t reserved_0_6:7; 390 } s; 391 struct cvmx_pcieep_cfg009_s cn52xx; 392 struct cvmx_pcieep_cfg009_s cn52xxp1; 393 struct cvmx_pcieep_cfg009_s cn56xx; 394 struct cvmx_pcieep_cfg009_s cn56xxp1; 395}; 396 397union cvmx_pcieep_cfg009_mask { 398 uint32_t u32; 399 struct cvmx_pcieep_cfg009_mask_s { 400 uint32_t umask:32; 401 } s; 402 struct cvmx_pcieep_cfg009_mask_s cn52xx; 403 struct cvmx_pcieep_cfg009_mask_s cn52xxp1; 404 struct cvmx_pcieep_cfg009_mask_s cn56xx; 405 struct cvmx_pcieep_cfg009_mask_s cn56xxp1; 406}; 407 408union cvmx_pcieep_cfg010 { 409 uint32_t u32; 410 struct cvmx_pcieep_cfg010_s { 411 uint32_t cisp:32; 412 } s; 413 struct cvmx_pcieep_cfg010_s cn52xx; 414 struct cvmx_pcieep_cfg010_s cn52xxp1; 415 struct cvmx_pcieep_cfg010_s cn56xx; 416 struct cvmx_pcieep_cfg010_s cn56xxp1; 417}; 418 419union cvmx_pcieep_cfg011 { 420 uint32_t u32; 421 struct cvmx_pcieep_cfg011_s { 422 uint32_t ssid:16; 423 uint32_t ssvid:16; 424 } s; 425 struct cvmx_pcieep_cfg011_s cn52xx; 426 struct cvmx_pcieep_cfg011_s cn52xxp1; 427 struct cvmx_pcieep_cfg011_s cn56xx; 428 struct cvmx_pcieep_cfg011_s cn56xxp1; 429}; 430 431union cvmx_pcieep_cfg012 { 432 uint32_t u32; 433 struct cvmx_pcieep_cfg012_s { 434 uint32_t eraddr:16; 435 uint32_t reserved_1_15:15; 436 uint32_t er_en:1; 437 } s; 438 struct cvmx_pcieep_cfg012_s cn52xx; 439 struct cvmx_pcieep_cfg012_s cn52xxp1; 440 struct cvmx_pcieep_cfg012_s cn56xx; 441 struct cvmx_pcieep_cfg012_s cn56xxp1; 442}; 443 444union cvmx_pcieep_cfg012_mask { 445 uint32_t u32; 446 struct cvmx_pcieep_cfg012_mask_s { 447 uint32_t mask:31; 448 uint32_t enb:1; 449 } s; 450 struct cvmx_pcieep_cfg012_mask_s cn52xx; 451 struct cvmx_pcieep_cfg012_mask_s cn52xxp1; 452 struct cvmx_pcieep_cfg012_mask_s cn56xx; 453 struct cvmx_pcieep_cfg012_mask_s cn56xxp1; 454}; 455 456union cvmx_pcieep_cfg013 { 457 uint32_t u32; 458 struct cvmx_pcieep_cfg013_s { 459 uint32_t reserved_8_31:24; 460 uint32_t cp:8; 461 } s; 462 struct cvmx_pcieep_cfg013_s cn52xx; 463 struct cvmx_pcieep_cfg013_s cn52xxp1; 464 struct cvmx_pcieep_cfg013_s cn56xx; 465 struct cvmx_pcieep_cfg013_s cn56xxp1; 466}; 467 468union cvmx_pcieep_cfg015 { 469 uint32_t u32; 470 struct cvmx_pcieep_cfg015_s { 471 uint32_t ml:8; 472 uint32_t mg:8; 473 uint32_t inta:8; 474 uint32_t il:8; 475 } s; 476 struct cvmx_pcieep_cfg015_s cn52xx; 477 struct cvmx_pcieep_cfg015_s cn52xxp1; 478 struct cvmx_pcieep_cfg015_s cn56xx; 479 struct cvmx_pcieep_cfg015_s cn56xxp1; 480}; 481 482union cvmx_pcieep_cfg016 { 483 uint32_t u32; 484 struct cvmx_pcieep_cfg016_s { 485 uint32_t pmes:5; 486 uint32_t d2s:1; 487 uint32_t d1s:1; 488 uint32_t auxc:3; 489 uint32_t dsi:1; 490 uint32_t reserved_20_20:1; 491 uint32_t pme_clock:1; 492 uint32_t pmsv:3; 493 uint32_t ncp:8; 494 uint32_t pmcid:8; 495 } s; 496 struct cvmx_pcieep_cfg016_s cn52xx; 497 struct cvmx_pcieep_cfg016_s cn52xxp1; 498 struct cvmx_pcieep_cfg016_s cn56xx; 499 struct cvmx_pcieep_cfg016_s cn56xxp1; 500}; 501 502union cvmx_pcieep_cfg017 { 503 uint32_t u32; 504 struct cvmx_pcieep_cfg017_s { 505 uint32_t pmdia:8; 506 uint32_t bpccee:1; 507 uint32_t bd3h:1; 508 uint32_t reserved_16_21:6; 509 uint32_t pmess:1; 510 uint32_t pmedsia:2; 511 uint32_t pmds:4; 512 uint32_t pmeens:1; 513 uint32_t reserved_4_7:4; 514 uint32_t nsr:1; 515 uint32_t reserved_2_2:1; 516 uint32_t ps:2; 517 } s; 518 struct cvmx_pcieep_cfg017_s cn52xx; 519 struct cvmx_pcieep_cfg017_s cn52xxp1; 520 struct cvmx_pcieep_cfg017_s cn56xx; 521 struct cvmx_pcieep_cfg017_s cn56xxp1; 522}; 523 524union cvmx_pcieep_cfg020 { 525 uint32_t u32; 526 struct cvmx_pcieep_cfg020_s { 527 uint32_t reserved_24_31:8; 528 uint32_t m64:1; 529 uint32_t mme:3; 530 uint32_t mmc:3; 531 uint32_t msien:1; 532 uint32_t ncp:8; 533 uint32_t msicid:8; 534 } s; 535 struct cvmx_pcieep_cfg020_s cn52xx; 536 struct cvmx_pcieep_cfg020_s cn52xxp1; 537 struct cvmx_pcieep_cfg020_s cn56xx; 538 struct cvmx_pcieep_cfg020_s cn56xxp1; 539}; 540 541union cvmx_pcieep_cfg021 { 542 uint32_t u32; 543 struct cvmx_pcieep_cfg021_s { 544 uint32_t lmsi:30; 545 uint32_t reserved_0_1:2; 546 } s; 547 struct cvmx_pcieep_cfg021_s cn52xx; 548 struct cvmx_pcieep_cfg021_s cn52xxp1; 549 struct cvmx_pcieep_cfg021_s cn56xx; 550 struct cvmx_pcieep_cfg021_s cn56xxp1; 551}; 552 553union cvmx_pcieep_cfg022 { 554 uint32_t u32; 555 struct cvmx_pcieep_cfg022_s { 556 uint32_t umsi:32; 557 } s; 558 struct cvmx_pcieep_cfg022_s cn52xx; 559 struct cvmx_pcieep_cfg022_s cn52xxp1; 560 struct cvmx_pcieep_cfg022_s cn56xx; 561 struct cvmx_pcieep_cfg022_s cn56xxp1; 562}; 563 564union cvmx_pcieep_cfg023 { 565 uint32_t u32; 566 struct cvmx_pcieep_cfg023_s { 567 uint32_t reserved_16_31:16; 568 uint32_t msimd:16; 569 } s; 570 struct cvmx_pcieep_cfg023_s cn52xx; 571 struct cvmx_pcieep_cfg023_s cn52xxp1; 572 struct cvmx_pcieep_cfg023_s cn56xx; 573 struct cvmx_pcieep_cfg023_s cn56xxp1; 574}; 575 576union cvmx_pcieep_cfg028 { 577 uint32_t u32; 578 struct cvmx_pcieep_cfg028_s { 579 uint32_t reserved_30_31:2; 580 uint32_t imn:5; 581 uint32_t si:1; 582 uint32_t dpt:4; 583 uint32_t pciecv:4; 584 uint32_t ncp:8; 585 uint32_t pcieid:8; 586 } s; 587 struct cvmx_pcieep_cfg028_s cn52xx; 588 struct cvmx_pcieep_cfg028_s cn52xxp1; 589 struct cvmx_pcieep_cfg028_s cn56xx; 590 struct cvmx_pcieep_cfg028_s cn56xxp1; 591}; 592 593union cvmx_pcieep_cfg029 { 594 uint32_t u32; 595 struct cvmx_pcieep_cfg029_s { 596 uint32_t reserved_28_31:4; 597 uint32_t cspls:2; 598 uint32_t csplv:8; 599 uint32_t reserved_16_17:2; 600 uint32_t rber:1; 601 uint32_t reserved_12_14:3; 602 uint32_t el1al:3; 603 uint32_t el0al:3; 604 uint32_t etfs:1; 605 uint32_t pfs:2; 606 uint32_t mpss:3; 607 } s; 608 struct cvmx_pcieep_cfg029_s cn52xx; 609 struct cvmx_pcieep_cfg029_s cn52xxp1; 610 struct cvmx_pcieep_cfg029_s cn56xx; 611 struct cvmx_pcieep_cfg029_s cn56xxp1; 612}; 613 614union cvmx_pcieep_cfg030 { 615 uint32_t u32; 616 struct cvmx_pcieep_cfg030_s { 617 uint32_t reserved_22_31:10; 618 uint32_t tp:1; 619 uint32_t ap_d:1; 620 uint32_t ur_d:1; 621 uint32_t fe_d:1; 622 uint32_t nfe_d:1; 623 uint32_t ce_d:1; 624 uint32_t reserved_15_15:1; 625 uint32_t mrrs:3; 626 uint32_t ns_en:1; 627 uint32_t ap_en:1; 628 uint32_t pf_en:1; 629 uint32_t etf_en:1; 630 uint32_t mps:3; 631 uint32_t ro_en:1; 632 uint32_t ur_en:1; 633 uint32_t fe_en:1; 634 uint32_t nfe_en:1; 635 uint32_t ce_en:1; 636 } s; 637 struct cvmx_pcieep_cfg030_s cn52xx; 638 struct cvmx_pcieep_cfg030_s cn52xxp1; 639 struct cvmx_pcieep_cfg030_s cn56xx; 640 struct cvmx_pcieep_cfg030_s cn56xxp1; 641}; 642 643union cvmx_pcieep_cfg031 { 644 uint32_t u32; 645 struct cvmx_pcieep_cfg031_s { 646 uint32_t pnum:8; 647 uint32_t reserved_22_23:2; 648 uint32_t lbnc:1; 649 uint32_t dllarc:1; 650 uint32_t sderc:1; 651 uint32_t cpm:1; 652 uint32_t l1el:3; 653 uint32_t l0el:3; 654 uint32_t aslpms:2; 655 uint32_t mlw:6; 656 uint32_t mls:4; 657 } s; 658 struct cvmx_pcieep_cfg031_s cn52xx; 659 struct cvmx_pcieep_cfg031_s cn52xxp1; 660 struct cvmx_pcieep_cfg031_s cn56xx; 661 struct cvmx_pcieep_cfg031_s cn56xxp1; 662}; 663 664union cvmx_pcieep_cfg032 { 665 uint32_t u32; 666 struct cvmx_pcieep_cfg032_s { 667 uint32_t reserved_30_31:2; 668 uint32_t dlla:1; 669 uint32_t scc:1; 670 uint32_t lt:1; 671 uint32_t reserved_26_26:1; 672 uint32_t nlw:6; 673 uint32_t ls:4; 674 uint32_t reserved_10_15:6; 675 uint32_t hawd:1; 676 uint32_t ecpm:1; 677 uint32_t es:1; 678 uint32_t ccc:1; 679 uint32_t rl:1; 680 uint32_t ld:1; 681 uint32_t rcb:1; 682 uint32_t reserved_2_2:1; 683 uint32_t aslpc:2; 684 } s; 685 struct cvmx_pcieep_cfg032_s cn52xx; 686 struct cvmx_pcieep_cfg032_s cn52xxp1; 687 struct cvmx_pcieep_cfg032_s cn56xx; 688 struct cvmx_pcieep_cfg032_s cn56xxp1; 689}; 690 691union cvmx_pcieep_cfg033 { 692 uint32_t u32; 693 struct cvmx_pcieep_cfg033_s { 694 uint32_t ps_num:13; 695 uint32_t nccs:1; 696 uint32_t emip:1; 697 uint32_t sp_ls:2; 698 uint32_t sp_lv:8; 699 uint32_t hp_c:1; 700 uint32_t hp_s:1; 701 uint32_t pip:1; 702 uint32_t aip:1; 703 uint32_t mrlsp:1; 704 uint32_t pcp:1; 705 uint32_t abp:1; 706 } s; 707 struct cvmx_pcieep_cfg033_s cn52xx; 708 struct cvmx_pcieep_cfg033_s cn52xxp1; 709 struct cvmx_pcieep_cfg033_s cn56xx; 710 struct cvmx_pcieep_cfg033_s cn56xxp1; 711}; 712 713union cvmx_pcieep_cfg034 { 714 uint32_t u32; 715 struct cvmx_pcieep_cfg034_s { 716 uint32_t reserved_25_31:7; 717 uint32_t dlls_c:1; 718 uint32_t emis:1; 719 uint32_t pds:1; 720 uint32_t mrlss:1; 721 uint32_t ccint_d:1; 722 uint32_t pd_c:1; 723 uint32_t mrls_c:1; 724 uint32_t pf_d:1; 725 uint32_t abp_d:1; 726 uint32_t reserved_13_15:3; 727 uint32_t dlls_en:1; 728 uint32_t emic:1; 729 uint32_t pcc:1; 730 uint32_t pic:2; 731 uint32_t aic:2; 732 uint32_t hpint_en:1; 733 uint32_t ccint_en:1; 734 uint32_t pd_en:1; 735 uint32_t mrls_en:1; 736 uint32_t pf_en:1; 737 uint32_t abp_en:1; 738 } s; 739 struct cvmx_pcieep_cfg034_s cn52xx; 740 struct cvmx_pcieep_cfg034_s cn52xxp1; 741 struct cvmx_pcieep_cfg034_s cn56xx; 742 struct cvmx_pcieep_cfg034_s cn56xxp1; 743}; 744 745union cvmx_pcieep_cfg037 { 746 uint32_t u32; 747 struct cvmx_pcieep_cfg037_s { 748 uint32_t reserved_5_31:27; 749 uint32_t ctds:1; 750 uint32_t ctrs:4; 751 } s; 752 struct cvmx_pcieep_cfg037_s cn52xx; 753 struct cvmx_pcieep_cfg037_s cn52xxp1; 754 struct cvmx_pcieep_cfg037_s cn56xx; 755 struct cvmx_pcieep_cfg037_s cn56xxp1; 756}; 757 758union cvmx_pcieep_cfg038 { 759 uint32_t u32; 760 struct cvmx_pcieep_cfg038_s { 761 uint32_t reserved_5_31:27; 762 uint32_t ctd:1; 763 uint32_t ctv:4; 764 } s; 765 struct cvmx_pcieep_cfg038_s cn52xx; 766 struct cvmx_pcieep_cfg038_s cn52xxp1; 767 struct cvmx_pcieep_cfg038_s cn56xx; 768 struct cvmx_pcieep_cfg038_s cn56xxp1; 769}; 770 771union cvmx_pcieep_cfg039 { 772 uint32_t u32; 773 struct cvmx_pcieep_cfg039_s { 774 uint32_t reserved_0_31:32; 775 } s; 776 struct cvmx_pcieep_cfg039_s cn52xx; 777 struct cvmx_pcieep_cfg039_s cn52xxp1; 778 struct cvmx_pcieep_cfg039_s cn56xx; 779 struct cvmx_pcieep_cfg039_s cn56xxp1; 780}; 781 782union cvmx_pcieep_cfg040 { 783 uint32_t u32; 784 struct cvmx_pcieep_cfg040_s { 785 uint32_t reserved_0_31:32; 786 } s; 787 struct cvmx_pcieep_cfg040_s cn52xx; 788 struct cvmx_pcieep_cfg040_s cn52xxp1; 789 struct cvmx_pcieep_cfg040_s cn56xx; 790 struct cvmx_pcieep_cfg040_s cn56xxp1; 791}; 792 793union cvmx_pcieep_cfg041 { 794 uint32_t u32; 795 struct cvmx_pcieep_cfg041_s { 796 uint32_t reserved_0_31:32; 797 } s; 798 struct cvmx_pcieep_cfg041_s cn52xx; 799 struct cvmx_pcieep_cfg041_s cn52xxp1; 800 struct cvmx_pcieep_cfg041_s cn56xx; 801 struct cvmx_pcieep_cfg041_s cn56xxp1; 802}; 803 804union cvmx_pcieep_cfg042 { 805 uint32_t u32; 806 struct cvmx_pcieep_cfg042_s { 807 uint32_t reserved_0_31:32; 808 } s; 809 struct cvmx_pcieep_cfg042_s cn52xx; 810 struct cvmx_pcieep_cfg042_s cn52xxp1; 811 struct cvmx_pcieep_cfg042_s cn56xx; 812 struct cvmx_pcieep_cfg042_s cn56xxp1; 813}; 814 815union cvmx_pcieep_cfg064 { 816 uint32_t u32; 817 struct cvmx_pcieep_cfg064_s { 818 uint32_t nco:12; 819 uint32_t cv:4; 820 uint32_t pcieec:16; 821 } s; 822 struct cvmx_pcieep_cfg064_s cn52xx; 823 struct cvmx_pcieep_cfg064_s cn52xxp1; 824 struct cvmx_pcieep_cfg064_s cn56xx; 825 struct cvmx_pcieep_cfg064_s cn56xxp1; 826}; 827 828union cvmx_pcieep_cfg065 { 829 uint32_t u32; 830 struct cvmx_pcieep_cfg065_s { 831 uint32_t reserved_21_31:11; 832 uint32_t ures:1; 833 uint32_t ecrces:1; 834 uint32_t mtlps:1; 835 uint32_t ros:1; 836 uint32_t ucs:1; 837 uint32_t cas:1; 838 uint32_t cts:1; 839 uint32_t fcpes:1; 840 uint32_t ptlps:1; 841 uint32_t reserved_6_11:6; 842 uint32_t sdes:1; 843 uint32_t dlpes:1; 844 uint32_t reserved_0_3:4; 845 } s; 846 struct cvmx_pcieep_cfg065_s cn52xx; 847 struct cvmx_pcieep_cfg065_s cn52xxp1; 848 struct cvmx_pcieep_cfg065_s cn56xx; 849 struct cvmx_pcieep_cfg065_s cn56xxp1; 850}; 851 852union cvmx_pcieep_cfg066 { 853 uint32_t u32; 854 struct cvmx_pcieep_cfg066_s { 855 uint32_t reserved_21_31:11; 856 uint32_t urem:1; 857 uint32_t ecrcem:1; 858 uint32_t mtlpm:1; 859 uint32_t rom:1; 860 uint32_t ucm:1; 861 uint32_t cam:1; 862 uint32_t ctm:1; 863 uint32_t fcpem:1; 864 uint32_t ptlpm:1; 865 uint32_t reserved_6_11:6; 866 uint32_t sdem:1; 867 uint32_t dlpem:1; 868 uint32_t reserved_0_3:4; 869 } s; 870 struct cvmx_pcieep_cfg066_s cn52xx; 871 struct cvmx_pcieep_cfg066_s cn52xxp1; 872 struct cvmx_pcieep_cfg066_s cn56xx; 873 struct cvmx_pcieep_cfg066_s cn56xxp1; 874}; 875 876union cvmx_pcieep_cfg067 { 877 uint32_t u32; 878 struct cvmx_pcieep_cfg067_s { 879 uint32_t reserved_21_31:11; 880 uint32_t ures:1; 881 uint32_t ecrces:1; 882 uint32_t mtlps:1; 883 uint32_t ros:1; 884 uint32_t ucs:1; 885 uint32_t cas:1; 886 uint32_t cts:1; 887 uint32_t fcpes:1; 888 uint32_t ptlps:1; 889 uint32_t reserved_6_11:6; 890 uint32_t sdes:1; 891 uint32_t dlpes:1; 892 uint32_t reserved_0_3:4; 893 } s; 894 struct cvmx_pcieep_cfg067_s cn52xx; 895 struct cvmx_pcieep_cfg067_s cn52xxp1; 896 struct cvmx_pcieep_cfg067_s cn56xx; 897 struct cvmx_pcieep_cfg067_s cn56xxp1; 898}; 899 900union cvmx_pcieep_cfg068 { 901 uint32_t u32; 902 struct cvmx_pcieep_cfg068_s { 903 uint32_t reserved_14_31:18; 904 uint32_t anfes:1; 905 uint32_t rtts:1; 906 uint32_t reserved_9_11:3; 907 uint32_t rnrs:1; 908 uint32_t bdllps:1; 909 uint32_t btlps:1; 910 uint32_t reserved_1_5:5; 911 uint32_t res:1; 912 } s; 913 struct cvmx_pcieep_cfg068_s cn52xx; 914 struct cvmx_pcieep_cfg068_s cn52xxp1; 915 struct cvmx_pcieep_cfg068_s cn56xx; 916 struct cvmx_pcieep_cfg068_s cn56xxp1; 917}; 918 919union cvmx_pcieep_cfg069 { 920 uint32_t u32; 921 struct cvmx_pcieep_cfg069_s { 922 uint32_t reserved_14_31:18; 923 uint32_t anfem:1; 924 uint32_t rttm:1; 925 uint32_t reserved_9_11:3; 926 uint32_t rnrm:1; 927 uint32_t bdllpm:1; 928 uint32_t btlpm:1; 929 uint32_t reserved_1_5:5; 930 uint32_t rem:1; 931 } s; 932 struct cvmx_pcieep_cfg069_s cn52xx; 933 struct cvmx_pcieep_cfg069_s cn52xxp1; 934 struct cvmx_pcieep_cfg069_s cn56xx; 935 struct cvmx_pcieep_cfg069_s cn56xxp1; 936}; 937 938union cvmx_pcieep_cfg070 { 939 uint32_t u32; 940 struct cvmx_pcieep_cfg070_s { 941 uint32_t reserved_9_31:23; 942 uint32_t ce:1; 943 uint32_t cc:1; 944 uint32_t ge:1; 945 uint32_t gc:1; 946 uint32_t fep:5; 947 } s; 948 struct cvmx_pcieep_cfg070_s cn52xx; 949 struct cvmx_pcieep_cfg070_s cn52xxp1; 950 struct cvmx_pcieep_cfg070_s cn56xx; 951 struct cvmx_pcieep_cfg070_s cn56xxp1; 952}; 953 954union cvmx_pcieep_cfg071 { 955 uint32_t u32; 956 struct cvmx_pcieep_cfg071_s { 957 uint32_t dword1:32; 958 } s; 959 struct cvmx_pcieep_cfg071_s cn52xx; 960 struct cvmx_pcieep_cfg071_s cn52xxp1; 961 struct cvmx_pcieep_cfg071_s cn56xx; 962 struct cvmx_pcieep_cfg071_s cn56xxp1; 963}; 964 965union cvmx_pcieep_cfg072 { 966 uint32_t u32; 967 struct cvmx_pcieep_cfg072_s { 968 uint32_t dword2:32; 969 } s; 970 struct cvmx_pcieep_cfg072_s cn52xx; 971 struct cvmx_pcieep_cfg072_s cn52xxp1; 972 struct cvmx_pcieep_cfg072_s cn56xx; 973 struct cvmx_pcieep_cfg072_s cn56xxp1; 974}; 975 976union cvmx_pcieep_cfg073 { 977 uint32_t u32; 978 struct cvmx_pcieep_cfg073_s { 979 uint32_t dword3:32; 980 } s; 981 struct cvmx_pcieep_cfg073_s cn52xx; 982 struct cvmx_pcieep_cfg073_s cn52xxp1; 983 struct cvmx_pcieep_cfg073_s cn56xx; 984 struct cvmx_pcieep_cfg073_s cn56xxp1; 985}; 986 987union cvmx_pcieep_cfg074 { 988 uint32_t u32; 989 struct cvmx_pcieep_cfg074_s { 990 uint32_t dword4:32; 991 } s; 992 struct cvmx_pcieep_cfg074_s cn52xx; 993 struct cvmx_pcieep_cfg074_s cn52xxp1; 994 struct cvmx_pcieep_cfg074_s cn56xx; 995 struct cvmx_pcieep_cfg074_s cn56xxp1; 996}; 997 998union cvmx_pcieep_cfg448 { 999 uint32_t u32; 1000 struct cvmx_pcieep_cfg448_s { 1001 uint32_t rtl:16; 1002 uint32_t rtltl:16; 1003 } s; 1004 struct cvmx_pcieep_cfg448_s cn52xx; 1005 struct cvmx_pcieep_cfg448_s cn52xxp1; 1006 struct cvmx_pcieep_cfg448_s cn56xx; 1007 struct cvmx_pcieep_cfg448_s cn56xxp1; 1008}; 1009 1010union cvmx_pcieep_cfg449 { 1011 uint32_t u32; 1012 struct cvmx_pcieep_cfg449_s { 1013 uint32_t omr:32; 1014 } s; 1015 struct cvmx_pcieep_cfg449_s cn52xx; 1016 struct cvmx_pcieep_cfg449_s cn52xxp1; 1017 struct cvmx_pcieep_cfg449_s cn56xx; 1018 struct cvmx_pcieep_cfg449_s cn56xxp1; 1019}; 1020 1021union cvmx_pcieep_cfg450 { 1022 uint32_t u32; 1023 struct cvmx_pcieep_cfg450_s { 1024 uint32_t lpec:8; 1025 uint32_t reserved_22_23:2; 1026 uint32_t link_state:6; 1027 uint32_t force_link:1; 1028 uint32_t reserved_8_14:7; 1029 uint32_t link_num:8; 1030 } s; 1031 struct cvmx_pcieep_cfg450_s cn52xx; 1032 struct cvmx_pcieep_cfg450_s cn52xxp1; 1033 struct cvmx_pcieep_cfg450_s cn56xx; 1034 struct cvmx_pcieep_cfg450_s cn56xxp1; 1035}; 1036 1037union cvmx_pcieep_cfg451 { 1038 uint32_t u32; 1039 struct cvmx_pcieep_cfg451_s { 1040 uint32_t reserved_30_31:2; 1041 uint32_t l1el:3; 1042 uint32_t l0el:3; 1043 uint32_t n_fts_cc:8; 1044 uint32_t n_fts:8; 1045 uint32_t ack_freq:8; 1046 } s; 1047 struct cvmx_pcieep_cfg451_s cn52xx; 1048 struct cvmx_pcieep_cfg451_s cn52xxp1; 1049 struct cvmx_pcieep_cfg451_s cn56xx; 1050 struct cvmx_pcieep_cfg451_s cn56xxp1; 1051}; 1052 1053union cvmx_pcieep_cfg452 { 1054 uint32_t u32; 1055 struct cvmx_pcieep_cfg452_s { 1056 uint32_t reserved_26_31:6; 1057 uint32_t eccrc:1; 1058 uint32_t reserved_22_24:3; 1059 uint32_t lme:6; 1060 uint32_t reserved_8_15:8; 1061 uint32_t flm:1; 1062 uint32_t reserved_6_6:1; 1063 uint32_t dllle:1; 1064 uint32_t reserved_4_4:1; 1065 uint32_t ra:1; 1066 uint32_t le:1; 1067 uint32_t sd:1; 1068 uint32_t omr:1; 1069 } s; 1070 struct cvmx_pcieep_cfg452_s cn52xx; 1071 struct cvmx_pcieep_cfg452_s cn52xxp1; 1072 struct cvmx_pcieep_cfg452_s cn56xx; 1073 struct cvmx_pcieep_cfg452_s cn56xxp1; 1074}; 1075 1076union cvmx_pcieep_cfg453 { 1077 uint32_t u32; 1078 struct cvmx_pcieep_cfg453_s { 1079 uint32_t dlld:1; 1080 uint32_t reserved_26_30:5; 1081 uint32_t ack_nak:1; 1082 uint32_t fcd:1; 1083 uint32_t ilst:24; 1084 } s; 1085 struct cvmx_pcieep_cfg453_s cn52xx; 1086 struct cvmx_pcieep_cfg453_s cn52xxp1; 1087 struct cvmx_pcieep_cfg453_s cn56xx; 1088 struct cvmx_pcieep_cfg453_s cn56xxp1; 1089}; 1090 1091union cvmx_pcieep_cfg454 { 1092 uint32_t u32; 1093 struct cvmx_pcieep_cfg454_s { 1094 uint32_t reserved_29_31:3; 1095 uint32_t tmfcwt:5; 1096 uint32_t tmanlt:5; 1097 uint32_t tmrt:5; 1098 uint32_t reserved_11_13:3; 1099 uint32_t nskps:3; 1100 uint32_t reserved_4_7:4; 1101 uint32_t ntss:4; 1102 } s; 1103 struct cvmx_pcieep_cfg454_s cn52xx; 1104 struct cvmx_pcieep_cfg454_s cn52xxp1; 1105 struct cvmx_pcieep_cfg454_s cn56xx; 1106 struct cvmx_pcieep_cfg454_s cn56xxp1; 1107}; 1108 1109union cvmx_pcieep_cfg455 { 1110 uint32_t u32; 1111 struct cvmx_pcieep_cfg455_s { 1112 uint32_t m_cfg0_filt:1; 1113 uint32_t m_io_filt:1; 1114 uint32_t msg_ctrl:1; 1115 uint32_t m_cpl_ecrc_filt:1; 1116 uint32_t m_ecrc_filt:1; 1117 uint32_t m_cpl_len_err:1; 1118 uint32_t m_cpl_attr_err:1; 1119 uint32_t m_cpl_tc_err:1; 1120 uint32_t m_cpl_fun_err:1; 1121 uint32_t m_cpl_rid_err:1; 1122 uint32_t m_cpl_tag_err:1; 1123 uint32_t m_lk_filt:1; 1124 uint32_t m_cfg1_filt:1; 1125 uint32_t m_bar_match:1; 1126 uint32_t m_pois_filt:1; 1127 uint32_t m_fun:1; 1128 uint32_t dfcwt:1; 1129 uint32_t reserved_11_14:4; 1130 uint32_t skpiv:11; 1131 } s; 1132 struct cvmx_pcieep_cfg455_s cn52xx; 1133 struct cvmx_pcieep_cfg455_s cn52xxp1; 1134 struct cvmx_pcieep_cfg455_s cn56xx; 1135 struct cvmx_pcieep_cfg455_s cn56xxp1; 1136}; 1137 1138union cvmx_pcieep_cfg456 { 1139 uint32_t u32; 1140 struct cvmx_pcieep_cfg456_s { 1141 uint32_t reserved_2_31:30; 1142 uint32_t m_vend1_drp:1; 1143 uint32_t m_vend0_drp:1; 1144 } s; 1145 struct cvmx_pcieep_cfg456_s cn52xx; 1146 struct cvmx_pcieep_cfg456_s cn52xxp1; 1147 struct cvmx_pcieep_cfg456_s cn56xx; 1148 struct cvmx_pcieep_cfg456_s cn56xxp1; 1149}; 1150 1151union cvmx_pcieep_cfg458 { 1152 uint32_t u32; 1153 struct cvmx_pcieep_cfg458_s { 1154 uint32_t dbg_info_l32:32; 1155 } s; 1156 struct cvmx_pcieep_cfg458_s cn52xx; 1157 struct cvmx_pcieep_cfg458_s cn52xxp1; 1158 struct cvmx_pcieep_cfg458_s cn56xx; 1159 struct cvmx_pcieep_cfg458_s cn56xxp1; 1160}; 1161 1162union cvmx_pcieep_cfg459 { 1163 uint32_t u32; 1164 struct cvmx_pcieep_cfg459_s { 1165 uint32_t dbg_info_u32:32; 1166 } s; 1167 struct cvmx_pcieep_cfg459_s cn52xx; 1168 struct cvmx_pcieep_cfg459_s cn52xxp1; 1169 struct cvmx_pcieep_cfg459_s cn56xx; 1170 struct cvmx_pcieep_cfg459_s cn56xxp1; 1171}; 1172 1173union cvmx_pcieep_cfg460 { 1174 uint32_t u32; 1175 struct cvmx_pcieep_cfg460_s { 1176 uint32_t reserved_20_31:12; 1177 uint32_t tphfcc:8; 1178 uint32_t tpdfcc:12; 1179 } s; 1180 struct cvmx_pcieep_cfg460_s cn52xx; 1181 struct cvmx_pcieep_cfg460_s cn52xxp1; 1182 struct cvmx_pcieep_cfg460_s cn56xx; 1183 struct cvmx_pcieep_cfg460_s cn56xxp1; 1184}; 1185 1186union cvmx_pcieep_cfg461 { 1187 uint32_t u32; 1188 struct cvmx_pcieep_cfg461_s { 1189 uint32_t reserved_20_31:12; 1190 uint32_t tchfcc:8; 1191 uint32_t tcdfcc:12; 1192 } s; 1193 struct cvmx_pcieep_cfg461_s cn52xx; 1194 struct cvmx_pcieep_cfg461_s cn52xxp1; 1195 struct cvmx_pcieep_cfg461_s cn56xx; 1196 struct cvmx_pcieep_cfg461_s cn56xxp1; 1197}; 1198 1199union cvmx_pcieep_cfg462 { 1200 uint32_t u32; 1201 struct cvmx_pcieep_cfg462_s { 1202 uint32_t reserved_20_31:12; 1203 uint32_t tchfcc:8; 1204 uint32_t tcdfcc:12; 1205 } s; 1206 struct cvmx_pcieep_cfg462_s cn52xx; 1207 struct cvmx_pcieep_cfg462_s cn52xxp1; 1208 struct cvmx_pcieep_cfg462_s cn56xx; 1209 struct cvmx_pcieep_cfg462_s cn56xxp1; 1210}; 1211 1212union cvmx_pcieep_cfg463 { 1213 uint32_t u32; 1214 struct cvmx_pcieep_cfg463_s { 1215 uint32_t reserved_3_31:29; 1216 uint32_t rqne:1; 1217 uint32_t trbne:1; 1218 uint32_t rtlpfccnr:1; 1219 } s; 1220 struct cvmx_pcieep_cfg463_s cn52xx; 1221 struct cvmx_pcieep_cfg463_s cn52xxp1; 1222 struct cvmx_pcieep_cfg463_s cn56xx; 1223 struct cvmx_pcieep_cfg463_s cn56xxp1; 1224}; 1225 1226union cvmx_pcieep_cfg464 { 1227 uint32_t u32; 1228 struct cvmx_pcieep_cfg464_s { 1229 uint32_t wrr_vc3:8; 1230 uint32_t wrr_vc2:8; 1231 uint32_t wrr_vc1:8; 1232 uint32_t wrr_vc0:8; 1233 } s; 1234 struct cvmx_pcieep_cfg464_s cn52xx; 1235 struct cvmx_pcieep_cfg464_s cn52xxp1; 1236 struct cvmx_pcieep_cfg464_s cn56xx; 1237 struct cvmx_pcieep_cfg464_s cn56xxp1; 1238}; 1239 1240union cvmx_pcieep_cfg465 { 1241 uint32_t u32; 1242 struct cvmx_pcieep_cfg465_s { 1243 uint32_t wrr_vc7:8; 1244 uint32_t wrr_vc6:8; 1245 uint32_t wrr_vc5:8; 1246 uint32_t wrr_vc4:8; 1247 } s; 1248 struct cvmx_pcieep_cfg465_s cn52xx; 1249 struct cvmx_pcieep_cfg465_s cn52xxp1; 1250 struct cvmx_pcieep_cfg465_s cn56xx; 1251 struct cvmx_pcieep_cfg465_s cn56xxp1; 1252}; 1253 1254union cvmx_pcieep_cfg466 { 1255 uint32_t u32; 1256 struct cvmx_pcieep_cfg466_s { 1257 uint32_t rx_queue_order:1; 1258 uint32_t type_ordering:1; 1259 uint32_t reserved_24_29:6; 1260 uint32_t queue_mode:3; 1261 uint32_t reserved_20_20:1; 1262 uint32_t header_credits:8; 1263 uint32_t data_credits:12; 1264 } s; 1265 struct cvmx_pcieep_cfg466_s cn52xx; 1266 struct cvmx_pcieep_cfg466_s cn52xxp1; 1267 struct cvmx_pcieep_cfg466_s cn56xx; 1268 struct cvmx_pcieep_cfg466_s cn56xxp1; 1269}; 1270 1271union cvmx_pcieep_cfg467 { 1272 uint32_t u32; 1273 struct cvmx_pcieep_cfg467_s { 1274 uint32_t reserved_24_31:8; 1275 uint32_t queue_mode:3; 1276 uint32_t reserved_20_20:1; 1277 uint32_t header_credits:8; 1278 uint32_t data_credits:12; 1279 } s; 1280 struct cvmx_pcieep_cfg467_s cn52xx; 1281 struct cvmx_pcieep_cfg467_s cn52xxp1; 1282 struct cvmx_pcieep_cfg467_s cn56xx; 1283 struct cvmx_pcieep_cfg467_s cn56xxp1; 1284}; 1285 1286union cvmx_pcieep_cfg468 { 1287 uint32_t u32; 1288 struct cvmx_pcieep_cfg468_s { 1289 uint32_t reserved_24_31:8; 1290 uint32_t queue_mode:3; 1291 uint32_t reserved_20_20:1; 1292 uint32_t header_credits:8; 1293 uint32_t data_credits:12; 1294 } s; 1295 struct cvmx_pcieep_cfg468_s cn52xx; 1296 struct cvmx_pcieep_cfg468_s cn52xxp1; 1297 struct cvmx_pcieep_cfg468_s cn56xx; 1298 struct cvmx_pcieep_cfg468_s cn56xxp1; 1299}; 1300 1301union cvmx_pcieep_cfg490 { 1302 uint32_t u32; 1303 struct cvmx_pcieep_cfg490_s { 1304 uint32_t reserved_26_31:6; 1305 uint32_t header_depth:10; 1306 uint32_t reserved_14_15:2; 1307 uint32_t data_depth:14; 1308 } s; 1309 struct cvmx_pcieep_cfg490_s cn52xx; 1310 struct cvmx_pcieep_cfg490_s cn52xxp1; 1311 struct cvmx_pcieep_cfg490_s cn56xx; 1312 struct cvmx_pcieep_cfg490_s cn56xxp1; 1313}; 1314 1315union cvmx_pcieep_cfg491 { 1316 uint32_t u32; 1317 struct cvmx_pcieep_cfg491_s { 1318 uint32_t reserved_26_31:6; 1319 uint32_t header_depth:10; 1320 uint32_t reserved_14_15:2; 1321 uint32_t data_depth:14; 1322 } s; 1323 struct cvmx_pcieep_cfg491_s cn52xx; 1324 struct cvmx_pcieep_cfg491_s cn52xxp1; 1325 struct cvmx_pcieep_cfg491_s cn56xx; 1326 struct cvmx_pcieep_cfg491_s cn56xxp1; 1327}; 1328 1329union cvmx_pcieep_cfg492 { 1330 uint32_t u32; 1331 struct cvmx_pcieep_cfg492_s { 1332 uint32_t reserved_26_31:6; 1333 uint32_t header_depth:10; 1334 uint32_t reserved_14_15:2; 1335 uint32_t data_depth:14; 1336 } s; 1337 struct cvmx_pcieep_cfg492_s cn52xx; 1338 struct cvmx_pcieep_cfg492_s cn52xxp1; 1339 struct cvmx_pcieep_cfg492_s cn56xx; 1340 struct cvmx_pcieep_cfg492_s cn56xxp1; 1341}; 1342 1343union cvmx_pcieep_cfg516 { 1344 uint32_t u32; 1345 struct cvmx_pcieep_cfg516_s { 1346 uint32_t phy_stat:32; 1347 } s; 1348 struct cvmx_pcieep_cfg516_s cn52xx; 1349 struct cvmx_pcieep_cfg516_s cn52xxp1; 1350 struct cvmx_pcieep_cfg516_s cn56xx; 1351 struct cvmx_pcieep_cfg516_s cn56xxp1; 1352}; 1353 1354union cvmx_pcieep_cfg517 { 1355 uint32_t u32; 1356 struct cvmx_pcieep_cfg517_s { 1357 uint32_t phy_ctrl:32; 1358 } s; 1359 struct cvmx_pcieep_cfg517_s cn52xx; 1360 struct cvmx_pcieep_cfg517_s cn52xxp1; 1361 struct cvmx_pcieep_cfg517_s cn56xx; 1362 struct cvmx_pcieep_cfg517_s cn56xxp1; 1363}; 1364 1365#endif 1366