1/***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2008 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28#ifndef __CVMX_MIXX_DEFS_H__ 29#define __CVMX_MIXX_DEFS_H__ 30 31#define CVMX_MIXX_BIST(offset) \ 32 CVMX_ADD_IO_SEG(0x0001070000100078ull + (((offset) & 1) * 2048)) 33#define CVMX_MIXX_CTL(offset) \ 34 CVMX_ADD_IO_SEG(0x0001070000100020ull + (((offset) & 1) * 2048)) 35#define CVMX_MIXX_INTENA(offset) \ 36 CVMX_ADD_IO_SEG(0x0001070000100050ull + (((offset) & 1) * 2048)) 37#define CVMX_MIXX_IRCNT(offset) \ 38 CVMX_ADD_IO_SEG(0x0001070000100030ull + (((offset) & 1) * 2048)) 39#define CVMX_MIXX_IRHWM(offset) \ 40 CVMX_ADD_IO_SEG(0x0001070000100028ull + (((offset) & 1) * 2048)) 41#define CVMX_MIXX_IRING1(offset) \ 42 CVMX_ADD_IO_SEG(0x0001070000100010ull + (((offset) & 1) * 2048)) 43#define CVMX_MIXX_IRING2(offset) \ 44 CVMX_ADD_IO_SEG(0x0001070000100018ull + (((offset) & 1) * 2048)) 45#define CVMX_MIXX_ISR(offset) \ 46 CVMX_ADD_IO_SEG(0x0001070000100048ull + (((offset) & 1) * 2048)) 47#define CVMX_MIXX_ORCNT(offset) \ 48 CVMX_ADD_IO_SEG(0x0001070000100040ull + (((offset) & 1) * 2048)) 49#define CVMX_MIXX_ORHWM(offset) \ 50 CVMX_ADD_IO_SEG(0x0001070000100038ull + (((offset) & 1) * 2048)) 51#define CVMX_MIXX_ORING1(offset) \ 52 CVMX_ADD_IO_SEG(0x0001070000100000ull + (((offset) & 1) * 2048)) 53#define CVMX_MIXX_ORING2(offset) \ 54 CVMX_ADD_IO_SEG(0x0001070000100008ull + (((offset) & 1) * 2048)) 55#define CVMX_MIXX_REMCNT(offset) \ 56 CVMX_ADD_IO_SEG(0x0001070000100058ull + (((offset) & 1) * 2048)) 57 58union cvmx_mixx_bist { 59 uint64_t u64; 60 struct cvmx_mixx_bist_s { 61 uint64_t reserved_4_63:60; 62 uint64_t mrqdat:1; 63 uint64_t ipfdat:1; 64 uint64_t irfdat:1; 65 uint64_t orfdat:1; 66 } s; 67 struct cvmx_mixx_bist_s cn52xx; 68 struct cvmx_mixx_bist_s cn52xxp1; 69 struct cvmx_mixx_bist_s cn56xx; 70 struct cvmx_mixx_bist_s cn56xxp1; 71}; 72 73union cvmx_mixx_ctl { 74 uint64_t u64; 75 struct cvmx_mixx_ctl_s { 76 uint64_t reserved_8_63:56; 77 uint64_t crc_strip:1; 78 uint64_t busy:1; 79 uint64_t en:1; 80 uint64_t reset:1; 81 uint64_t lendian:1; 82 uint64_t nbtarb:1; 83 uint64_t mrq_hwm:2; 84 } s; 85 struct cvmx_mixx_ctl_s cn52xx; 86 struct cvmx_mixx_ctl_s cn52xxp1; 87 struct cvmx_mixx_ctl_s cn56xx; 88 struct cvmx_mixx_ctl_s cn56xxp1; 89}; 90 91union cvmx_mixx_intena { 92 uint64_t u64; 93 struct cvmx_mixx_intena_s { 94 uint64_t reserved_7_63:57; 95 uint64_t orunena:1; 96 uint64_t irunena:1; 97 uint64_t data_drpena:1; 98 uint64_t ithena:1; 99 uint64_t othena:1; 100 uint64_t ivfena:1; 101 uint64_t ovfena:1; 102 } s; 103 struct cvmx_mixx_intena_s cn52xx; 104 struct cvmx_mixx_intena_s cn52xxp1; 105 struct cvmx_mixx_intena_s cn56xx; 106 struct cvmx_mixx_intena_s cn56xxp1; 107}; 108 109union cvmx_mixx_ircnt { 110 uint64_t u64; 111 struct cvmx_mixx_ircnt_s { 112 uint64_t reserved_20_63:44; 113 uint64_t ircnt:20; 114 } s; 115 struct cvmx_mixx_ircnt_s cn52xx; 116 struct cvmx_mixx_ircnt_s cn52xxp1; 117 struct cvmx_mixx_ircnt_s cn56xx; 118 struct cvmx_mixx_ircnt_s cn56xxp1; 119}; 120 121union cvmx_mixx_irhwm { 122 uint64_t u64; 123 struct cvmx_mixx_irhwm_s { 124 uint64_t reserved_40_63:24; 125 uint64_t ibplwm:20; 126 uint64_t irhwm:20; 127 } s; 128 struct cvmx_mixx_irhwm_s cn52xx; 129 struct cvmx_mixx_irhwm_s cn52xxp1; 130 struct cvmx_mixx_irhwm_s cn56xx; 131 struct cvmx_mixx_irhwm_s cn56xxp1; 132}; 133 134union cvmx_mixx_iring1 { 135 uint64_t u64; 136 struct cvmx_mixx_iring1_s { 137 uint64_t reserved_60_63:4; 138 uint64_t isize:20; 139 uint64_t reserved_36_39:4; 140 uint64_t ibase:33; 141 uint64_t reserved_0_2:3; 142 } s; 143 struct cvmx_mixx_iring1_s cn52xx; 144 struct cvmx_mixx_iring1_s cn52xxp1; 145 struct cvmx_mixx_iring1_s cn56xx; 146 struct cvmx_mixx_iring1_s cn56xxp1; 147}; 148 149union cvmx_mixx_iring2 { 150 uint64_t u64; 151 struct cvmx_mixx_iring2_s { 152 uint64_t reserved_52_63:12; 153 uint64_t itlptr:20; 154 uint64_t reserved_20_31:12; 155 uint64_t idbell:20; 156 } s; 157 struct cvmx_mixx_iring2_s cn52xx; 158 struct cvmx_mixx_iring2_s cn52xxp1; 159 struct cvmx_mixx_iring2_s cn56xx; 160 struct cvmx_mixx_iring2_s cn56xxp1; 161}; 162 163union cvmx_mixx_isr { 164 uint64_t u64; 165 struct cvmx_mixx_isr_s { 166 uint64_t reserved_7_63:57; 167 uint64_t orun:1; 168 uint64_t irun:1; 169 uint64_t data_drp:1; 170 uint64_t irthresh:1; 171 uint64_t orthresh:1; 172 uint64_t idblovf:1; 173 uint64_t odblovf:1; 174 } s; 175 struct cvmx_mixx_isr_s cn52xx; 176 struct cvmx_mixx_isr_s cn52xxp1; 177 struct cvmx_mixx_isr_s cn56xx; 178 struct cvmx_mixx_isr_s cn56xxp1; 179}; 180 181union cvmx_mixx_orcnt { 182 uint64_t u64; 183 struct cvmx_mixx_orcnt_s { 184 uint64_t reserved_20_63:44; 185 uint64_t orcnt:20; 186 } s; 187 struct cvmx_mixx_orcnt_s cn52xx; 188 struct cvmx_mixx_orcnt_s cn52xxp1; 189 struct cvmx_mixx_orcnt_s cn56xx; 190 struct cvmx_mixx_orcnt_s cn56xxp1; 191}; 192 193union cvmx_mixx_orhwm { 194 uint64_t u64; 195 struct cvmx_mixx_orhwm_s { 196 uint64_t reserved_20_63:44; 197 uint64_t orhwm:20; 198 } s; 199 struct cvmx_mixx_orhwm_s cn52xx; 200 struct cvmx_mixx_orhwm_s cn52xxp1; 201 struct cvmx_mixx_orhwm_s cn56xx; 202 struct cvmx_mixx_orhwm_s cn56xxp1; 203}; 204 205union cvmx_mixx_oring1 { 206 uint64_t u64; 207 struct cvmx_mixx_oring1_s { 208 uint64_t reserved_60_63:4; 209 uint64_t osize:20; 210 uint64_t reserved_36_39:4; 211 uint64_t obase:33; 212 uint64_t reserved_0_2:3; 213 } s; 214 struct cvmx_mixx_oring1_s cn52xx; 215 struct cvmx_mixx_oring1_s cn52xxp1; 216 struct cvmx_mixx_oring1_s cn56xx; 217 struct cvmx_mixx_oring1_s cn56xxp1; 218}; 219 220union cvmx_mixx_oring2 { 221 uint64_t u64; 222 struct cvmx_mixx_oring2_s { 223 uint64_t reserved_52_63:12; 224 uint64_t otlptr:20; 225 uint64_t reserved_20_31:12; 226 uint64_t odbell:20; 227 } s; 228 struct cvmx_mixx_oring2_s cn52xx; 229 struct cvmx_mixx_oring2_s cn52xxp1; 230 struct cvmx_mixx_oring2_s cn56xx; 231 struct cvmx_mixx_oring2_s cn56xxp1; 232}; 233 234union cvmx_mixx_remcnt { 235 uint64_t u64; 236 struct cvmx_mixx_remcnt_s { 237 uint64_t reserved_52_63:12; 238 uint64_t iremcnt:20; 239 uint64_t reserved_20_31:12; 240 uint64_t oremcnt:20; 241 } s; 242 struct cvmx_mixx_remcnt_s cn52xx; 243 struct cvmx_mixx_remcnt_s cn52xxp1; 244 struct cvmx_mixx_remcnt_s cn56xx; 245 struct cvmx_mixx_remcnt_s cn56xxp1; 246}; 247 248#endif 249