1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle 7 * Copyright (C) 2000 Silicon Graphics, Inc. 8 * Modified for further R[236]000 support by Paul M. Antoine, 1996. 9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 10 * Copyright (C) 2000, 07 MIPS Technologies, Inc. 11 * Copyright (C) 2003, 2004 Maciej W. Rozycki 12 */ 13#ifndef _ASM_MIPSREGS_H 14#define _ASM_MIPSREGS_H 15 16#include <linux/linkage.h> 17#include <asm/hazards.h> 18#include <asm/war.h> 19 20/* 21 * The following macros are especially useful for __asm__ 22 * inline assembler. 23 */ 24#ifndef __STR 25#define __STR(x) #x 26#endif 27#ifndef STR 28#define STR(x) __STR(x) 29#endif 30 31/* 32 * Configure language 33 */ 34#ifdef __ASSEMBLY__ 35#define _ULCAST_ 36#else 37#define _ULCAST_ (unsigned long) 38#endif 39 40/* 41 * Coprocessor 0 register names 42 */ 43#define CP0_INDEX $0 44#define CP0_RANDOM $1 45#define CP0_ENTRYLO0 $2 46#define CP0_ENTRYLO1 $3 47#define CP0_CONF $3 48#define CP0_CONTEXT $4 49#define CP0_PAGEMASK $5 50#define CP0_WIRED $6 51#define CP0_INFO $7 52#define CP0_BADVADDR $8 53#define CP0_COUNT $9 54#define CP0_ENTRYHI $10 55#define CP0_COMPARE $11 56#define CP0_STATUS $12 57#define CP0_CAUSE $13 58#define CP0_EPC $14 59#define CP0_PRID $15 60#define CP0_CONFIG $16 61#define CP0_LLADDR $17 62#define CP0_WATCHLO $18 63#define CP0_WATCHHI $19 64#define CP0_XCONTEXT $20 65#define CP0_FRAMEMASK $21 66#define CP0_DIAGNOSTIC $22 67#define CP0_DEBUG $23 68#define CP0_DEPC $24 69#define CP0_PERFORMANCE $25 70#define CP0_ECC $26 71#define CP0_CACHEERR $27 72#define CP0_TAGLO $28 73#define CP0_TAGHI $29 74#define CP0_ERROREPC $30 75#define CP0_DESAVE $31 76 77/* 78 * R4640/R4650 cp0 register names. These registers are listed 79 * here only for completeness; without MMU these CPUs are not useable 80 * by Linux. A future ELKS port might take make Linux run on them 81 * though ... 82 */ 83#define CP0_IBASE $0 84#define CP0_IBOUND $1 85#define CP0_DBASE $2 86#define CP0_DBOUND $3 87#define CP0_CALG $17 88#define CP0_IWATCH $18 89#define CP0_DWATCH $19 90 91/* 92 * Coprocessor 0 Set 1 register names 93 */ 94#define CP0_S1_DERRADDR0 $26 95#define CP0_S1_DERRADDR1 $27 96#define CP0_S1_INTCONTROL $20 97 98/* 99 * Coprocessor 0 Set 2 register names 100 */ 101#define CP0_S2_SRSCTL $12 /* MIPSR2 */ 102 103/* 104 * Coprocessor 0 Set 3 register names 105 */ 106#define CP0_S3_SRSMAP $12 /* MIPSR2 */ 107 108/* 109 * Coprocessor 0 Set 5 register names 110 */ 111#define CP0_S5_SRSMAP2 $12 /* MIPSR2 */ 112 113/* 114 * TX39 Series 115 */ 116#define CP0_TX39_CACHE $7 117 118/* 119 * Coprocessor 1 (FPU) register names 120 */ 121#define CP1_REVISION $0 122#define CP1_STATUS $31 123 124/* 125 * FPU Status Register Values 126 */ 127/* 128 * Status Register Values 129 */ 130 131#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ 132#define FPU_CSR_COND 0x00800000 /* $fcc0 */ 133#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ 134#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ 135#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ 136#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ 137#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ 138#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ 139#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ 140#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ 141 142/* 143 * Bits 18 - 20 of the FPU Status Register will be read as 0, 144 * and should be written as zero. 145 */ 146#define FPU_CSR_RSVD 0x001c0000 147 148/* 149 * X the exception cause indicator 150 * E the exception enable 151 * S the sticky/flag bit 152*/ 153#define FPU_CSR_ALL_X 0x0003f000 154#define FPU_CSR_UNI_X 0x00020000 155#define FPU_CSR_INV_X 0x00010000 156#define FPU_CSR_DIV_X 0x00008000 157#define FPU_CSR_OVF_X 0x00004000 158#define FPU_CSR_UDF_X 0x00002000 159#define FPU_CSR_INE_X 0x00001000 160 161#define FPU_CSR_ALL_E 0x00000f80 162#define FPU_CSR_INV_E 0x00000800 163#define FPU_CSR_DIV_E 0x00000400 164#define FPU_CSR_OVF_E 0x00000200 165#define FPU_CSR_UDF_E 0x00000100 166#define FPU_CSR_INE_E 0x00000080 167 168#define FPU_CSR_ALL_S 0x0000007c 169#define FPU_CSR_INV_S 0x00000040 170#define FPU_CSR_DIV_S 0x00000020 171#define FPU_CSR_OVF_S 0x00000010 172#define FPU_CSR_UDF_S 0x00000008 173#define FPU_CSR_INE_S 0x00000004 174 175/* Bits 0 and 1 of FPU Status Register specify the rounding mode */ 176#define FPU_CSR_RM 0x00000003 177#define FPU_CSR_RN 0x0 /* nearest */ 178#define FPU_CSR_RZ 0x1 /* towards zero */ 179#define FPU_CSR_RU 0x2 /* towards +Infinity */ 180#define FPU_CSR_RD 0x3 /* towards -Infinity */ 181 182 183/* 184 * Values for PageMask register 185 */ 186#ifdef CONFIG_CPU_VR41XX 187 188/* Why doesn't stupidity hurt ... */ 189 190#define PM_1K 0x00000000 191#define PM_4K 0x00001800 192#define PM_16K 0x00007800 193#define PM_64K 0x0001f800 194#define PM_256K 0x0007f800 195 196#else 197 198#define PM_4K 0x00000000 199#define PM_8K 0x00002000 200#define PM_16K 0x00006000 201#define PM_32K 0x0000e000 202#define PM_64K 0x0001e000 203#define PM_128K 0x0003e000 204#define PM_256K 0x0007e000 205#define PM_512K 0x000fe000 206#define PM_1M 0x001fe000 207#define PM_2M 0x003fe000 208#define PM_4M 0x007fe000 209#define PM_8M 0x00ffe000 210#define PM_16M 0x01ffe000 211#define PM_32M 0x03ffe000 212#define PM_64M 0x07ffe000 213#define PM_256M 0x1fffe000 214#define PM_1G 0x7fffe000 215 216#endif 217 218/* 219 * Default page size for a given kernel configuration 220 */ 221#ifdef CONFIG_PAGE_SIZE_4KB 222#define PM_DEFAULT_MASK PM_4K 223#elif defined(CONFIG_PAGE_SIZE_8KB) 224#define PM_DEFAULT_MASK PM_8K 225#elif defined(CONFIG_PAGE_SIZE_16KB) 226#define PM_DEFAULT_MASK PM_16K 227#elif defined(CONFIG_PAGE_SIZE_32KB) 228#define PM_DEFAULT_MASK PM_32K 229#elif defined(CONFIG_PAGE_SIZE_64KB) 230#define PM_DEFAULT_MASK PM_64K 231#else 232#error Bad page size configuration! 233#endif 234 235/* 236 * Default huge tlb size for a given kernel configuration 237 */ 238#ifdef CONFIG_PAGE_SIZE_4KB 239#define PM_HUGE_MASK PM_1M 240#elif defined(CONFIG_PAGE_SIZE_8KB) 241#define PM_HUGE_MASK PM_4M 242#elif defined(CONFIG_PAGE_SIZE_16KB) 243#define PM_HUGE_MASK PM_16M 244#elif defined(CONFIG_PAGE_SIZE_32KB) 245#define PM_HUGE_MASK PM_64M 246#elif defined(CONFIG_PAGE_SIZE_64KB) 247#define PM_HUGE_MASK PM_256M 248#elif defined(CONFIG_HUGETLB_PAGE) 249#error Bad page size configuration for hugetlbfs! 250#endif 251 252/* 253 * Values used for computation of new tlb entries 254 */ 255#define PL_4K 12 256#define PL_16K 14 257#define PL_64K 16 258#define PL_256K 18 259#define PL_1M 20 260#define PL_4M 22 261#define PL_16M 24 262#define PL_64M 26 263#define PL_256M 28 264 265/* 266 * PageGrain bits 267 */ 268#define PG_RIE (_ULCAST_(1) << 31) 269#define PG_XIE (_ULCAST_(1) << 30) 270#define PG_ELPA (_ULCAST_(1) << 29) 271#define PG_ESP (_ULCAST_(1) << 28) 272 273/* 274 * R4x00 interrupt enable / cause bits 275 */ 276#define IE_SW0 (_ULCAST_(1) << 8) 277#define IE_SW1 (_ULCAST_(1) << 9) 278#define IE_IRQ0 (_ULCAST_(1) << 10) 279#define IE_IRQ1 (_ULCAST_(1) << 11) 280#define IE_IRQ2 (_ULCAST_(1) << 12) 281#define IE_IRQ3 (_ULCAST_(1) << 13) 282#define IE_IRQ4 (_ULCAST_(1) << 14) 283#define IE_IRQ5 (_ULCAST_(1) << 15) 284 285/* 286 * R4x00 interrupt cause bits 287 */ 288#define C_SW0 (_ULCAST_(1) << 8) 289#define C_SW1 (_ULCAST_(1) << 9) 290#define C_IRQ0 (_ULCAST_(1) << 10) 291#define C_IRQ1 (_ULCAST_(1) << 11) 292#define C_IRQ2 (_ULCAST_(1) << 12) 293#define C_IRQ3 (_ULCAST_(1) << 13) 294#define C_IRQ4 (_ULCAST_(1) << 14) 295#define C_IRQ5 (_ULCAST_(1) << 15) 296 297/* 298 * Bitfields in the R4xx0 cp0 status register 299 */ 300#define ST0_IE 0x00000001 301#define ST0_EXL 0x00000002 302#define ST0_ERL 0x00000004 303#define ST0_KSU 0x00000018 304# define KSU_USER 0x00000010 305# define KSU_SUPERVISOR 0x00000008 306# define KSU_KERNEL 0x00000000 307#define ST0_UX 0x00000020 308#define ST0_SX 0x00000040 309#define ST0_KX 0x00000080 310#define ST0_DE 0x00010000 311#define ST0_CE 0x00020000 312 313/* 314 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate 315 * cacheops in userspace. This bit exists only on RM7000 and RM9000 316 * processors. 317 */ 318#define ST0_CO 0x08000000 319 320/* 321 * Bitfields in the R[23]000 cp0 status register. 322 */ 323#define ST0_IEC 0x00000001 324#define ST0_KUC 0x00000002 325#define ST0_IEP 0x00000004 326#define ST0_KUP 0x00000008 327#define ST0_IEO 0x00000010 328#define ST0_KUO 0x00000020 329/* bits 6 & 7 are reserved on R[23]000 */ 330#define ST0_ISC 0x00010000 331#define ST0_SWC 0x00020000 332#define ST0_CM 0x00080000 333 334/* 335 * Bits specific to the R4640/R4650 336 */ 337#define ST0_UM (_ULCAST_(1) << 4) 338#define ST0_IL (_ULCAST_(1) << 23) 339#define ST0_DL (_ULCAST_(1) << 24) 340 341/* 342 * Enable the MIPS MDMX and DSP ASEs 343 */ 344#define ST0_MX 0x01000000 345 346/* 347 * Bitfields in the TX39 family CP0 Configuration Register 3 348 */ 349#define TX39_CONF_ICS_SHIFT 19 350#define TX39_CONF_ICS_MASK 0x00380000 351#define TX39_CONF_ICS_1KB 0x00000000 352#define TX39_CONF_ICS_2KB 0x00080000 353#define TX39_CONF_ICS_4KB 0x00100000 354#define TX39_CONF_ICS_8KB 0x00180000 355#define TX39_CONF_ICS_16KB 0x00200000 356 357#define TX39_CONF_DCS_SHIFT 16 358#define TX39_CONF_DCS_MASK 0x00070000 359#define TX39_CONF_DCS_1KB 0x00000000 360#define TX39_CONF_DCS_2KB 0x00010000 361#define TX39_CONF_DCS_4KB 0x00020000 362#define TX39_CONF_DCS_8KB 0x00030000 363#define TX39_CONF_DCS_16KB 0x00040000 364 365#define TX39_CONF_CWFON 0x00004000 366#define TX39_CONF_WBON 0x00002000 367#define TX39_CONF_RF_SHIFT 10 368#define TX39_CONF_RF_MASK 0x00000c00 369#define TX39_CONF_DOZE 0x00000200 370#define TX39_CONF_HALT 0x00000100 371#define TX39_CONF_LOCK 0x00000080 372#define TX39_CONF_ICE 0x00000020 373#define TX39_CONF_DCE 0x00000010 374#define TX39_CONF_IRSIZE_SHIFT 2 375#define TX39_CONF_IRSIZE_MASK 0x0000000c 376#define TX39_CONF_DRSIZE_SHIFT 0 377#define TX39_CONF_DRSIZE_MASK 0x00000003 378 379/* 380 * Status register bits available in all MIPS CPUs. 381 */ 382#define ST0_IM 0x0000ff00 383#define STATUSB_IP0 8 384#define STATUSF_IP0 (_ULCAST_(1) << 8) 385#define STATUSB_IP1 9 386#define STATUSF_IP1 (_ULCAST_(1) << 9) 387#define STATUSB_IP2 10 388#define STATUSF_IP2 (_ULCAST_(1) << 10) 389#define STATUSB_IP3 11 390#define STATUSF_IP3 (_ULCAST_(1) << 11) 391#define STATUSB_IP4 12 392#define STATUSF_IP4 (_ULCAST_(1) << 12) 393#define STATUSB_IP5 13 394#define STATUSF_IP5 (_ULCAST_(1) << 13) 395#define STATUSB_IP6 14 396#define STATUSF_IP6 (_ULCAST_(1) << 14) 397#define STATUSB_IP7 15 398#define STATUSF_IP7 (_ULCAST_(1) << 15) 399#define STATUSB_IP8 0 400#define STATUSF_IP8 (_ULCAST_(1) << 0) 401#define STATUSB_IP9 1 402#define STATUSF_IP9 (_ULCAST_(1) << 1) 403#define STATUSB_IP10 2 404#define STATUSF_IP10 (_ULCAST_(1) << 2) 405#define STATUSB_IP11 3 406#define STATUSF_IP11 (_ULCAST_(1) << 3) 407#define STATUSB_IP12 4 408#define STATUSF_IP12 (_ULCAST_(1) << 4) 409#define STATUSB_IP13 5 410#define STATUSF_IP13 (_ULCAST_(1) << 5) 411#define STATUSB_IP14 6 412#define STATUSF_IP14 (_ULCAST_(1) << 6) 413#define STATUSB_IP15 7 414#define STATUSF_IP15 (_ULCAST_(1) << 7) 415#define ST0_CH 0x00040000 416#define ST0_NMI 0x00080000 417#define ST0_SR 0x00100000 418#define ST0_TS 0x00200000 419#define ST0_BEV 0x00400000 420#define ST0_RE 0x02000000 421#define ST0_FR 0x04000000 422#define ST0_CU 0xf0000000 423#define ST0_CU0 0x10000000 424#define ST0_CU1 0x20000000 425#define ST0_CU2 0x40000000 426#define ST0_CU3 0x80000000 427#define ST0_XX 0x80000000 /* MIPS IV naming */ 428 429/* 430 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2) 431 * 432 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 433 */ 434#define INTCTLB_IPPCI 26 435#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI) 436#define INTCTLB_IPTI 29 437#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI) 438 439/* 440 * Bitfields and bit numbers in the coprocessor 0 cause register. 441 * 442 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 443 */ 444#define CAUSEB_EXCCODE 2 445#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) 446#define CAUSEB_IP 8 447#define CAUSEF_IP (_ULCAST_(255) << 8) 448#define CAUSEB_IP0 8 449#define CAUSEF_IP0 (_ULCAST_(1) << 8) 450#define CAUSEB_IP1 9 451#define CAUSEF_IP1 (_ULCAST_(1) << 9) 452#define CAUSEB_IP2 10 453#define CAUSEF_IP2 (_ULCAST_(1) << 10) 454#define CAUSEB_IP3 11 455#define CAUSEF_IP3 (_ULCAST_(1) << 11) 456#define CAUSEB_IP4 12 457#define CAUSEF_IP4 (_ULCAST_(1) << 12) 458#define CAUSEB_IP5 13 459#define CAUSEF_IP5 (_ULCAST_(1) << 13) 460#define CAUSEB_IP6 14 461#define CAUSEF_IP6 (_ULCAST_(1) << 14) 462#define CAUSEB_IP7 15 463#define CAUSEF_IP7 (_ULCAST_(1) << 15) 464#define CAUSEB_IV 23 465#define CAUSEF_IV (_ULCAST_(1) << 23) 466#define CAUSEB_CE 28 467#define CAUSEF_CE (_ULCAST_(3) << 28) 468#define CAUSEB_TI 30 469#define CAUSEF_TI (_ULCAST_(1) << 30) 470#define CAUSEB_BD 31 471#define CAUSEF_BD (_ULCAST_(1) << 31) 472 473/* 474 * Bits in the coprocessor 0 config register. 475 */ 476/* Generic bits. */ 477#define CONF_CM_CACHABLE_NO_WA 0 478#define CONF_CM_CACHABLE_WA 1 479#define CONF_CM_UNCACHED 2 480#define CONF_CM_CACHABLE_NONCOHERENT 3 481#define CONF_CM_CACHABLE_CE 4 482#define CONF_CM_CACHABLE_COW 5 483#define CONF_CM_CACHABLE_CUW 6 484#define CONF_CM_CACHABLE_ACCELERATED 7 485#define CONF_CM_CMASK 7 486#define CONF_BE (_ULCAST_(1) << 15) 487 488/* Bits common to various processors. */ 489#define CONF_CU (_ULCAST_(1) << 3) 490#define CONF_DB (_ULCAST_(1) << 4) 491#define CONF_IB (_ULCAST_(1) << 5) 492#define CONF_DC (_ULCAST_(7) << 6) 493#define CONF_IC (_ULCAST_(7) << 9) 494#define CONF_EB (_ULCAST_(1) << 13) 495#define CONF_EM (_ULCAST_(1) << 14) 496#define CONF_SM (_ULCAST_(1) << 16) 497#define CONF_SC (_ULCAST_(1) << 17) 498#define CONF_EW (_ULCAST_(3) << 18) 499#define CONF_EP (_ULCAST_(15)<< 24) 500#define CONF_EC (_ULCAST_(7) << 28) 501#define CONF_CM (_ULCAST_(1) << 31) 502 503/* Bits specific to the R4xx0. */ 504#define R4K_CONF_SW (_ULCAST_(1) << 20) 505#define R4K_CONF_SS (_ULCAST_(1) << 21) 506#define R4K_CONF_SB (_ULCAST_(3) << 22) 507 508/* Bits specific to the R5000. */ 509#define R5K_CONF_SE (_ULCAST_(1) << 12) 510#define R5K_CONF_SS (_ULCAST_(3) << 20) 511 512/* Bits specific to the RM7000. */ 513#define RM7K_CONF_SE (_ULCAST_(1) << 3) 514#define RM7K_CONF_TE (_ULCAST_(1) << 12) 515#define RM7K_CONF_CLK (_ULCAST_(1) << 16) 516#define RM7K_CONF_TC (_ULCAST_(1) << 17) 517#define RM7K_CONF_SI (_ULCAST_(3) << 20) 518#define RM7K_CONF_SC (_ULCAST_(1) << 31) 519 520/* Bits specific to the R10000. */ 521#define R10K_CONF_DN (_ULCAST_(3) << 3) 522#define R10K_CONF_CT (_ULCAST_(1) << 5) 523#define R10K_CONF_PE (_ULCAST_(1) << 6) 524#define R10K_CONF_PM (_ULCAST_(3) << 7) 525#define R10K_CONF_EC (_ULCAST_(15)<< 9) 526#define R10K_CONF_SB (_ULCAST_(1) << 13) 527#define R10K_CONF_SK (_ULCAST_(1) << 14) 528#define R10K_CONF_SS (_ULCAST_(7) << 16) 529#define R10K_CONF_SC (_ULCAST_(7) << 19) 530#define R10K_CONF_DC (_ULCAST_(7) << 26) 531#define R10K_CONF_IC (_ULCAST_(7) << 29) 532 533/* Bits specific to the VR41xx. */ 534#define VR41_CONF_CS (_ULCAST_(1) << 12) 535#define VR41_CONF_P4K (_ULCAST_(1) << 13) 536#define VR41_CONF_BP (_ULCAST_(1) << 16) 537#define VR41_CONF_M16 (_ULCAST_(1) << 20) 538#define VR41_CONF_AD (_ULCAST_(1) << 23) 539 540/* Bits specific to the R30xx. */ 541#define R30XX_CONF_FDM (_ULCAST_(1) << 19) 542#define R30XX_CONF_REV (_ULCAST_(1) << 22) 543#define R30XX_CONF_AC (_ULCAST_(1) << 23) 544#define R30XX_CONF_RF (_ULCAST_(1) << 24) 545#define R30XX_CONF_HALT (_ULCAST_(1) << 25) 546#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) 547#define R30XX_CONF_DBR (_ULCAST_(1) << 29) 548#define R30XX_CONF_SB (_ULCAST_(1) << 30) 549#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) 550 551/* Bits specific to the TX49. */ 552#define TX49_CONF_DC (_ULCAST_(1) << 16) 553#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ 554#define TX49_CONF_HALT (_ULCAST_(1) << 18) 555#define TX49_CONF_CWFON (_ULCAST_(1) << 27) 556 557/* Bits specific to the MIPS32/64 PRA. */ 558#define MIPS_CONF_MT (_ULCAST_(7) << 7) 559#define MIPS_CONF_AR (_ULCAST_(7) << 10) 560#define MIPS_CONF_AT (_ULCAST_(3) << 13) 561#define MIPS_CONF_M (_ULCAST_(1) << 31) 562 563/* 564 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. 565 */ 566#define MIPS_CONF1_FP (_ULCAST_(1) << 0) 567#define MIPS_CONF1_EP (_ULCAST_(1) << 1) 568#define MIPS_CONF1_CA (_ULCAST_(1) << 2) 569#define MIPS_CONF1_WR (_ULCAST_(1) << 3) 570#define MIPS_CONF1_PC (_ULCAST_(1) << 4) 571#define MIPS_CONF1_MD (_ULCAST_(1) << 5) 572#define MIPS_CONF1_C2 (_ULCAST_(1) << 6) 573#define MIPS_CONF1_DA (_ULCAST_(7) << 7) 574#define MIPS_CONF1_DL (_ULCAST_(7) << 10) 575#define MIPS_CONF1_DS (_ULCAST_(7) << 13) 576#define MIPS_CONF1_IA (_ULCAST_(7) << 16) 577#define MIPS_CONF1_IL (_ULCAST_(7) << 19) 578#define MIPS_CONF1_IS (_ULCAST_(7) << 22) 579#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) 580 581#define MIPS_CONF2_SA (_ULCAST_(15)<< 0) 582#define MIPS_CONF2_SL (_ULCAST_(15)<< 4) 583#define MIPS_CONF2_SS (_ULCAST_(15)<< 8) 584#define MIPS_CONF2_SU (_ULCAST_(15)<< 12) 585#define MIPS_CONF2_TA (_ULCAST_(15)<< 16) 586#define MIPS_CONF2_TL (_ULCAST_(15)<< 20) 587#define MIPS_CONF2_TS (_ULCAST_(15)<< 24) 588#define MIPS_CONF2_TU (_ULCAST_(7) << 28) 589 590#define MIPS_CONF3_TL (_ULCAST_(1) << 0) 591#define MIPS_CONF3_SM (_ULCAST_(1) << 1) 592#define MIPS_CONF3_MT (_ULCAST_(1) << 2) 593#define MIPS_CONF3_SP (_ULCAST_(1) << 4) 594#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 595#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 596#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 597#define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9) 598#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 599#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 600#define MIPS_CONF3_ISA (_ULCAST_(3) << 14) 601 602#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 603#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 604#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) 605 606#define MIPS_CONF6_SYND (_ULCAST_(1) << 13) 607 608#define MIPS_CONF7_WII (_ULCAST_(1) << 31) 609#define MIPS_CONF7_AR (_ULCAST_(1) << 16) 610#define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 611 612 613/* 614 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. 615 */ 616#define MIPS_FPIR_S (_ULCAST_(1) << 16) 617#define MIPS_FPIR_D (_ULCAST_(1) << 17) 618#define MIPS_FPIR_PS (_ULCAST_(1) << 18) 619#define MIPS_FPIR_3D (_ULCAST_(1) << 19) 620#define MIPS_FPIR_W (_ULCAST_(1) << 20) 621#define MIPS_FPIR_L (_ULCAST_(1) << 21) 622#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 623 624#ifndef __ASSEMBLY__ 625 626/* 627 * Functions to access the R10000 performance counters. These are basically 628 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit 629 * performance counter number encoded into bits 1 ... 5 of the instruction. 630 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware 631 * disassembler these will look like an access to sel 0 or 1. 632 */ 633#define read_r10k_perf_cntr(counter) \ 634({ \ 635 unsigned int __res; \ 636 __asm__ __volatile__( \ 637 "mfpc\t%0, %1" \ 638 : "=r" (__res) \ 639 : "i" (counter)); \ 640 \ 641 __res; \ 642}) 643 644#define write_r10k_perf_cntr(counter,val) \ 645do { \ 646 __asm__ __volatile__( \ 647 "mtpc\t%0, %1" \ 648 : \ 649 : "r" (val), "i" (counter)); \ 650} while (0) 651 652#define read_r10k_perf_event(counter) \ 653({ \ 654 unsigned int __res; \ 655 __asm__ __volatile__( \ 656 "mfps\t%0, %1" \ 657 : "=r" (__res) \ 658 : "i" (counter)); \ 659 \ 660 __res; \ 661}) 662 663#define write_r10k_perf_cntl(counter,val) \ 664do { \ 665 __asm__ __volatile__( \ 666 "mtps\t%0, %1" \ 667 : \ 668 : "r" (val), "i" (counter)); \ 669} while (0) 670 671 672/* 673 * Macros to access the system control coprocessor 674 */ 675 676#define __read_32bit_c0_register(source, sel) \ 677({ int __res; \ 678 if (sel == 0) \ 679 __asm__ __volatile__( \ 680 "mfc0\t%0, " #source "\n\t" \ 681 : "=r" (__res)); \ 682 else \ 683 __asm__ __volatile__( \ 684 ".set\tmips32\n\t" \ 685 "mfc0\t%0, " #source ", " #sel "\n\t" \ 686 ".set\tmips0\n\t" \ 687 : "=r" (__res)); \ 688 __res; \ 689}) 690 691#define __read_64bit_c0_register(source, sel) \ 692({ unsigned long long __res; \ 693 if (sizeof(unsigned long) == 4) \ 694 __res = __read_64bit_c0_split(source, sel); \ 695 else if (sel == 0) \ 696 __asm__ __volatile__( \ 697 ".set\tmips3\n\t" \ 698 "dmfc0\t%0, " #source "\n\t" \ 699 ".set\tmips0" \ 700 : "=r" (__res)); \ 701 else \ 702 __asm__ __volatile__( \ 703 ".set\tmips64\n\t" \ 704 "dmfc0\t%0, " #source ", " #sel "\n\t" \ 705 ".set\tmips0" \ 706 : "=r" (__res)); \ 707 __res; \ 708}) 709 710#define __write_32bit_c0_register(register, sel, value) \ 711do { \ 712 if (sel == 0) \ 713 __asm__ __volatile__( \ 714 "mtc0\t%z0, " #register "\n\t" \ 715 : : "Jr" ((unsigned int)(value))); \ 716 else \ 717 __asm__ __volatile__( \ 718 ".set\tmips32\n\t" \ 719 "mtc0\t%z0, " #register ", " #sel "\n\t" \ 720 ".set\tmips0" \ 721 : : "Jr" ((unsigned int)(value))); \ 722} while (0) 723 724#define __write_64bit_c0_register(register, sel, value) \ 725do { \ 726 if (sizeof(unsigned long) == 4) \ 727 __write_64bit_c0_split(register, sel, value); \ 728 else if (sel == 0) \ 729 __asm__ __volatile__( \ 730 ".set\tmips3\n\t" \ 731 "dmtc0\t%z0, " #register "\n\t" \ 732 ".set\tmips0" \ 733 : : "Jr" (value)); \ 734 else \ 735 __asm__ __volatile__( \ 736 ".set\tmips64\n\t" \ 737 "dmtc0\t%z0, " #register ", " #sel "\n\t" \ 738 ".set\tmips0" \ 739 : : "Jr" (value)); \ 740} while (0) 741 742#define __read_ulong_c0_register(reg, sel) \ 743 ((sizeof(unsigned long) == 4) ? \ 744 (unsigned long) __read_32bit_c0_register(reg, sel) : \ 745 (unsigned long) __read_64bit_c0_register(reg, sel)) 746 747#define __write_ulong_c0_register(reg, sel, val) \ 748do { \ 749 if (sizeof(unsigned long) == 4) \ 750 __write_32bit_c0_register(reg, sel, val); \ 751 else \ 752 __write_64bit_c0_register(reg, sel, val); \ 753} while (0) 754 755/* 756 * On RM7000/RM9000 these are uses to access cop0 set 1 registers 757 */ 758#define __read_32bit_c0_ctrl_register(source) \ 759({ int __res; \ 760 __asm__ __volatile__( \ 761 "cfc0\t%0, " #source "\n\t" \ 762 : "=r" (__res)); \ 763 __res; \ 764}) 765 766#define __write_32bit_c0_ctrl_register(register, value) \ 767do { \ 768 __asm__ __volatile__( \ 769 "ctc0\t%z0, " #register "\n\t" \ 770 : : "Jr" ((unsigned int)(value))); \ 771} while (0) 772 773/* 774 * These versions are only needed for systems with more than 38 bits of 775 * physical address space running the 32-bit kernel. That's none atm :-) 776 */ 777#define __read_64bit_c0_split(source, sel) \ 778({ \ 779 unsigned long long __val; \ 780 unsigned long __flags; \ 781 \ 782 local_irq_save(__flags); \ 783 if (sel == 0) \ 784 __asm__ __volatile__( \ 785 ".set\tmips64\n\t" \ 786 "dmfc0\t%M0, " #source "\n\t" \ 787 "dsll\t%L0, %M0, 32\n\t" \ 788 "dsra\t%M0, %M0, 32\n\t" \ 789 "dsra\t%L0, %L0, 32\n\t" \ 790 ".set\tmips0" \ 791 : "=r" (__val)); \ 792 else \ 793 __asm__ __volatile__( \ 794 ".set\tmips64\n\t" \ 795 "dmfc0\t%M0, " #source ", " #sel "\n\t" \ 796 "dsll\t%L0, %M0, 32\n\t" \ 797 "dsra\t%M0, %M0, 32\n\t" \ 798 "dsra\t%L0, %L0, 32\n\t" \ 799 ".set\tmips0" \ 800 : "=r" (__val)); \ 801 local_irq_restore(__flags); \ 802 \ 803 __val; \ 804}) 805 806#define __write_64bit_c0_split(source, sel, val) \ 807do { \ 808 unsigned long __flags; \ 809 \ 810 local_irq_save(__flags); \ 811 if (sel == 0) \ 812 __asm__ __volatile__( \ 813 ".set\tmips64\n\t" \ 814 "dsll\t%L0, %L0, 32\n\t" \ 815 "dsrl\t%L0, %L0, 32\n\t" \ 816 "dsll\t%M0, %M0, 32\n\t" \ 817 "or\t%L0, %L0, %M0\n\t" \ 818 "dmtc0\t%L0, " #source "\n\t" \ 819 ".set\tmips0" \ 820 : : "r" (val)); \ 821 else \ 822 __asm__ __volatile__( \ 823 ".set\tmips64\n\t" \ 824 "dsll\t%L0, %L0, 32\n\t" \ 825 "dsrl\t%L0, %L0, 32\n\t" \ 826 "dsll\t%M0, %M0, 32\n\t" \ 827 "or\t%L0, %L0, %M0\n\t" \ 828 "dmtc0\t%L0, " #source ", " #sel "\n\t" \ 829 ".set\tmips0" \ 830 : : "r" (val)); \ 831 local_irq_restore(__flags); \ 832} while (0) 833 834#define read_c0_index() __read_32bit_c0_register($0, 0) 835#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) 836 837#define read_c0_random() __read_32bit_c0_register($1, 0) 838#define write_c0_random(val) __write_32bit_c0_register($1, 0, val) 839 840#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) 841#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) 842 843#define read_c0_entrylo1() __read_ulong_c0_register($3, 0) 844#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) 845 846#define read_c0_conf() __read_32bit_c0_register($3, 0) 847#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) 848 849#define read_c0_context() __read_ulong_c0_register($4, 0) 850#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) 851 852#define read_c0_contextconfig() __read_ulong_c0_register($4, 1) 853#define write_c0_contextconfig(val) __write_ulong_c0_register($4, 1, val) 854 855#define read_c0_userlocal() __read_ulong_c0_register($4, 2) 856#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) 857 858#define read_c0_pagemask() __read_32bit_c0_register($5, 0) 859#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 860 861#define read_c0_pagegrain() __read_32bit_c0_register($5, 1) 862#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) 863 864#define read_c0_wired() __read_32bit_c0_register($6, 0) 865#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) 866 867#define read_c0_info() __read_32bit_c0_register($7, 0) 868 869#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ 870#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) 871 872#define read_c0_badvaddr() __read_ulong_c0_register($8, 0) 873#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) 874 875#define read_c0_count() __read_32bit_c0_register($9, 0) 876#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) 877 878#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ 879#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) 880 881#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ 882#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) 883 884#define read_c0_entryhi() __read_ulong_c0_register($10, 0) 885#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) 886 887#define read_c0_compare() __read_32bit_c0_register($11, 0) 888#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) 889 890#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ 891#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) 892 893#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ 894#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) 895 896#define read_c0_status() __read_32bit_c0_register($12, 0) 897#ifdef CONFIG_MIPS_MT_SMTC 898#define write_c0_status(val) \ 899do { \ 900 __write_32bit_c0_register($12, 0, val); \ 901 __ehb(); \ 902} while (0) 903#else 904/* 905 * Legacy non-SMTC code, which may be hazardous 906 * but which might not support EHB 907 */ 908#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 909#endif /* CONFIG_MIPS_MT_SMTC */ 910 911#define read_c0_cause() __read_32bit_c0_register($13, 0) 912#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) 913 914#define read_c0_epc() __read_ulong_c0_register($14, 0) 915#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) 916 917#define read_c0_prid() __read_32bit_c0_register($15, 0) 918 919#define read_c0_config() __read_32bit_c0_register($16, 0) 920#define read_c0_config1() __read_32bit_c0_register($16, 1) 921#define read_c0_config2() __read_32bit_c0_register($16, 2) 922#define read_c0_config3() __read_32bit_c0_register($16, 3) 923#define read_c0_config4() __read_32bit_c0_register($16, 4) 924#define read_c0_config5() __read_32bit_c0_register($16, 5) 925#define read_c0_config6() __read_32bit_c0_register($16, 6) 926#define read_c0_config7() __read_32bit_c0_register($16, 7) 927#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) 928#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) 929#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) 930#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) 931#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) 932#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) 933#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) 934#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) 935 936/* 937 * The WatchLo register. There may be upto 8 of them. 938 */ 939#define read_c0_watchlo0() __read_ulong_c0_register($18, 0) 940#define read_c0_watchlo1() __read_ulong_c0_register($18, 1) 941#define read_c0_watchlo2() __read_ulong_c0_register($18, 2) 942#define read_c0_watchlo3() __read_ulong_c0_register($18, 3) 943#define read_c0_watchlo4() __read_ulong_c0_register($18, 4) 944#define read_c0_watchlo5() __read_ulong_c0_register($18, 5) 945#define read_c0_watchlo6() __read_ulong_c0_register($18, 6) 946#define read_c0_watchlo7() __read_ulong_c0_register($18, 7) 947#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) 948#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) 949#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) 950#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) 951#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) 952#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) 953#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) 954#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) 955 956/* 957 * The WatchHi register. There may be upto 8 of them. 958 */ 959#define read_c0_watchhi0() __read_32bit_c0_register($19, 0) 960#define read_c0_watchhi1() __read_32bit_c0_register($19, 1) 961#define read_c0_watchhi2() __read_32bit_c0_register($19, 2) 962#define read_c0_watchhi3() __read_32bit_c0_register($19, 3) 963#define read_c0_watchhi4() __read_32bit_c0_register($19, 4) 964#define read_c0_watchhi5() __read_32bit_c0_register($19, 5) 965#define read_c0_watchhi6() __read_32bit_c0_register($19, 6) 966#define read_c0_watchhi7() __read_32bit_c0_register($19, 7) 967 968#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) 969#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) 970#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) 971#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) 972#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) 973#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) 974#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) 975#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) 976 977#define read_c0_xcontext() __read_ulong_c0_register($20, 0) 978#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) 979 980#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) 981#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) 982 983#define read_c0_framemask() __read_32bit_c0_register($21, 0) 984#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) 985 986/* RM9000 PerfControl performance counter control register */ 987#define read_c0_perfcontrol() __read_32bit_c0_register($22, 0) 988#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val) 989 990#define read_c0_diag() __read_32bit_c0_register($22, 0) 991#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) 992 993#define read_c0_diag1() __read_32bit_c0_register($22, 1) 994#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) 995 996#define read_c0_diag2() __read_32bit_c0_register($22, 2) 997#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) 998 999#define read_c0_diag3() __read_32bit_c0_register($22, 3) 1000#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) 1001 1002#define read_c0_diag4() __read_32bit_c0_register($22, 4) 1003#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) 1004 1005#define read_c0_diag5() __read_32bit_c0_register($22, 5) 1006#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) 1007 1008#define read_c0_debug() __read_32bit_c0_register($23, 0) 1009#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) 1010 1011#define read_c0_depc() __read_ulong_c0_register($24, 0) 1012#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) 1013 1014/* 1015 * MIPS32 / MIPS64 performance counters 1016 */ 1017#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) 1018#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) 1019#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) 1020#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) 1021#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) 1022#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) 1023#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) 1024#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) 1025#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) 1026#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) 1027#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) 1028#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) 1029#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) 1030#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) 1031#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) 1032#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) 1033 1034/* RM9000 PerfCount performance counter register */ 1035#define read_c0_perfcount() __read_64bit_c0_register($25, 0) 1036#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val) 1037 1038#define read_c0_ecc() __read_32bit_c0_register($26, 0) 1039#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) 1040 1041#define read_c0_derraddr0() __read_ulong_c0_register($26, 1) 1042#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) 1043 1044#define read_c0_cacheerr() __read_32bit_c0_register($27, 0) 1045 1046#define read_c0_derraddr1() __read_ulong_c0_register($27, 1) 1047#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) 1048 1049#define read_c0_taglo() __read_32bit_c0_register($28, 0) 1050#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) 1051 1052#define read_c0_dtaglo() __read_32bit_c0_register($28, 2) 1053#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) 1054 1055#define read_c0_taghi() __read_32bit_c0_register($29, 0) 1056#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) 1057 1058#define read_c0_errorepc() __read_ulong_c0_register($30, 0) 1059#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) 1060 1061/* MIPSR2 */ 1062#define read_c0_hwrena() __read_32bit_c0_register($7, 0) 1063#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) 1064 1065#define read_c0_intctl() __read_32bit_c0_register($12, 1) 1066#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) 1067 1068#define read_c0_srsctl() __read_32bit_c0_register($12, 2) 1069#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) 1070 1071#define read_c0_srsmap() __read_32bit_c0_register($12, 3) 1072#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) 1073 1074#define read_c0_srsmap2() __read_32bit_c0_register($12, 5) 1075#define write_c0_srsmap2(val) __write_32bit_c0_register($12, 5, val) 1076 1077#define read_c0_ebase() __read_32bit_c0_register($15, 1) 1078#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1079 1080 1081/* Cavium OCTEON (cnMIPS) */ 1082#define read_c0_cvmcount() __read_ulong_c0_register($9, 6) 1083#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) 1084 1085#define read_c0_cvmctl() __read_64bit_c0_register($9, 7) 1086#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) 1087 1088#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) 1089#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) 1090/* 1091 * The cacheerr registers are not standardized. On OCTEON, they are 1092 * 64 bits wide. 1093 */ 1094#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) 1095#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) 1096 1097#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) 1098#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) 1099 1100/* 1101 * Macros to access the floating point coprocessor control registers 1102 */ 1103#define read_32bit_cp1_register(source) \ 1104({ \ 1105 int __res; \ 1106 \ 1107 __asm__ __volatile__( \ 1108 " .set push \n" \ 1109 " .set reorder \n" \ 1110 " # gas fails to assemble cfc1 for some archs, \n" \ 1111 " # like Octeon. \n" \ 1112 " .set mips1 \n" \ 1113 " cfc1 %0,"STR(source)" \n" \ 1114 " .set pop \n" \ 1115 : "=r" (__res)); \ 1116 __res; \ 1117}) 1118 1119/* 1120 * Macros to access the DSP ASE registers 1121 */ 1122 1123#ifdef CONFIG_CPU_MICROMIPS 1124#define rddsp(mask) \ 1125({ \ 1126 unsigned int __res; \ 1127 \ 1128 __asm__ __volatile__( \ 1129 " .set push \n" \ 1130 " .set noat \n" \ 1131 " # rddsp $1, %x1 \n" \ 1132 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ 1133 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ 1134 " move %0, $1 \n" \ 1135 " .set pop \n" \ 1136 : "=r" (__res) \ 1137 : "i" (mask)); \ 1138 __res; \ 1139}) 1140 1141#define wrdsp(val, mask) \ 1142do { \ 1143 __asm__ __volatile__( \ 1144 " .set push \n" \ 1145 " .set noat \n" \ 1146 " move $1, %0 \n" \ 1147 " # wrdsp $1, %x1 \n" \ 1148 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ 1149 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ 1150 " .set pop \n" \ 1151 : \ 1152 : "r" (val), "i" (mask)); \ 1153} while (0) 1154 1155#define _umips_dsp_mfxxx(ins) \ 1156({ \ 1157 unsigned long __treg; \ 1158 \ 1159 __asm__ __volatile__( \ 1160 " .set push \n" \ 1161 " .set noat \n" \ 1162 " .hword 0x0001 \n" \ 1163 " .hword %x1 \n" \ 1164 " move %0, $1 \n" \ 1165 " .set pop \n" \ 1166 : "=r" (__treg) \ 1167 : "i" (ins)); \ 1168 __treg; \ 1169}) 1170 1171#define _umips_dsp_mtxxx(val, ins) \ 1172do { \ 1173 __asm__ __volatile__( \ 1174 " .set push \n" \ 1175 " .set noat \n" \ 1176 " move $1, %0 \n" \ 1177 " .hword 0x0001 \n" \ 1178 " .hword %x1 \n" \ 1179 " .set pop \n" \ 1180 : \ 1181 : "r" (val), "i" (ins)); \ 1182} while (0) 1183 1184#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c) 1185#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c) 1186 1187#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c)) 1188#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c)) 1189 1190#define mflo0() _umips_dsp_mflo(0) 1191#define mflo1() _umips_dsp_mflo(1) 1192#define mflo2() _umips_dsp_mflo(2) 1193#define mflo3() _umips_dsp_mflo(3) 1194 1195#define mfhi0() _umips_dsp_mfhi(0) 1196#define mfhi1() _umips_dsp_mfhi(1) 1197#define mfhi2() _umips_dsp_mfhi(2) 1198#define mfhi3() _umips_dsp_mfhi(3) 1199 1200#define mtlo0(x) _umips_dsp_mtlo(x, 0) 1201#define mtlo1(x) _umips_dsp_mtlo(x, 1) 1202#define mtlo2(x) _umips_dsp_mtlo(x, 2) 1203#define mtlo3(x) _umips_dsp_mtlo(x, 3) 1204 1205#define mthi0(x) _umips_dsp_mthi(x, 0) 1206#define mthi1(x) _umips_dsp_mthi(x, 1) 1207#define mthi2(x) _umips_dsp_mthi(x, 2) 1208#define mthi3(x) _umips_dsp_mthi(x, 3) 1209 1210#else /* !CONFIG_CPU_MICROMIPS */ 1211 1212#define rddsp(mask) \ 1213({ \ 1214 unsigned int __res; \ 1215 \ 1216 __asm__ __volatile__( \ 1217 " .set push \n" \ 1218 " .set noat \n" \ 1219 " # rddsp $1, %x1 \n" \ 1220 " .word 0x7c000cb8 | (%x1 << 16) \n" \ 1221 " move %0, $1 \n" \ 1222 " .set pop \n" \ 1223 : "=r" (__res) \ 1224 : "i" (mask)); \ 1225 __res; \ 1226}) 1227 1228#define wrdsp(val, mask) \ 1229do { \ 1230 __asm__ __volatile__( \ 1231 " .set push \n" \ 1232 " .set noat \n" \ 1233 " move $1, %0 \n" \ 1234 " # wrdsp $1, %x1 \n" \ 1235 " .word 0x7c2004f8 | (%x1 << 11) \n" \ 1236 " .set pop \n" \ 1237 : \ 1238 : "r" (val), "i" (mask)); \ 1239} while (0) 1240 1241#define _dsp_mfxxx(ins) \ 1242({ \ 1243 unsigned long __treg; \ 1244 \ 1245 __asm__ __volatile__( \ 1246 " .set push \n" \ 1247 " .set noat \n" \ 1248 " .word (0x00000810 | %1) \n" \ 1249 " move %0, $1 \n" \ 1250 " .set pop \n" \ 1251 : "=r" (__treg) \ 1252 : "i" (ins)); \ 1253 __treg; \ 1254}) 1255 1256#define _dsp_mtxxx(val, ins) \ 1257do { \ 1258 __asm__ __volatile__( \ 1259 " .set push \n" \ 1260 " .set noat \n" \ 1261 " move $1, %0 \n" \ 1262 " .word (0x00200011 | %1) \n" \ 1263 " .set pop \n" \ 1264 : \ 1265 : "r" (val), "i" (ins)); \ 1266} while (0) 1267 1268#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) 1269#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) 1270 1271#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) 1272#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) 1273 1274#define mflo0() _dsp_mflo(0) 1275#define mflo1() _dsp_mflo(1) 1276#define mflo2() _dsp_mflo(2) 1277#define mflo3() _dsp_mflo(3) 1278 1279#define mfhi0() _dsp_mfhi(0) 1280#define mfhi1() _dsp_mfhi(1) 1281#define mfhi2() _dsp_mfhi(2) 1282#define mfhi3() _dsp_mfhi(3) 1283 1284#define mtlo0(x) _dsp_mtlo(x, 0) 1285#define mtlo1(x) _dsp_mtlo(x, 1) 1286#define mtlo2(x) _dsp_mtlo(x, 2) 1287#define mtlo3(x) _dsp_mtlo(x, 3) 1288 1289#define mthi0(x) _dsp_mthi(x, 0) 1290#define mthi1(x) _dsp_mthi(x, 1) 1291#define mthi2(x) _dsp_mthi(x, 2) 1292#define mthi3(x) _dsp_mthi(x, 3) 1293 1294#endif /* CONFIG_CPU_MICROMIPS */ 1295 1296/* 1297 * TLB operations. 1298 * 1299 * It is responsibility of the caller to take care of any TLB hazards. 1300 */ 1301static inline void tlb_probe(void) 1302{ 1303 __asm__ __volatile__( 1304 ".set noreorder\n\t" 1305 "tlbp\n\t" 1306 ".set reorder"); 1307} 1308 1309static inline void tlb_read(void) 1310{ 1311#if MIPS34K_MISSED_ITLB_WAR 1312 int res = 0; 1313 1314 __asm__ __volatile__( 1315 " .set push \n" 1316 " .set noreorder \n" 1317 " .set noat \n" 1318 " .set mips32r2 \n" 1319 " .word 0x41610001 # dvpe $1 \n" 1320 " move %0, $1 \n" 1321 " ehb \n" 1322 " .set pop \n" 1323 : "=r" (res)); 1324 1325 instruction_hazard(); 1326#endif 1327 1328 __asm__ __volatile__( 1329 ".set noreorder\n\t" 1330 "tlbr\n\t" 1331 ".set reorder"); 1332 1333#if MIPS34K_MISSED_ITLB_WAR 1334 if ((res & _ULCAST_(1))) 1335 __asm__ __volatile__( 1336 " .set push \n" 1337 " .set noreorder \n" 1338 " .set noat \n" 1339 " .set mips32r2 \n" 1340 " .word 0x41600021 # evpe \n" 1341 " ehb \n" 1342 " .set pop \n"); 1343#endif 1344} 1345 1346static inline void tlb_write_indexed(void) 1347{ 1348 __asm__ __volatile__( 1349 ".set noreorder\n\t" 1350 "tlbwi\n\t" 1351 ".set reorder"); 1352} 1353 1354static inline void tlb_write_random(void) 1355{ 1356 __asm__ __volatile__( 1357 ".set noreorder\n\t" 1358 "tlbwr\n\t" 1359 ".set reorder"); 1360} 1361 1362/* 1363 * Manipulate bits in a c0 register. 1364 */ 1365#ifndef CONFIG_MIPS_MT_SMTC 1366/* 1367 * SMTC Linux requires shutting-down microthread scheduling 1368 * during CP0 register read-modify-write sequences. 1369 */ 1370#define __BUILD_SET_C0(name) \ 1371static inline unsigned int \ 1372set_c0_##name(unsigned int set) \ 1373{ \ 1374 unsigned int res, new; \ 1375 \ 1376 res = read_c0_##name(); \ 1377 new = res | set; \ 1378 write_c0_##name(new); \ 1379 \ 1380 return res; \ 1381} \ 1382 \ 1383static inline unsigned int \ 1384clear_c0_##name(unsigned int clear) \ 1385{ \ 1386 unsigned int res, new; \ 1387 \ 1388 res = read_c0_##name(); \ 1389 new = res & ~clear; \ 1390 write_c0_##name(new); \ 1391 \ 1392 return res; \ 1393} \ 1394 \ 1395static inline unsigned int \ 1396change_c0_##name(unsigned int change, unsigned int val) \ 1397{ \ 1398 unsigned int res, new; \ 1399 \ 1400 res = read_c0_##name(); \ 1401 new = res & ~change; \ 1402 new |= (val & change); \ 1403 write_c0_##name(new); \ 1404 \ 1405 return res; \ 1406} 1407 1408#else /* SMTC versions that manage MT scheduling */ 1409 1410#include <linux/irqflags.h> 1411 1412/* 1413 * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with 1414 * header file recursion. 1415 */ 1416static inline unsigned int __dmt(void) 1417{ 1418 int res; 1419 1420 __asm__ __volatile__( 1421 " .set push \n" 1422 " .set mips32r2 \n" 1423 " .set noat \n" 1424 " .word 0x41610BC1 # dmt $1 \n" 1425 " ehb \n" 1426 " move %0, $1 \n" 1427 " .set pop \n" 1428 : "=r" (res)); 1429 1430 instruction_hazard(); 1431 1432 return res; 1433} 1434 1435#define __VPECONTROL_TE_SHIFT 15 1436#define __VPECONTROL_TE (1UL << __VPECONTROL_TE_SHIFT) 1437 1438#define __EMT_ENABLE __VPECONTROL_TE 1439 1440static inline void __emt(unsigned int previous) 1441{ 1442 if ((previous & __EMT_ENABLE)) 1443 __asm__ __volatile__( 1444 " .set mips32r2 \n" 1445 " .word 0x41600be1 # emt \n" 1446 " ehb \n" 1447 " .set mips0 \n"); 1448} 1449 1450static inline void __ehb(void) 1451{ 1452 __asm__ __volatile__( 1453 " .set mips32r2 \n" 1454 " ehb \n" " .set mips0 \n"); 1455} 1456 1457/* 1458 * Note that local_irq_save/restore affect TC-specific IXMT state, 1459 * not Status.IE as in non-SMTC kernel. 1460 */ 1461 1462#define __BUILD_SET_C0(name) \ 1463static inline unsigned int \ 1464set_c0_##name(unsigned int set) \ 1465{ \ 1466 unsigned int res; \ 1467 unsigned int new; \ 1468 unsigned int omt; \ 1469 unsigned long flags; \ 1470 \ 1471 local_irq_save(flags); \ 1472 omt = __dmt(); \ 1473 res = read_c0_##name(); \ 1474 new = res | set; \ 1475 write_c0_##name(new); \ 1476 __emt(omt); \ 1477 local_irq_restore(flags); \ 1478 \ 1479 return res; \ 1480} \ 1481 \ 1482static inline unsigned int \ 1483clear_c0_##name(unsigned int clear) \ 1484{ \ 1485 unsigned int res; \ 1486 unsigned int new; \ 1487 unsigned int omt; \ 1488 unsigned long flags; \ 1489 \ 1490 local_irq_save(flags); \ 1491 omt = __dmt(); \ 1492 res = read_c0_##name(); \ 1493 new = res & ~clear; \ 1494 write_c0_##name(new); \ 1495 __emt(omt); \ 1496 local_irq_restore(flags); \ 1497 \ 1498 return res; \ 1499} \ 1500 \ 1501static inline unsigned int \ 1502change_c0_##name(unsigned int change, unsigned int newbits) \ 1503{ \ 1504 unsigned int res; \ 1505 unsigned int new; \ 1506 unsigned int omt; \ 1507 unsigned long flags; \ 1508 \ 1509 local_irq_save(flags); \ 1510 \ 1511 omt = __dmt(); \ 1512 res = read_c0_##name(); \ 1513 new = res & ~change; \ 1514 new |= (newbits & change); \ 1515 write_c0_##name(new); \ 1516 __emt(omt); \ 1517 local_irq_restore(flags); \ 1518 \ 1519 return res; \ 1520} 1521#endif 1522 1523__BUILD_SET_C0(status) 1524__BUILD_SET_C0(cause) 1525__BUILD_SET_C0(config) 1526__BUILD_SET_C0(intcontrol) 1527__BUILD_SET_C0(srsctl) 1528__BUILD_SET_C0(intctl) 1529__BUILD_SET_C0(srsmap) 1530__BUILD_SET_C0(srsmap2) 1531 1532#endif /* !__ASSEMBLY__ */ 1533 1534#endif /* _ASM_MIPSREGS_H */ 1535