1#ifndef BCM63XX_CPU_H_ 2#define BCM63XX_CPU_H_ 3 4#include <linux/types.h> 5#include <linux/init.h> 6 7/* 8 * Macro to fetch bcm63xx cpu id and revision, should be optimized at 9 * compile time if only one CPU support is enabled (idea stolen from 10 * arm mach-types) 11 */ 12#define BCM6338_CPU_ID 0x6338 13#define BCM6345_CPU_ID 0x6345 14#define BCM6348_CPU_ID 0x6348 15#define BCM6358_CPU_ID 0x6358 16 17void __init bcm63xx_cpu_init(void); 18u16 __bcm63xx_get_cpu_id(void); 19u16 bcm63xx_get_cpu_rev(void); 20unsigned int bcm63xx_get_cpu_freq(void); 21 22#ifdef CONFIG_BCM63XX_CPU_6338 23# ifdef bcm63xx_get_cpu_id 24# undef bcm63xx_get_cpu_id 25# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 26# define BCMCPU_RUNTIME_DETECT 27# else 28# define bcm63xx_get_cpu_id() BCM6338_CPU_ID 29# endif 30# define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID) 31#else 32# define BCMCPU_IS_6338() (0) 33#endif 34 35#ifdef CONFIG_BCM63XX_CPU_6345 36# ifdef bcm63xx_get_cpu_id 37# undef bcm63xx_get_cpu_id 38# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 39# define BCMCPU_RUNTIME_DETECT 40# else 41# define bcm63xx_get_cpu_id() BCM6345_CPU_ID 42# endif 43# define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID) 44#else 45# define BCMCPU_IS_6345() (0) 46#endif 47 48#ifdef CONFIG_BCM63XX_CPU_6348 49# ifdef bcm63xx_get_cpu_id 50# undef bcm63xx_get_cpu_id 51# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 52# define BCMCPU_RUNTIME_DETECT 53# else 54# define bcm63xx_get_cpu_id() BCM6348_CPU_ID 55# endif 56# define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID) 57#else 58# define BCMCPU_IS_6348() (0) 59#endif 60 61#ifdef CONFIG_BCM63XX_CPU_6358 62# ifdef bcm63xx_get_cpu_id 63# undef bcm63xx_get_cpu_id 64# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 65# define BCMCPU_RUNTIME_DETECT 66# else 67# define bcm63xx_get_cpu_id() BCM6358_CPU_ID 68# endif 69# define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID) 70#else 71# define BCMCPU_IS_6358() (0) 72#endif 73 74#ifndef bcm63xx_get_cpu_id 75#error "No CPU support configured" 76#endif 77 78/* 79 * While registers sets are (mostly) the same across 63xx CPU, base 80 * address of these sets do change. 81 */ 82enum bcm63xx_regs_set { 83 RSET_DSL_LMEM = 0, 84 RSET_PERF, 85 RSET_TIMER, 86 RSET_WDT, 87 RSET_UART0, 88 RSET_UART1, 89 RSET_GPIO, 90 RSET_SPI, 91 RSET_UDC0, 92 RSET_OHCI0, 93 RSET_OHCI_PRIV, 94 RSET_USBH_PRIV, 95 RSET_MPI, 96 RSET_PCMCIA, 97 RSET_DSL, 98 RSET_ENET0, 99 RSET_ENET1, 100 RSET_ENETDMA, 101 RSET_EHCI0, 102 RSET_SDRAM, 103 RSET_MEMC, 104 RSET_DDR, 105}; 106 107#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) 108#define RSET_DSL_SIZE 4096 109#define RSET_WDT_SIZE 12 110#define RSET_ENET_SIZE 2048 111#define RSET_ENETDMA_SIZE 2048 112#define RSET_UART_SIZE 24 113#define RSET_UDC_SIZE 256 114#define RSET_OHCI_SIZE 256 115#define RSET_EHCI_SIZE 256 116#define RSET_PCMCIA_SIZE 12 117 118/* 119 * 6338 register sets base address 120 */ 121#define BCM_6338_DSL_LMEM_BASE (0xfff00000) 122#define BCM_6338_PERF_BASE (0xfffe0000) 123#define BCM_6338_BB_BASE (0xfffe0100) 124#define BCM_6338_TIMER_BASE (0xfffe0200) 125#define BCM_6338_WDT_BASE (0xfffe021c) 126#define BCM_6338_UART0_BASE (0xfffe0300) 127#define BCM_6338_UART1_BASE (0xdeadbeef) 128#define BCM_6338_GPIO_BASE (0xfffe0400) 129#define BCM_6338_SPI_BASE (0xfffe0c00) 130#define BCM_6338_UDC0_BASE (0xdeadbeef) 131#define BCM_6338_USBDMA_BASE (0xfffe2400) 132#define BCM_6338_OHCI0_BASE (0xdeadbeef) 133#define BCM_6338_OHCI_PRIV_BASE (0xfffe3000) 134#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) 135#define BCM_6338_MPI_BASE (0xfffe3160) 136#define BCM_6338_PCMCIA_BASE (0xdeadbeef) 137#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) 138#define BCM_6338_DSL_BASE (0xfffe1000) 139#define BCM_6338_SAR_BASE (0xfffe2000) 140#define BCM_6338_UBUS_BASE (0xdeadbeef) 141#define BCM_6338_ENET0_BASE (0xfffe2800) 142#define BCM_6338_ENET1_BASE (0xdeadbeef) 143#define BCM_6338_ENETDMA_BASE (0xfffe2400) 144#define BCM_6338_EHCI0_BASE (0xdeadbeef) 145#define BCM_6338_SDRAM_BASE (0xfffe3100) 146#define BCM_6338_MEMC_BASE (0xdeadbeef) 147#define BCM_6338_DDR_BASE (0xdeadbeef) 148 149/* 150 * 6345 register sets base address 151 */ 152#define BCM_6345_DSL_LMEM_BASE (0xfff00000) 153#define BCM_6345_PERF_BASE (0xfffe0000) 154#define BCM_6345_BB_BASE (0xfffe0100) 155#define BCM_6345_TIMER_BASE (0xfffe0200) 156#define BCM_6345_WDT_BASE (0xfffe021c) 157#define BCM_6345_UART0_BASE (0xfffe0300) 158#define BCM_6345_UART1_BASE (0xdeadbeef) 159#define BCM_6345_GPIO_BASE (0xfffe0400) 160#define BCM_6345_SPI_BASE (0xdeadbeef) 161#define BCM_6345_UDC0_BASE (0xdeadbeef) 162#define BCM_6345_USBDMA_BASE (0xfffe2800) 163#define BCM_6345_ENET0_BASE (0xfffe1800) 164#define BCM_6345_ENETDMA_BASE (0xfffe2800) 165#define BCM_6345_PCMCIA_BASE (0xfffe2028) 166#define BCM_6345_MPI_BASE (0xdeadbeef) 167#define BCM_6345_OHCI0_BASE (0xfffe2100) 168#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) 169#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) 170#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) 171#define BCM_6345_DSL_BASE (0xdeadbeef) 172#define BCM_6345_SAR_BASE (0xdeadbeef) 173#define BCM_6345_UBUS_BASE (0xdeadbeef) 174#define BCM_6345_ENET1_BASE (0xdeadbeef) 175#define BCM_6345_EHCI0_BASE (0xdeadbeef) 176#define BCM_6345_SDRAM_BASE (0xfffe2300) 177#define BCM_6345_MEMC_BASE (0xdeadbeef) 178#define BCM_6345_DDR_BASE (0xdeadbeef) 179 180/* 181 * 6348 register sets base address 182 */ 183#define BCM_6348_DSL_LMEM_BASE (0xfff00000) 184#define BCM_6348_PERF_BASE (0xfffe0000) 185#define BCM_6348_TIMER_BASE (0xfffe0200) 186#define BCM_6348_WDT_BASE (0xfffe021c) 187#define BCM_6348_UART0_BASE (0xfffe0300) 188#define BCM_6348_UART1_BASE (0xdeadbeef) 189#define BCM_6348_GPIO_BASE (0xfffe0400) 190#define BCM_6348_SPI_BASE (0xfffe0c00) 191#define BCM_6348_UDC0_BASE (0xfffe1000) 192#define BCM_6348_OHCI0_BASE (0xfffe1b00) 193#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) 194#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef) 195#define BCM_6348_MPI_BASE (0xfffe2000) 196#define BCM_6348_PCMCIA_BASE (0xfffe2054) 197#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300) 198#define BCM_6348_DSL_BASE (0xfffe3000) 199#define BCM_6348_ENET0_BASE (0xfffe6000) 200#define BCM_6348_ENET1_BASE (0xfffe6800) 201#define BCM_6348_ENETDMA_BASE (0xfffe7000) 202#define BCM_6348_EHCI0_BASE (0xdeadbeef) 203#define BCM_6348_SDRAM_BASE (0xfffe2300) 204#define BCM_6348_MEMC_BASE (0xdeadbeef) 205#define BCM_6348_DDR_BASE (0xdeadbeef) 206 207/* 208 * 6358 register sets base address 209 */ 210#define BCM_6358_DSL_LMEM_BASE (0xfff00000) 211#define BCM_6358_PERF_BASE (0xfffe0000) 212#define BCM_6358_TIMER_BASE (0xfffe0040) 213#define BCM_6358_WDT_BASE (0xfffe005c) 214#define BCM_6358_UART0_BASE (0xfffe0100) 215#define BCM_6358_UART1_BASE (0xfffe0120) 216#define BCM_6358_GPIO_BASE (0xfffe0080) 217#define BCM_6358_SPI_BASE (0xdeadbeef) 218#define BCM_6358_UDC0_BASE (0xfffe0800) 219#define BCM_6358_OHCI0_BASE (0xfffe1400) 220#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) 221#define BCM_6358_USBH_PRIV_BASE (0xfffe1500) 222#define BCM_6358_MPI_BASE (0xfffe1000) 223#define BCM_6358_PCMCIA_BASE (0xfffe1054) 224#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300) 225#define BCM_6358_DSL_BASE (0xfffe3000) 226#define BCM_6358_ENET0_BASE (0xfffe4000) 227#define BCM_6358_ENET1_BASE (0xfffe4800) 228#define BCM_6358_ENETDMA_BASE (0xfffe5000) 229#define BCM_6358_EHCI0_BASE (0xfffe1300) 230#define BCM_6358_SDRAM_BASE (0xdeadbeef) 231#define BCM_6358_MEMC_BASE (0xfffe1200) 232#define BCM_6358_DDR_BASE (0xfffe12a0) 233 234 235extern const unsigned long *bcm63xx_regs_base; 236 237static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) 238{ 239#ifdef BCMCPU_RUNTIME_DETECT 240 return bcm63xx_regs_base[set]; 241#else 242#ifdef CONFIG_BCM63XX_CPU_6338 243 switch (set) { 244 case RSET_DSL_LMEM: 245 return BCM_6338_DSL_LMEM_BASE; 246 case RSET_PERF: 247 return BCM_6338_PERF_BASE; 248 case RSET_TIMER: 249 return BCM_6338_TIMER_BASE; 250 case RSET_WDT: 251 return BCM_6338_WDT_BASE; 252 case RSET_UART0: 253 return BCM_6338_UART0_BASE; 254 case RSET_UART1: 255 return BCM_6338_UART1_BASE; 256 case RSET_GPIO: 257 return BCM_6338_GPIO_BASE; 258 case RSET_SPI: 259 return BCM_6338_SPI_BASE; 260 case RSET_UDC0: 261 return BCM_6338_UDC0_BASE; 262 case RSET_OHCI0: 263 return BCM_6338_OHCI0_BASE; 264 case RSET_OHCI_PRIV: 265 return BCM_6338_OHCI_PRIV_BASE; 266 case RSET_USBH_PRIV: 267 return BCM_6338_USBH_PRIV_BASE; 268 case RSET_MPI: 269 return BCM_6338_MPI_BASE; 270 case RSET_PCMCIA: 271 return BCM_6338_PCMCIA_BASE; 272 case RSET_DSL: 273 return BCM_6338_DSL_BASE; 274 case RSET_ENET0: 275 return BCM_6338_ENET0_BASE; 276 case RSET_ENET1: 277 return BCM_6338_ENET1_BASE; 278 case RSET_ENETDMA: 279 return BCM_6338_ENETDMA_BASE; 280 case RSET_EHCI0: 281 return BCM_6338_EHCI0_BASE; 282 case RSET_SDRAM: 283 return BCM_6338_SDRAM_BASE; 284 case RSET_MEMC: 285 return BCM_6338_MEMC_BASE; 286 case RSET_DDR: 287 return BCM_6338_DDR_BASE; 288 } 289#endif 290#ifdef CONFIG_BCM63XX_CPU_6345 291 switch (set) { 292 case RSET_DSL_LMEM: 293 return BCM_6345_DSL_LMEM_BASE; 294 case RSET_PERF: 295 return BCM_6345_PERF_BASE; 296 case RSET_TIMER: 297 return BCM_6345_TIMER_BASE; 298 case RSET_WDT: 299 return BCM_6345_WDT_BASE; 300 case RSET_UART0: 301 return BCM_6345_UART0_BASE; 302 case RSET_UART1: 303 return BCM_6345_UART1_BASE; 304 case RSET_GPIO: 305 return BCM_6345_GPIO_BASE; 306 case RSET_SPI: 307 return BCM_6345_SPI_BASE; 308 case RSET_UDC0: 309 return BCM_6345_UDC0_BASE; 310 case RSET_OHCI0: 311 return BCM_6345_OHCI0_BASE; 312 case RSET_OHCI_PRIV: 313 return BCM_6345_OHCI_PRIV_BASE; 314 case RSET_USBH_PRIV: 315 return BCM_6345_USBH_PRIV_BASE; 316 case RSET_MPI: 317 return BCM_6345_MPI_BASE; 318 case RSET_PCMCIA: 319 return BCM_6345_PCMCIA_BASE; 320 case RSET_DSL: 321 return BCM_6345_DSL_BASE; 322 case RSET_ENET0: 323 return BCM_6345_ENET0_BASE; 324 case RSET_ENET1: 325 return BCM_6345_ENET1_BASE; 326 case RSET_ENETDMA: 327 return BCM_6345_ENETDMA_BASE; 328 case RSET_EHCI0: 329 return BCM_6345_EHCI0_BASE; 330 case RSET_SDRAM: 331 return BCM_6345_SDRAM_BASE; 332 case RSET_MEMC: 333 return BCM_6345_MEMC_BASE; 334 case RSET_DDR: 335 return BCM_6345_DDR_BASE; 336 } 337#endif 338#ifdef CONFIG_BCM63XX_CPU_6348 339 switch (set) { 340 case RSET_DSL_LMEM: 341 return BCM_6348_DSL_LMEM_BASE; 342 case RSET_PERF: 343 return BCM_6348_PERF_BASE; 344 case RSET_TIMER: 345 return BCM_6348_TIMER_BASE; 346 case RSET_WDT: 347 return BCM_6348_WDT_BASE; 348 case RSET_UART0: 349 return BCM_6348_UART0_BASE; 350 case RSET_UART1: 351 return BCM_6348_UART1_BASE; 352 case RSET_GPIO: 353 return BCM_6348_GPIO_BASE; 354 case RSET_SPI: 355 return BCM_6348_SPI_BASE; 356 case RSET_UDC0: 357 return BCM_6348_UDC0_BASE; 358 case RSET_OHCI0: 359 return BCM_6348_OHCI0_BASE; 360 case RSET_OHCI_PRIV: 361 return BCM_6348_OHCI_PRIV_BASE; 362 case RSET_USBH_PRIV: 363 return BCM_6348_USBH_PRIV_BASE; 364 case RSET_MPI: 365 return BCM_6348_MPI_BASE; 366 case RSET_PCMCIA: 367 return BCM_6348_PCMCIA_BASE; 368 case RSET_DSL: 369 return BCM_6348_DSL_BASE; 370 case RSET_ENET0: 371 return BCM_6348_ENET0_BASE; 372 case RSET_ENET1: 373 return BCM_6348_ENET1_BASE; 374 case RSET_ENETDMA: 375 return BCM_6348_ENETDMA_BASE; 376 case RSET_EHCI0: 377 return BCM_6348_EHCI0_BASE; 378 case RSET_SDRAM: 379 return BCM_6348_SDRAM_BASE; 380 case RSET_MEMC: 381 return BCM_6348_MEMC_BASE; 382 case RSET_DDR: 383 return BCM_6348_DDR_BASE; 384 } 385#endif 386#ifdef CONFIG_BCM63XX_CPU_6358 387 switch (set) { 388 case RSET_DSL_LMEM: 389 return BCM_6358_DSL_LMEM_BASE; 390 case RSET_PERF: 391 return BCM_6358_PERF_BASE; 392 case RSET_TIMER: 393 return BCM_6358_TIMER_BASE; 394 case RSET_WDT: 395 return BCM_6358_WDT_BASE; 396 case RSET_UART0: 397 return BCM_6358_UART0_BASE; 398 case RSET_UART1: 399 return BCM_6358_UART1_BASE; 400 case RSET_GPIO: 401 return BCM_6358_GPIO_BASE; 402 case RSET_SPI: 403 return BCM_6358_SPI_BASE; 404 case RSET_UDC0: 405 return BCM_6358_UDC0_BASE; 406 case RSET_OHCI0: 407 return BCM_6358_OHCI0_BASE; 408 case RSET_OHCI_PRIV: 409 return BCM_6358_OHCI_PRIV_BASE; 410 case RSET_USBH_PRIV: 411 return BCM_6358_USBH_PRIV_BASE; 412 case RSET_MPI: 413 return BCM_6358_MPI_BASE; 414 case RSET_PCMCIA: 415 return BCM_6358_PCMCIA_BASE; 416 case RSET_ENET0: 417 return BCM_6358_ENET0_BASE; 418 case RSET_ENET1: 419 return BCM_6358_ENET1_BASE; 420 case RSET_ENETDMA: 421 return BCM_6358_ENETDMA_BASE; 422 case RSET_DSL: 423 return BCM_6358_DSL_BASE; 424 case RSET_EHCI0: 425 return BCM_6358_EHCI0_BASE; 426 case RSET_SDRAM: 427 return BCM_6358_SDRAM_BASE; 428 case RSET_MEMC: 429 return BCM_6358_MEMC_BASE; 430 case RSET_DDR: 431 return BCM_6358_DDR_BASE; 432 } 433#endif 434#endif 435 /* unreached */ 436 return 0; 437} 438 439/* 440 * IRQ number changes across CPU too 441 */ 442enum bcm63xx_irq { 443 IRQ_TIMER = 0, 444 IRQ_UART0, 445 IRQ_UART1, 446 IRQ_DSL, 447 IRQ_ENET0, 448 IRQ_ENET1, 449 IRQ_ENET_PHY, 450 IRQ_OHCI0, 451 IRQ_EHCI0, 452 IRQ_PCMCIA0, 453 IRQ_ENET0_RXDMA, 454 IRQ_ENET0_TXDMA, 455 IRQ_ENET1_RXDMA, 456 IRQ_ENET1_TXDMA, 457 IRQ_PCI, 458 IRQ_PCMCIA, 459}; 460 461/* 462 * 6338 irqs 463 */ 464#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 465#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 466#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 467#define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4) 468#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) 469#define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6) 470#define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7) 471#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 472#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 473#define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10) 474#define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11) 475#define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12) 476#define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13) 477#define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14) 478#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 479#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 480#define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17) 481 482/* 483 * 6345 irqs 484 */ 485#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 486#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 487#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) 488#define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4) 489#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5) 490#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 491#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 492#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) 493#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) 494#define BCM_6345_EBI_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 5) 495#define BCM_6345_EBI_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 6) 496#define BCM_6345_RESERVED_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 9) 497#define BCM_6345_RESERVED_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 10) 498#define BCM_6345_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 13) 499#define BCM_6345_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 14) 500#define BCM_6345_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 15) 501#define BCM_6345_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 16) 502#define BCM_6345_USB_ISO_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 17) 503#define BCM_6345_USB_ISO_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 18) 504 505/* 506 * 6348 irqs 507 */ 508#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 509#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 510#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 511#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7) 512#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 513#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 514#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) 515#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) 516#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) 517#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) 518#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23) 519#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) 520#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24) 521 522/* 523 * 6358 irqs 524 */ 525#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 526#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 527#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 528#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 529#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) 530#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 531#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 532#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) 533#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 534#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 535#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) 536#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) 537#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29) 538#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31) 539#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) 540 541extern const int *bcm63xx_irqs; 542 543static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq) 544{ 545 return bcm63xx_irqs[irq]; 546} 547 548/* 549 * return installed memory size 550 */ 551unsigned int bcm63xx_get_memory_size(void); 552 553#endif /* !BCM63XX_CPU_H_ */ 554