1/* 2 * GPIO functions for Au1000, Au1500, Au1100, Au1550, Au1200 3 * 4 * Copyright (c) 2009 Manuel Lauss. 5 * 6 * Licensed under the terms outlined in the file COPYING. 7 */ 8 9#ifndef _ALCHEMY_GPIO_AU1000_H_ 10#define _ALCHEMY_GPIO_AU1000_H_ 11 12#include <asm/mach-au1x00/au1000.h> 13 14/* The default GPIO numberspace as documented in the Alchemy manuals. 15 * GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block. 16 */ 17#define ALCHEMY_GPIO1_BASE 0 18#define ALCHEMY_GPIO2_BASE 200 19 20#define ALCHEMY_GPIO1_NUM 32 21#define ALCHEMY_GPIO2_NUM 16 22#define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1) 23#define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1) 24 25#define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off)) 26 27 28static inline int au1000_gpio1_to_irq(int gpio) 29{ 30 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE); 31} 32 33static inline int au1000_gpio2_to_irq(int gpio) 34{ 35 return -ENXIO; 36} 37 38static inline int au1000_irq_to_gpio(int irq) 39{ 40 if ((irq >= AU1000_GPIO0_INT) && (irq <= AU1000_GPIO31_INT)) 41 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO0_INT) + 0; 42 43 return -ENXIO; 44} 45 46static inline int au1500_gpio1_to_irq(int gpio) 47{ 48 gpio -= ALCHEMY_GPIO1_BASE; 49 50 switch (gpio) { 51 case 0 ... 15: 52 case 20: 53 case 23 ... 28: return MAKE_IRQ(1, gpio); 54 } 55 56 return -ENXIO; 57} 58 59static inline int au1500_gpio2_to_irq(int gpio) 60{ 61 gpio -= ALCHEMY_GPIO2_BASE; 62 63 switch (gpio) { 64 case 0 ... 3: return MAKE_IRQ(1, 16 + gpio - 0); 65 case 4 ... 5: return MAKE_IRQ(1, 21 + gpio - 4); 66 case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6); 67 } 68 69 return -ENXIO; 70} 71 72static inline int au1500_irq_to_gpio(int irq) 73{ 74 switch (irq) { 75 case AU1500_GPIO0_INT ... AU1500_GPIO15_INT: 76 case AU1500_GPIO20_INT: 77 case AU1500_GPIO23_INT ... AU1500_GPIO28_INT: 78 return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO0_INT) + 0; 79 case AU1500_GPIO200_INT ... AU1500_GPIO203_INT: 80 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO200_INT) + 0; 81 case AU1500_GPIO204_INT ... AU1500_GPIO205_INT: 82 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO204_INT) + 4; 83 case AU1500_GPIO206_INT ... AU1500_GPIO207_INT: 84 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO206_INT) + 6; 85 case AU1500_GPIO208_215_INT: 86 return ALCHEMY_GPIO2_BASE + 8; 87 } 88 89 return -ENXIO; 90} 91 92static inline int au1100_gpio1_to_irq(int gpio) 93{ 94 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE); 95} 96 97static inline int au1100_gpio2_to_irq(int gpio) 98{ 99 gpio -= ALCHEMY_GPIO2_BASE; 100 101 if ((gpio >= 8) && (gpio <= 15)) 102 return MAKE_IRQ(0, 29); /* shared GPIO208_215 */ 103 104 return -ENXIO; 105} 106 107static inline int au1100_irq_to_gpio(int irq) 108{ 109 switch (irq) { 110 case AU1100_GPIO0_INT ... AU1100_GPIO31_INT: 111 return ALCHEMY_GPIO1_BASE + (irq - AU1100_GPIO0_INT) + 0; 112 case AU1100_GPIO208_215_INT: 113 return ALCHEMY_GPIO2_BASE + 8; 114 } 115 116 return -ENXIO; 117} 118 119static inline int au1550_gpio1_to_irq(int gpio) 120{ 121 gpio -= ALCHEMY_GPIO1_BASE; 122 123 switch (gpio) { 124 case 0 ... 15: 125 case 20 ... 28: return MAKE_IRQ(1, gpio); 126 case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16); 127 } 128 129 return -ENXIO; 130} 131 132static inline int au1550_gpio2_to_irq(int gpio) 133{ 134 gpio -= ALCHEMY_GPIO2_BASE; 135 136 switch (gpio) { 137 case 0: return MAKE_IRQ(1, 16); 138 case 1 ... 5: return MAKE_IRQ(1, 17); /* shared GPIO201_205 */ 139 case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6); 140 case 8 ... 15: return MAKE_IRQ(1, 31); /* shared GPIO208_215 */ 141 } 142 143 return -ENXIO; 144} 145 146static inline int au1550_irq_to_gpio(int irq) 147{ 148 switch (irq) { 149 case AU1550_GPIO0_INT ... AU1550_GPIO15_INT: 150 return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO0_INT) + 0; 151 case AU1550_GPIO200_INT: 152 case AU1550_GPIO201_205_INT: 153 return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO200_INT) + 0; 154 case AU1550_GPIO16_INT ... AU1550_GPIO28_INT: 155 return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO16_INT) + 16; 156 case AU1550_GPIO206_INT ... AU1550_GPIO208_215_INT: 157 return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO206_INT) + 6; 158 } 159 160 return -ENXIO; 161} 162 163static inline int au1200_gpio1_to_irq(int gpio) 164{ 165 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE); 166} 167 168static inline int au1200_gpio2_to_irq(int gpio) 169{ 170 gpio -= ALCHEMY_GPIO2_BASE; 171 172 switch (gpio) { 173 case 0 ... 2: return MAKE_IRQ(0, 5 + gpio - 0); 174 case 3: return MAKE_IRQ(0, 22); 175 case 4 ... 7: return MAKE_IRQ(0, 24 + gpio - 4); 176 case 8 ... 15: return MAKE_IRQ(0, 28); /* shared GPIO208_215 */ 177 } 178 179 return -ENXIO; 180} 181 182static inline int au1200_irq_to_gpio(int irq) 183{ 184 switch (irq) { 185 case AU1200_GPIO0_INT ... AU1200_GPIO31_INT: 186 return ALCHEMY_GPIO1_BASE + (irq - AU1200_GPIO0_INT) + 0; 187 case AU1200_GPIO200_INT ... AU1200_GPIO202_INT: 188 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO200_INT) + 0; 189 case AU1200_GPIO203_INT: 190 return ALCHEMY_GPIO2_BASE + 3; 191 case AU1200_GPIO204_INT ... AU1200_GPIO208_215_INT: 192 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO204_INT) + 4; 193 } 194 195 return -ENXIO; 196} 197 198/* 199 * GPIO1 block macros for common linux gpio functions. 200 */ 201static inline void alchemy_gpio1_set_value(int gpio, int v) 202{ 203 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); 204 unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR; 205 au_writel(mask, r); 206 au_sync(); 207} 208 209static inline int alchemy_gpio1_get_value(int gpio) 210{ 211 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); 212 return au_readl(SYS_PINSTATERD) & mask; 213} 214 215static inline int alchemy_gpio1_direction_input(int gpio) 216{ 217 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); 218 au_writel(mask, SYS_TRIOUTCLR); 219 au_sync(); 220 return 0; 221} 222 223static inline int alchemy_gpio1_direction_output(int gpio, int v) 224{ 225 /* hardware switches to "output" mode when one of the two 226 * "set_value" registers is accessed. 227 */ 228 alchemy_gpio1_set_value(gpio, v); 229 return 0; 230} 231 232static inline int alchemy_gpio1_is_valid(int gpio) 233{ 234 return ((gpio >= ALCHEMY_GPIO1_BASE) && (gpio <= ALCHEMY_GPIO1_MAX)); 235} 236 237static inline int alchemy_gpio1_to_irq(int gpio) 238{ 239 switch (alchemy_get_cputype()) { 240 case ALCHEMY_CPU_AU1000: 241 return au1000_gpio1_to_irq(gpio); 242 case ALCHEMY_CPU_AU1100: 243 return au1100_gpio1_to_irq(gpio); 244 case ALCHEMY_CPU_AU1500: 245 return au1500_gpio1_to_irq(gpio); 246 case ALCHEMY_CPU_AU1550: 247 return au1550_gpio1_to_irq(gpio); 248 case ALCHEMY_CPU_AU1200: 249 return au1200_gpio1_to_irq(gpio); 250 } 251 return -ENXIO; 252} 253 254/* 255 * GPIO2 block macros for common linux GPIO functions. The 'gpio' 256 * parameter must be in range of ALCHEMY_GPIO2_BASE..ALCHEMY_GPIO2_MAX. 257 */ 258static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out) 259{ 260 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE); 261 unsigned long d = au_readl(GPIO2_DIR); 262 if (to_out) 263 d |= mask; 264 else 265 d &= ~mask; 266 au_writel(d, GPIO2_DIR); 267 au_sync(); 268} 269 270static inline void alchemy_gpio2_set_value(int gpio, int v) 271{ 272 unsigned long mask; 273 mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE); 274 au_writel(mask, GPIO2_OUTPUT); 275 au_sync(); 276} 277 278static inline int alchemy_gpio2_get_value(int gpio) 279{ 280 return au_readl(GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE)); 281} 282 283static inline int alchemy_gpio2_direction_input(int gpio) 284{ 285 unsigned long flags; 286 local_irq_save(flags); 287 __alchemy_gpio2_mod_dir(gpio, 0); 288 local_irq_restore(flags); 289 return 0; 290} 291 292static inline int alchemy_gpio2_direction_output(int gpio, int v) 293{ 294 unsigned long flags; 295 alchemy_gpio2_set_value(gpio, v); 296 local_irq_save(flags); 297 __alchemy_gpio2_mod_dir(gpio, 1); 298 local_irq_restore(flags); 299 return 0; 300} 301 302static inline int alchemy_gpio2_is_valid(int gpio) 303{ 304 return ((gpio >= ALCHEMY_GPIO2_BASE) && (gpio <= ALCHEMY_GPIO2_MAX)); 305} 306 307static inline int alchemy_gpio2_to_irq(int gpio) 308{ 309 switch (alchemy_get_cputype()) { 310 case ALCHEMY_CPU_AU1000: 311 return au1000_gpio2_to_irq(gpio); 312 case ALCHEMY_CPU_AU1100: 313 return au1100_gpio2_to_irq(gpio); 314 case ALCHEMY_CPU_AU1500: 315 return au1500_gpio2_to_irq(gpio); 316 case ALCHEMY_CPU_AU1550: 317 return au1550_gpio2_to_irq(gpio); 318 case ALCHEMY_CPU_AU1200: 319 return au1200_gpio2_to_irq(gpio); 320 } 321 return -ENXIO; 322} 323 324/**********************************************************************/ 325 326/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before 327 * SYS_PININPUTEN is written to at least once. On Au1550/Au1200 this 328 * register enables use of GPIOs as wake source. 329 */ 330static inline void alchemy_gpio1_input_enable(void) 331{ 332 au_writel(0, SYS_PININPUTEN); /* the write op is key */ 333 au_sync(); 334} 335 336/* GPIO2 shared interrupts and control */ 337 338static inline void __alchemy_gpio2_mod_int(int gpio2, int en) 339{ 340 unsigned long r = au_readl(GPIO2_INTENABLE); 341 if (en) 342 r |= 1 << gpio2; 343 else 344 r &= ~(1 << gpio2); 345 au_writel(r, GPIO2_INTENABLE); 346 au_sync(); 347} 348 349/** 350 * alchemy_gpio2_enable_int - Enable a GPIO2 pins' shared irq contribution. 351 * @gpio2: The GPIO2 pin to activate (200...215). 352 * 353 * GPIO208-215 have one shared interrupt line to the INTC. They are 354 * and'ed with a per-pin enable bit and finally or'ed together to form 355 * a single irq request (useful for active-high sources). 356 * With this function, a pins' individual contribution to the int request 357 * can be enabled. As with all other GPIO-based interrupts, the INTC 358 * must be programmed to accept the GPIO208_215 interrupt as well. 359 * 360 * NOTE: Calling this macro is only necessary for GPIO208-215; all other 361 * GPIO2-based interrupts have their own request to the INTC. Please 362 * consult your Alchemy databook for more information! 363 * 364 * NOTE: On the Au1550, GPIOs 201-205 also have a shared interrupt request 365 * line to the INTC, GPIO201_205. This function can be used for those 366 * as well. 367 * 368 * NOTE: 'gpio2' parameter must be in range of the GPIO2 numberspace 369 * (200-215 by default). No sanity checks are made, 370 */ 371static inline void alchemy_gpio2_enable_int(int gpio2) 372{ 373 unsigned long flags; 374 375 gpio2 -= ALCHEMY_GPIO2_BASE; 376 377 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */ 378 switch (alchemy_get_cputype()) { 379 case ALCHEMY_CPU_AU1100: 380 case ALCHEMY_CPU_AU1500: 381 gpio2 -= 8; 382 } 383 384 local_irq_save(flags); 385 __alchemy_gpio2_mod_int(gpio2, 1); 386 local_irq_restore(flags); 387} 388 389/** 390 * alchemy_gpio2_disable_int - Disable a GPIO2 pins' shared irq contribution. 391 * @gpio2: The GPIO2 pin to activate (200...215). 392 * 393 * see function alchemy_gpio2_enable_int() for more information. 394 */ 395static inline void alchemy_gpio2_disable_int(int gpio2) 396{ 397 unsigned long flags; 398 399 gpio2 -= ALCHEMY_GPIO2_BASE; 400 401 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */ 402 switch (alchemy_get_cputype()) { 403 case ALCHEMY_CPU_AU1100: 404 case ALCHEMY_CPU_AU1500: 405 gpio2 -= 8; 406 } 407 408 local_irq_save(flags); 409 __alchemy_gpio2_mod_int(gpio2, 0); 410 local_irq_restore(flags); 411} 412 413/** 414 * alchemy_gpio2_enable - Activate GPIO2 block. 415 * 416 * The GPIO2 block must be enabled excplicitly to work. On systems 417 * where this isn't done by the bootloader, this macro can be used. 418 */ 419static inline void alchemy_gpio2_enable(void) 420{ 421 au_writel(3, GPIO2_ENABLE); /* reset, clock enabled */ 422 au_sync(); 423 au_writel(1, GPIO2_ENABLE); /* clock enabled */ 424 au_sync(); 425} 426 427/** 428 * alchemy_gpio2_disable - disable GPIO2 block. 429 * 430 * Disable and put GPIO2 block in low-power mode. 431 */ 432static inline void alchemy_gpio2_disable(void) 433{ 434 au_writel(2, GPIO2_ENABLE); /* reset, clock disabled */ 435 au_sync(); 436} 437 438/**********************************************************************/ 439 440/* wrappers for on-chip gpios; can be used before gpio chips have been 441 * registered with gpiolib. 442 */ 443static inline int alchemy_gpio_direction_input(int gpio) 444{ 445 return (gpio >= ALCHEMY_GPIO2_BASE) ? 446 alchemy_gpio2_direction_input(gpio) : 447 alchemy_gpio1_direction_input(gpio); 448} 449 450static inline int alchemy_gpio_direction_output(int gpio, int v) 451{ 452 return (gpio >= ALCHEMY_GPIO2_BASE) ? 453 alchemy_gpio2_direction_output(gpio, v) : 454 alchemy_gpio1_direction_output(gpio, v); 455} 456 457static inline int alchemy_gpio_get_value(int gpio) 458{ 459 return (gpio >= ALCHEMY_GPIO2_BASE) ? 460 alchemy_gpio2_get_value(gpio) : 461 alchemy_gpio1_get_value(gpio); 462} 463 464static inline void alchemy_gpio_set_value(int gpio, int v) 465{ 466 if (gpio >= ALCHEMY_GPIO2_BASE) 467 alchemy_gpio2_set_value(gpio, v); 468 else 469 alchemy_gpio1_set_value(gpio, v); 470} 471 472static inline int alchemy_gpio_is_valid(int gpio) 473{ 474 return (gpio >= ALCHEMY_GPIO2_BASE) ? 475 alchemy_gpio2_is_valid(gpio) : 476 alchemy_gpio1_is_valid(gpio); 477} 478 479static inline int alchemy_gpio_cansleep(int gpio) 480{ 481 return 0; /* Alchemy never gets tired */ 482} 483 484static inline int alchemy_gpio_to_irq(int gpio) 485{ 486 return (gpio >= ALCHEMY_GPIO2_BASE) ? 487 alchemy_gpio2_to_irq(gpio) : 488 alchemy_gpio1_to_irq(gpio); 489} 490 491static inline int alchemy_irq_to_gpio(int irq) 492{ 493 switch (alchemy_get_cputype()) { 494 case ALCHEMY_CPU_AU1000: 495 return au1000_irq_to_gpio(irq); 496 case ALCHEMY_CPU_AU1100: 497 return au1100_irq_to_gpio(irq); 498 case ALCHEMY_CPU_AU1500: 499 return au1500_irq_to_gpio(irq); 500 case ALCHEMY_CPU_AU1550: 501 return au1550_irq_to_gpio(irq); 502 case ALCHEMY_CPU_AU1200: 503 return au1200_irq_to_gpio(irq); 504 } 505 return -ENXIO; 506} 507 508/**********************************************************************/ 509 510/* Linux gpio framework integration. 511 * 512 * 4 use cases of Au1000-Au1200 GPIOS: 513 *(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y: 514 * Board must register gpiochips. 515 *(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n: 516 * 2 (1 for Au1000) gpio_chips are registered. 517 * 518 *(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y: 519 * the boards' gpio.h must provide the linux gpio wrapper functions, 520 * 521 *(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n: 522 * inlinable gpio functions are provided which enable access to the 523 * Au1000 gpios only by using the numbers straight out of the data- 524 * sheets. 525 526 * Cases 1 and 3 are intended for boards which want to provide their own 527 * GPIO namespace and -operations (i.e. for example you have 8 GPIOs 528 * which are in part provided by spare Au1000 GPIO pins and in part by 529 * an external FPGA but you still want them to be accssible in linux 530 * as gpio0-7. The board can of course use the alchemy_gpioX_* functions 531 * as required). 532 */ 533 534#ifndef CONFIG_GPIOLIB 535 536 537#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */ 538 539static inline int gpio_direction_input(int gpio) 540{ 541 return alchemy_gpio_direction_input(gpio); 542} 543 544static inline int gpio_direction_output(int gpio, int v) 545{ 546 return alchemy_gpio_direction_output(gpio, v); 547} 548 549static inline int gpio_get_value(int gpio) 550{ 551 return alchemy_gpio_get_value(gpio); 552} 553 554static inline void gpio_set_value(int gpio, int v) 555{ 556 alchemy_gpio_set_value(gpio, v); 557} 558 559static inline int gpio_is_valid(int gpio) 560{ 561 return alchemy_gpio_is_valid(gpio); 562} 563 564static inline int gpio_cansleep(int gpio) 565{ 566 return alchemy_gpio_cansleep(gpio); 567} 568 569static inline int gpio_to_irq(int gpio) 570{ 571 return alchemy_gpio_to_irq(gpio); 572} 573 574static inline int irq_to_gpio(int irq) 575{ 576 return alchemy_irq_to_gpio(irq); 577} 578 579static inline int gpio_request(unsigned gpio, const char *label) 580{ 581 return 0; 582} 583 584static inline void gpio_free(unsigned gpio) 585{ 586} 587 588#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ 589 590 591#else /* CONFIG GPIOLIB */ 592 593 594 /* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */ 595#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */ 596 597/* get everything through gpiolib */ 598#define gpio_to_irq __gpio_to_irq 599#define gpio_get_value __gpio_get_value 600#define gpio_set_value __gpio_set_value 601#define gpio_cansleep __gpio_cansleep 602#define irq_to_gpio alchemy_irq_to_gpio 603 604#include <asm-generic/gpio.h> 605 606#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ 607 608 609#endif /* !CONFIG_GPIOLIB */ 610 611#endif /* _ALCHEMY_GPIO_AU1000_H_ */ 612