1/****************************************************************************/ 2 3/* 4 * m5272sim.h -- ColdFire 5272 System Integration Module support. 5 * 6 * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) 7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com) 8 */ 9 10/****************************************************************************/ 11#ifndef m5272sim_h 12#define m5272sim_h 13/****************************************************************************/ 14 15/* 16 * Define the 5272 SIM register set addresses. 17 */ 18#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */ 19#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/ 20#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */ 21#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */ 22#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */ 23 24#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */ 25#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */ 26#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */ 27#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */ 28 29#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */ 30#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */ 31#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */ 32#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */ 33 34#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */ 35#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */ 36#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */ 37#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */ 38 39#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */ 40#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */ 41#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */ 42#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */ 43#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */ 44#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */ 45#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */ 46#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */ 47#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */ 48#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */ 49#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */ 50#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */ 51#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */ 52#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */ 53#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */ 54#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */ 55 56#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */ 57#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */ 58#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */ 59#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */ 60#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */ 61#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */ 62#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ 63#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ 64 65#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */ 66#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */ 67#define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */ 68#define MCFSIM_PBCNT (MCF_MBAR + 0x88) /* Port B Control (r/w) */ 69#define MCFSIM_PBDDR (MCF_MBAR + 0x8c) /* Port B Direction (r/w) */ 70#define MCFSIM_PBDAT (MCF_MBAR + 0x8e) /* Port B Data (r/w) */ 71#define MCFSIM_PCDDR (MCF_MBAR + 0x94) /* Port C Direction (r/w) */ 72#define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */ 73#define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */ 74 75/* 76 * Define system peripheral IRQ usage. 77 */ 78#define MCFINT_VECBASE 64 /* Base of interrupts */ 79#define MCF_IRQ_SPURIOUS 64 /* User Spurious */ 80#define MCF_IRQ_EINT1 65 /* External Interrupt 1 */ 81#define MCF_IRQ_EINT2 66 /* External Interrupt 2 */ 82#define MCF_IRQ_EINT3 67 /* External Interrupt 3 */ 83#define MCF_IRQ_EINT4 68 /* External Interrupt 4 */ 84#define MCF_IRQ_TIMER1 69 /* Timer 1 */ 85#define MCF_IRQ_TIMER2 70 /* Timer 2 */ 86#define MCF_IRQ_TIMER3 71 /* Timer 3 */ 87#define MCF_IRQ_TIMER4 72 /* Timer 4 */ 88#define MCF_IRQ_UART1 73 /* UART 1 */ 89#define MCF_IRQ_UART2 74 /* UART 2 */ 90#define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */ 91#define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */ 92#define MCF_IRQ_USB0 77 /* USB Endpoint 0 */ 93#define MCF_IRQ_USB1 78 /* USB Endpoint 1 */ 94#define MCF_IRQ_USB2 79 /* USB Endpoint 2 */ 95#define MCF_IRQ_USB3 80 /* USB Endpoint 3 */ 96#define MCF_IRQ_USB4 81 /* USB Endpoint 4 */ 97#define MCF_IRQ_USB5 82 /* USB Endpoint 5 */ 98#define MCF_IRQ_USB6 83 /* USB Endpoint 6 */ 99#define MCF_IRQ_USB7 84 /* USB Endpoint 7 */ 100#define MCF_IRQ_DMA 85 /* DMA Controller */ 101#define MCF_IRQ_ERX 86 /* Ethernet Receiver */ 102#define MCF_IRQ_ETX 87 /* Ethernet Transmitter */ 103#define MCF_IRQ_ENTC 88 /* Ethernet Non-Time Critical */ 104#define MCF_IRQ_QSPI 89 /* Queued Serial Interface */ 105#define MCF_IRQ_EINT5 90 /* External Interrupt 5 */ 106#define MCF_IRQ_EINT6 91 /* External Interrupt 6 */ 107#define MCF_IRQ_SWTO 92 /* Software Watchdog */ 108#define MCFINT_VECMAX 95 /* Maxmum interrupt */ 109 110#define MCF_IRQ_TIMER MCF_IRQ_TIMER1 111#define MCF_IRQ_PROFILER MCF_IRQ_TIMER2 112 113/* 114 * Generic GPIO support 115 */ 116#define MCFGPIO_PIN_MAX 48 117#define MCFGPIO_IRQ_MAX -1 118#define MCFGPIO_IRQ_VECBASE -1 119/****************************************************************************/ 120#endif /* m5272sim_h */ 121