1#ifndef _ASM_IA64_HW_IRQ_H 2#define _ASM_IA64_HW_IRQ_H 3 4/* 5 * Copyright (C) 2001-2003 Hewlett-Packard Co 6 * David Mosberger-Tang <davidm@hpl.hp.com> 7 */ 8 9#include <linux/interrupt.h> 10#include <linux/sched.h> 11#include <linux/types.h> 12#include <linux/profile.h> 13 14#include <asm/machvec.h> 15#include <asm/ptrace.h> 16#include <asm/smp.h> 17 18#ifndef CONFIG_PARAVIRT 19typedef u8 ia64_vector; 20#else 21typedef u16 ia64_vector; 22#endif 23 24/* 25 * 0 special 26 * 27 * 1,3-14 are reserved from firmware 28 * 29 * 16-255 (vectored external interrupts) are available 30 * 31 * 15 spurious interrupt (see IVR) 32 * 33 * 16 lowest priority, 255 highest priority 34 * 35 * 15 classes of 16 interrupts each. 36 */ 37#define IA64_MIN_VECTORED_IRQ 16 38#define IA64_MAX_VECTORED_IRQ 255 39#define IA64_NUM_VECTORS 256 40 41#define AUTO_ASSIGN -1 42 43#define IA64_SPURIOUS_INT_VECTOR 0x0f 44 45/* 46 * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI. 47 */ 48#define IA64_CPEP_VECTOR 0x1c /* corrected platform error polling vector */ 49#define IA64_CMCP_VECTOR 0x1d /* corrected machine-check polling vector */ 50#define IA64_CPE_VECTOR 0x1e /* corrected platform error interrupt vector */ 51#define IA64_CMC_VECTOR 0x1f /* corrected machine-check interrupt vector */ 52/* 53 * Vectors 0x20-0x2f are reserved for legacy ISA IRQs. 54 * Use vectors 0x30-0xe7 as the default device vector range for ia64. 55 * Platforms may choose to reduce this range in platform_irq_setup, but the 56 * platform range must fall within 57 * [IA64_DEF_FIRST_DEVICE_VECTOR..IA64_DEF_LAST_DEVICE_VECTOR] 58 */ 59extern int ia64_first_device_vector; 60extern int ia64_last_device_vector; 61 62#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG)) 63/* Reserve the lower priority vector than device vectors for "move IRQ" IPI */ 64#define IA64_IRQ_MOVE_VECTOR 0x30 /* "move IRQ" IPI */ 65#define IA64_DEF_FIRST_DEVICE_VECTOR 0x31 66#else 67#define IA64_DEF_FIRST_DEVICE_VECTOR 0x30 68#endif 69#define IA64_DEF_LAST_DEVICE_VECTOR 0xe7 70#define IA64_FIRST_DEVICE_VECTOR ia64_first_device_vector 71#define IA64_LAST_DEVICE_VECTOR ia64_last_device_vector 72#define IA64_MAX_DEVICE_VECTORS (IA64_DEF_LAST_DEVICE_VECTOR - IA64_DEF_FIRST_DEVICE_VECTOR + 1) 73#define IA64_NUM_DEVICE_VECTORS (IA64_LAST_DEVICE_VECTOR - IA64_FIRST_DEVICE_VECTOR + 1) 74 75#define IA64_MCA_RENDEZ_VECTOR 0xe8 /* MCA rendez interrupt */ 76#define IA64_PERFMON_VECTOR 0xee /* performance monitor interrupt vector */ 77#define IA64_TIMER_VECTOR 0xef /* use highest-prio group 15 interrupt for timer */ 78#define IA64_MCA_WAKEUP_VECTOR 0xf0 /* MCA wakeup (must be >MCA_RENDEZ_VECTOR) */ 79#define IA64_IPI_LOCAL_TLB_FLUSH 0xfc /* SMP flush local TLB */ 80#define IA64_IPI_RESCHEDULE 0xfd /* SMP reschedule */ 81#define IA64_IPI_VECTOR 0xfe /* inter-processor interrupt vector */ 82 83/* Used for encoding redirected irqs */ 84 85#define IA64_IRQ_REDIRECTED (1 << 31) 86 87/* IA64 inter-cpu interrupt related definitions */ 88 89#define IA64_IPI_DEFAULT_BASE_ADDR 0xfee00000 90 91/* Delivery modes for inter-cpu interrupts */ 92enum { 93 IA64_IPI_DM_INT = 0x0, /* pend an external interrupt */ 94 IA64_IPI_DM_PMI = 0x2, /* pend a PMI */ 95 IA64_IPI_DM_NMI = 0x4, /* pend an NMI (vector 2) */ 96 IA64_IPI_DM_INIT = 0x5, /* pend an INIT interrupt */ 97 IA64_IPI_DM_EXTINT = 0x7, /* pend an 8259-compatible interrupt. */ 98}; 99 100extern __u8 isa_irq_to_vector_map[16]; 101#define isa_irq_to_vector(x) isa_irq_to_vector_map[(x)] 102 103struct irq_cfg { 104 ia64_vector vector; 105 cpumask_t domain; 106 cpumask_t old_domain; 107 unsigned move_cleanup_count; 108 u8 move_in_progress : 1; 109}; 110extern spinlock_t vector_lock; 111extern struct irq_cfg irq_cfg[NR_IRQS]; 112#define irq_to_domain(x) irq_cfg[(x)].domain 113DECLARE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq); 114 115extern struct irq_chip irq_type_ia64_lsapic; /* CPU-internal interrupt controller */ 116 117#ifdef CONFIG_PARAVIRT_GUEST 118#include <asm/paravirt.h> 119#else 120#define ia64_register_ipi ia64_native_register_ipi 121#define assign_irq_vector ia64_native_assign_irq_vector 122#define free_irq_vector ia64_native_free_irq_vector 123#define register_percpu_irq ia64_native_register_percpu_irq 124#define ia64_resend_irq ia64_native_resend_irq 125#endif 126 127extern void ia64_native_register_ipi(void); 128extern int bind_irq_vector(int irq, int vector, cpumask_t domain); 129extern int ia64_native_assign_irq_vector (int irq); /* allocate a free vector */ 130extern void ia64_native_free_irq_vector (int vector); 131extern int reserve_irq_vector (int vector); 132extern void __setup_vector_irq(int cpu); 133extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect); 134extern void ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action); 135extern int check_irq_used (int irq); 136extern void destroy_and_reserve_irq (unsigned int irq); 137 138#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG)) 139extern int irq_prepare_move(int irq, int cpu); 140extern void irq_complete_move(unsigned int irq); 141#else 142static inline int irq_prepare_move(int irq, int cpu) { return 0; } 143static inline void irq_complete_move(unsigned int irq) {} 144#endif 145 146static inline void ia64_native_resend_irq(unsigned int vector) 147{ 148 platform_send_ipi(smp_processor_id(), vector, IA64_IPI_DM_INT, 0); 149} 150 151/* 152 * Default implementations for the irq-descriptor API: 153 */ 154 155extern struct irq_desc irq_desc[NR_IRQS]; 156 157#ifndef CONFIG_IA64_GENERIC 158static inline ia64_vector __ia64_irq_to_vector(int irq) 159{ 160 return irq_cfg[irq].vector; 161} 162 163static inline unsigned int 164__ia64_local_vector_to_irq (ia64_vector vec) 165{ 166 return __get_cpu_var(vector_irq)[vec]; 167} 168#endif 169 170/* 171 * Next follows the irq descriptor interface. On IA-64, each CPU supports 256 interrupt 172 * vectors. On smaller systems, there is a one-to-one correspondence between interrupt 173 * vectors and the Linux irq numbers. However, larger systems may have multiple interrupt 174 * domains meaning that the translation from vector number to irq number depends on the 175 * interrupt domain that a CPU belongs to. This API abstracts such platform-dependent 176 * differences and provides a uniform means to translate between vector and irq numbers 177 * and to obtain the irq descriptor for a given irq number. 178 */ 179 180/* Extract the IA-64 vector that corresponds to IRQ. */ 181static inline ia64_vector 182irq_to_vector (int irq) 183{ 184 return platform_irq_to_vector(irq); 185} 186 187/* 188 * Convert the local IA-64 vector to the corresponding irq number. This translation is 189 * done in the context of the interrupt domain that the currently executing CPU belongs 190 * to. 191 */ 192static inline unsigned int 193local_vector_to_irq (ia64_vector vec) 194{ 195 return platform_local_vector_to_irq(vec); 196} 197 198#endif /* _ASM_IA64_HW_IRQ_H */ 199