1/* setup.c: FRV specific setup 2 * 3 * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved. 4 * Written by David Howells (dhowells@redhat.com) 5 * - Derived from arch/m68k/kernel/setup.c 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13#include <generated/utsrelease.h> 14#include <linux/kernel.h> 15#include <linux/sched.h> 16#include <linux/delay.h> 17#include <linux/interrupt.h> 18#include <linux/fs.h> 19#include <linux/mm.h> 20#include <linux/fb.h> 21#include <linux/console.h> 22#include <linux/genhd.h> 23#include <linux/errno.h> 24#include <linux/string.h> 25#include <linux/major.h> 26#include <linux/bootmem.h> 27#include <linux/highmem.h> 28#include <linux/seq_file.h> 29#include <linux/serial.h> 30#include <linux/serial_core.h> 31#include <linux/serial_reg.h> 32#include <linux/serial_8250.h> 33 34#include <asm/setup.h> 35#include <asm/irq.h> 36#include <asm/sections.h> 37#include <asm/pgalloc.h> 38#include <asm/busctl-regs.h> 39#include <asm/serial-regs.h> 40#include <asm/timer-regs.h> 41#include <asm/irc-regs.h> 42#include <asm/spr-regs.h> 43#include <asm/mb-regs.h> 44#include <asm/mb93493-regs.h> 45#include <asm/gdb-stub.h> 46#include <asm/io.h> 47 48#ifdef CONFIG_BLK_DEV_INITRD 49#include <asm/pgtable.h> 50#endif 51 52#include "local.h" 53 54#ifdef CONFIG_MB93090_MB00 55static void __init mb93090_display(void); 56#endif 57#ifdef CONFIG_MMU 58static void __init setup_linux_memory(void); 59#else 60static void __init setup_uclinux_memory(void); 61#endif 62 63#ifdef CONFIG_MB93090_MB00 64static char __initdata mb93090_banner[] = "FJ/RH FR-V Linux"; 65static char __initdata mb93090_version[] = UTS_RELEASE; 66 67int __nongprelbss mb93090_mb00_detected; 68#endif 69 70const char __frv_unknown_system[] = "unknown"; 71const char __frv_mb93091_cb10[] = "mb93091-cb10"; 72const char __frv_mb93091_cb11[] = "mb93091-cb11"; 73const char __frv_mb93091_cb30[] = "mb93091-cb30"; 74const char __frv_mb93091_cb41[] = "mb93091-cb41"; 75const char __frv_mb93091_cb60[] = "mb93091-cb60"; 76const char __frv_mb93091_cb70[] = "mb93091-cb70"; 77const char __frv_mb93091_cb451[] = "mb93091-cb451"; 78const char __frv_mb93090_mb00[] = "mb93090-mb00"; 79 80const char __frv_mb93493[] = "mb93493"; 81 82const char __frv_mb93093[] = "mb93093"; 83 84static const char *__nongprelbss cpu_series; 85static const char *__nongprelbss cpu_core; 86static const char *__nongprelbss cpu_silicon; 87static const char *__nongprelbss cpu_mmu; 88static const char *__nongprelbss cpu_system; 89static const char *__nongprelbss cpu_board1; 90static const char *__nongprelbss cpu_board2; 91 92static unsigned long __nongprelbss cpu_psr_all; 93static unsigned long __nongprelbss cpu_hsr0_all; 94 95unsigned long __nongprelbss pdm_suspend_mode; 96 97unsigned long __nongprelbss rom_length; 98unsigned long __nongprelbss memory_start; 99unsigned long __nongprelbss memory_end; 100 101unsigned long __nongprelbss dma_coherent_mem_start; 102unsigned long __nongprelbss dma_coherent_mem_end; 103 104unsigned long __initdata __sdram_old_base; 105unsigned long __initdata num_mappedpages; 106 107struct cpuinfo_frv __nongprelbss boot_cpu_data; 108 109char __initdata command_line[COMMAND_LINE_SIZE]; 110char __initdata redboot_command_line[COMMAND_LINE_SIZE]; 111 112#ifdef CONFIG_PM 113#define __pminit 114#define __pminitdata 115#else 116#define __pminit __init 117#define __pminitdata __initdata 118#endif 119 120struct clock_cmode { 121 uint8_t xbus, sdram, corebus, core, dsu; 122}; 123 124#define _frac(N,D) ((N)<<4 | (D)) 125#define _x0_16 _frac(1,6) 126#define _x0_25 _frac(1,4) 127#define _x0_33 _frac(1,3) 128#define _x0_375 _frac(3,8) 129#define _x0_5 _frac(1,2) 130#define _x0_66 _frac(2,3) 131#define _x0_75 _frac(3,4) 132#define _x1 _frac(1,1) 133#define _x1_5 _frac(3,2) 134#define _x2 _frac(2,1) 135#define _x3 _frac(3,1) 136#define _x4 _frac(4,1) 137#define _x4_5 _frac(9,2) 138#define _x6 _frac(6,1) 139#define _x8 _frac(8,1) 140#define _x9 _frac(9,1) 141 142int __nongprelbss clock_p0_current; 143int __nongprelbss clock_cm_current; 144int __nongprelbss clock_cmode_current; 145#ifdef CONFIG_PM 146int __nongprelbss clock_cmodes_permitted; 147unsigned long __nongprelbss clock_bits_settable; 148#endif 149 150static struct clock_cmode __pminitdata undef_clock_cmode = { _x1, _x1, _x1, _x1, _x1 }; 151 152static struct clock_cmode __pminitdata clock_cmodes_fr401_fr403[16] = { 153 [4] = { _x1, _x1, _x2, _x2, _x0_25 }, 154 [5] = { _x1, _x2, _x4, _x4, _x0_5 }, 155 [8] = { _x1, _x1, _x1, _x2, _x0_25 }, 156 [9] = { _x1, _x2, _x2, _x4, _x0_5 }, 157 [11] = { _x1, _x4, _x4, _x8, _x1 }, 158 [12] = { _x1, _x1, _x2, _x4, _x0_5 }, 159 [13] = { _x1, _x2, _x4, _x8, _x1 }, 160}; 161 162static struct clock_cmode __pminitdata clock_cmodes_fr405[16] = { 163 [0] = { _x1, _x1, _x1, _x1, _x0_5 }, 164 [1] = { _x1, _x1, _x1, _x3, _x0_25 }, 165 [2] = { _x1, _x1, _x2, _x6, _x0_5 }, 166 [3] = { _x1, _x2, _x2, _x6, _x0_5 }, 167 [4] = { _x1, _x1, _x2, _x2, _x0_16 }, 168 [8] = { _x1, _x1, _x1, _x2, _x0_16 }, 169 [9] = { _x1, _x2, _x2, _x4, _x0_33 }, 170 [12] = { _x1, _x1, _x2, _x4, _x0_33 }, 171 [14] = { _x1, _x3, _x3, _x9, _x0_75 }, 172 [15] = { _x1, _x1_5, _x1_5, _x4_5, _x0_375 }, 173 174#define CLOCK_CMODES_PERMITTED_FR405 0xd31f 175}; 176 177static struct clock_cmode __pminitdata clock_cmodes_fr555[16] = { 178 [0] = { _x1, _x2, _x2, _x4, _x0_33 }, 179 [1] = { _x1, _x3, _x3, _x6, _x0_5 }, 180 [2] = { _x1, _x2, _x4, _x8, _x0_66 }, 181 [3] = { _x1, _x1_5, _x3, _x6, _x0_5 }, 182 [4] = { _x1, _x3, _x3, _x9, _x0_75 }, 183 [5] = { _x1, _x2, _x2, _x6, _x0_5 }, 184 [6] = { _x1, _x1_5, _x1_5, _x4_5, _x0_375 }, 185}; 186 187static const struct clock_cmode __pminitdata *clock_cmodes; 188static int __pminitdata clock_doubled; 189 190static struct uart_port __pminitdata __frv_uart0 = { 191 .uartclk = 0, 192 .membase = (char *) UART0_BASE, 193 .irq = IRQ_CPU_UART0, 194 .regshift = 3, 195 .iotype = UPIO_MEM, 196 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, 197}; 198 199static struct uart_port __pminitdata __frv_uart1 = { 200 .uartclk = 0, 201 .membase = (char *) UART1_BASE, 202 .irq = IRQ_CPU_UART1, 203 .regshift = 3, 204 .iotype = UPIO_MEM, 205 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, 206}; 207 208 209/*****************************************************************************/ 210/* 211 * dump the memory map 212 */ 213static void __init dump_memory_map(void) 214{ 215 216 217 218} /* end dump_memory_map() */ 219 220/*****************************************************************************/ 221/* 222 * attempt to detect a VDK motherboard and DAV daughter board on an MB93091 system 223 */ 224#ifdef CONFIG_MB93091_VDK 225static void __init detect_mb93091(void) 226{ 227#ifdef CONFIG_MB93090_MB00 228 /* Detect CB70 without motherboard */ 229 if (!(cpu_system == __frv_mb93091_cb70 && ((*(unsigned short *)0xffc00030) & 0x100))) { 230 cpu_board1 = __frv_mb93090_mb00; 231 mb93090_mb00_detected = 1; 232 } 233#endif 234 235#ifdef CONFIG_FUJITSU_MB93493 236 cpu_board2 = __frv_mb93493; 237#endif 238 239} /* end detect_mb93091() */ 240#endif 241 242/*****************************************************************************/ 243/* 244 * determine the CPU type and set appropriate parameters 245 * 246 * Family Series CPU Core Silicon Imple Vers 247 * ---------------------------------------------------------- 248 * FR-V --+-> FR400 --+-> FR401 --+-> MB93401 02 00 [1] 249 * | | | 250 * | | +-> MB93401/A 02 01 251 * | | | 252 * | | +-> MB93403 02 02 253 * | | 254 * | +-> FR405 ----> MB93405 04 00 255 * | 256 * +-> FR450 ----> FR451 ----> MB93451 05 00 257 * | 258 * +-> FR500 ----> FR501 --+-> MB93501 01 01 [2] 259 * | | 260 * | +-> MB93501/A 01 02 261 * | 262 * +-> FR550 --+-> FR551 ----> MB93555 03 01 263 * 264 * [1] The MB93401 is an obsolete CPU replaced by the MB93401A 265 * [2] The MB93501 is an obsolete CPU replaced by the MB93501A 266 * 267 * Imple is PSR(Processor Status Register)[31:28]. 268 * Vers is PSR(Processor Status Register)[27:24]. 269 * 270 * A "Silicon" consists of CPU core and some on-chip peripherals. 271 */ 272static void __init determine_cpu(void) 273{ 274 unsigned long hsr0 = __get_HSR(0); 275 unsigned long psr = __get_PSR(); 276 277 /* work out what selectable services the CPU supports */ 278 __set_PSR(psr | PSR_EM | PSR_EF | PSR_CM | PSR_NEM); 279 cpu_psr_all = __get_PSR(); 280 __set_PSR(psr); 281 282 __set_HSR(0, hsr0 | HSR0_GRLE | HSR0_GRHE | HSR0_FRLE | HSR0_FRHE); 283 cpu_hsr0_all = __get_HSR(0); 284 __set_HSR(0, hsr0); 285 286 /* derive other service specs from the CPU type */ 287 cpu_series = "unknown"; 288 cpu_core = "unknown"; 289 cpu_silicon = "unknown"; 290 cpu_mmu = "Prot"; 291 cpu_system = __frv_unknown_system; 292 clock_cmodes = NULL; 293 clock_doubled = 0; 294#ifdef CONFIG_PM 295 clock_bits_settable = CLOCK_BIT_CM_H | CLOCK_BIT_CM_M | CLOCK_BIT_P0; 296#endif 297 298 switch (PSR_IMPLE(psr)) { 299 case PSR_IMPLE_FR401: 300 cpu_series = "fr400"; 301 cpu_core = "fr401"; 302 pdm_suspend_mode = HSR0_PDM_PLL_RUN; 303 304 switch (PSR_VERSION(psr)) { 305 case PSR_VERSION_FR401_MB93401: 306 cpu_silicon = "mb93401"; 307 cpu_system = __frv_mb93091_cb10; 308 clock_cmodes = clock_cmodes_fr401_fr403; 309 clock_doubled = 1; 310 break; 311 case PSR_VERSION_FR401_MB93401A: 312 cpu_silicon = "mb93401/A"; 313 cpu_system = __frv_mb93091_cb11; 314 clock_cmodes = clock_cmodes_fr401_fr403; 315 break; 316 case PSR_VERSION_FR401_MB93403: 317 cpu_silicon = "mb93403"; 318#ifndef CONFIG_MB93093_PDK 319 cpu_system = __frv_mb93091_cb30; 320#else 321 cpu_system = __frv_mb93093; 322#endif 323 clock_cmodes = clock_cmodes_fr401_fr403; 324 break; 325 default: 326 break; 327 } 328 break; 329 330 case PSR_IMPLE_FR405: 331 cpu_series = "fr400"; 332 cpu_core = "fr405"; 333 pdm_suspend_mode = HSR0_PDM_PLL_STOP; 334 335 switch (PSR_VERSION(psr)) { 336 case PSR_VERSION_FR405_MB93405: 337 cpu_silicon = "mb93405"; 338 cpu_system = __frv_mb93091_cb60; 339 clock_cmodes = clock_cmodes_fr405; 340#ifdef CONFIG_PM 341 clock_bits_settable |= CLOCK_BIT_CMODE; 342 clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405; 343#endif 344 345 /* the FPGA on the CB70 has extra registers 346 * - it has 0x0046 in the VDK_ID FPGA register at 0x1a0, which is 347 * how we tell the difference between it and a CB60 348 */ 349 if (*(volatile unsigned short *) 0xffc001a0 == 0x0046) 350 cpu_system = __frv_mb93091_cb70; 351 break; 352 default: 353 break; 354 } 355 break; 356 357 case PSR_IMPLE_FR451: 358 cpu_series = "fr450"; 359 cpu_core = "fr451"; 360 pdm_suspend_mode = HSR0_PDM_PLL_STOP; 361#ifdef CONFIG_PM 362 clock_bits_settable |= CLOCK_BIT_CMODE; 363 clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405; 364#endif 365 switch (PSR_VERSION(psr)) { 366 case PSR_VERSION_FR451_MB93451: 367 cpu_silicon = "mb93451"; 368 cpu_mmu = "Prot, SAT, xSAT, DAT"; 369 cpu_system = __frv_mb93091_cb451; 370 clock_cmodes = clock_cmodes_fr405; 371 break; 372 default: 373 break; 374 } 375 break; 376 377 case PSR_IMPLE_FR501: 378 cpu_series = "fr500"; 379 cpu_core = "fr501"; 380 pdm_suspend_mode = HSR0_PDM_PLL_STOP; 381 382 switch (PSR_VERSION(psr)) { 383 case PSR_VERSION_FR501_MB93501: cpu_silicon = "mb93501"; break; 384 case PSR_VERSION_FR501_MB93501A: cpu_silicon = "mb93501/A"; break; 385 default: 386 break; 387 } 388 break; 389 390 case PSR_IMPLE_FR551: 391 cpu_series = "fr550"; 392 cpu_core = "fr551"; 393 pdm_suspend_mode = HSR0_PDM_PLL_RUN; 394 395 switch (PSR_VERSION(psr)) { 396 case PSR_VERSION_FR551_MB93555: 397 cpu_silicon = "mb93555"; 398 cpu_mmu = "Prot, SAT"; 399 cpu_system = __frv_mb93091_cb41; 400 clock_cmodes = clock_cmodes_fr555; 401 clock_doubled = 1; 402 break; 403 default: 404 break; 405 } 406 break; 407 408 default: 409 break; 410 } 411 412 printk("- Series:%s CPU:%s Silicon:%s\n", 413 cpu_series, cpu_core, cpu_silicon); 414 415#ifdef CONFIG_MB93091_VDK 416 detect_mb93091(); 417#endif 418 419#if defined(CONFIG_MB93093_PDK) && defined(CONFIG_FUJITSU_MB93493) 420 cpu_board2 = __frv_mb93493; 421#endif 422 423} /* end determine_cpu() */ 424 425/*****************************************************************************/ 426/* 427 * calculate the bus clock speed 428 */ 429void __pminit determine_clocks(int verbose) 430{ 431 const struct clock_cmode *mode, *tmode; 432 unsigned long clkc, psr, quot; 433 434 clkc = __get_CLKC(); 435 psr = __get_PSR(); 436 437 clock_p0_current = !!(clkc & CLKC_P0); 438 clock_cm_current = clkc & CLKC_CM; 439 clock_cmode_current = (clkc & CLKC_CMODE) >> CLKC_CMODE_s; 440 441 if (verbose) 442 printk("psr=%08lx hsr0=%08lx clkc=%08lx\n", psr, __get_HSR(0), clkc); 443 444 /* the CB70 has some alternative ways of setting the clock speed through switches accessed 445 * through the FPGA. */ 446 if (cpu_system == __frv_mb93091_cb70) { 447 unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL; 448 449 if (clkswr & 0x1000) 450 __clkin_clock_speed_HZ = 60000000UL; 451 else 452 __clkin_clock_speed_HZ = 453 ((clkswr >> 8) & 0xf) * 10000000 + 454 ((clkswr >> 4) & 0xf) * 1000000 + 455 ((clkswr ) & 0xf) * 100000; 456 } 457 /* the FR451 is currently fixed at 24MHz */ 458 else if (cpu_system == __frv_mb93091_cb451) { 459 //__clkin_clock_speed_HZ = 24000000UL; // CB451-FPGA 460 unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL; 461 462 if (clkswr & 0x1000) 463 __clkin_clock_speed_HZ = 60000000UL; 464 else 465 __clkin_clock_speed_HZ = 466 ((clkswr >> 8) & 0xf) * 10000000 + 467 ((clkswr >> 4) & 0xf) * 1000000 + 468 ((clkswr ) & 0xf) * 100000; 469 } 470 /* otherwise determine the clockspeed from VDK or other registers */ 471 else { 472 __clkin_clock_speed_HZ = __get_CLKIN(); 473 } 474 475 /* look up the appropriate clock relationships table entry */ 476 mode = &undef_clock_cmode; 477 if (clock_cmodes) { 478 tmode = &clock_cmodes[(clkc & CLKC_CMODE) >> CLKC_CMODE_s]; 479 if (tmode->xbus) 480 mode = tmode; 481 } 482 483#define CLOCK(SRC,RATIO) ((SRC) * (((RATIO) >> 4) & 0x0f) / ((RATIO) & 0x0f)) 484 485 if (clock_doubled) 486 __clkin_clock_speed_HZ <<= 1; 487 488 __ext_bus_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->xbus); 489 __sdram_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->sdram); 490 __dsu_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->dsu); 491 492 switch (clkc & CLKC_CM) { 493 case 0: /* High */ 494 __core_bus_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->corebus); 495 __core_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->core); 496 break; 497 case 1: /* Medium */ 498 __core_bus_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->sdram); 499 __core_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->sdram); 500 break; 501 case 2: /* Low; not supported */ 502 case 3: /* UNDEF */ 503 printk("Unsupported CLKC CM %ld\n", clkc & CLKC_CM); 504 panic("Bye"); 505 } 506 507 __res_bus_clock_speed_HZ = __ext_bus_clock_speed_HZ; 508 if (clkc & CLKC_P0) 509 __res_bus_clock_speed_HZ >>= 1; 510 511 if (verbose) { 512 printk("CLKIN: %lu.%3.3luMHz\n", 513 __clkin_clock_speed_HZ / 1000000, 514 (__clkin_clock_speed_HZ / 1000) % 1000); 515 516 printk("CLKS:" 517 " ext=%luMHz res=%luMHz sdram=%luMHz cbus=%luMHz core=%luMHz dsu=%luMHz\n", 518 __ext_bus_clock_speed_HZ / 1000000, 519 __res_bus_clock_speed_HZ / 1000000, 520 __sdram_clock_speed_HZ / 1000000, 521 __core_bus_clock_speed_HZ / 1000000, 522 __core_clock_speed_HZ / 1000000, 523 __dsu_clock_speed_HZ / 1000000 524 ); 525 } 526 527 /* calculate the number of __delay() loop iterations per sec (2 insn loop) */ 528 __delay_loops_MHz = __core_clock_speed_HZ / (1000000 * 2); 529 530 /* set the serial prescaler */ 531 __serial_clock_speed_HZ = __res_bus_clock_speed_HZ; 532 quot = 1; 533 while (__serial_clock_speed_HZ / quot / 16 / 65536 > 3000) 534 quot += 1; 535 536 /* double the divisor if P0 is clear, so that if/when P0 is set, it's still achievable 537 * - we have to be careful - dividing too much can mean we can't get 115200 baud 538 */ 539 if (__serial_clock_speed_HZ > 32000000 && !(clkc & CLKC_P0)) 540 quot <<= 1; 541 542 __serial_clock_speed_HZ /= quot; 543 __frv_uart0.uartclk = __serial_clock_speed_HZ; 544 __frv_uart1.uartclk = __serial_clock_speed_HZ; 545 546 if (verbose) 547 printk(" uart=%luMHz\n", __serial_clock_speed_HZ / 1000000 * quot); 548 549 while (!(__get_UART0_LSR() & UART_LSR_TEMT)) 550 continue; 551 552 while (!(__get_UART1_LSR() & UART_LSR_TEMT)) 553 continue; 554 555 __set_UCPVR(quot); 556 __set_UCPSR(0); 557} /* end determine_clocks() */ 558 559/*****************************************************************************/ 560/* 561 * reserve some DMA consistent memory 562 */ 563#ifdef CONFIG_RESERVE_DMA_COHERENT 564static void __init reserve_dma_coherent(void) 565{ 566 unsigned long ampr; 567 568 /* find the first non-kernel memory tile and steal it */ 569#define __steal_AMPR(r) \ 570 if (__get_DAMPR(r) & xAMPRx_V) { \ 571 ampr = __get_DAMPR(r); \ 572 __set_DAMPR(r, ampr | xAMPRx_S | xAMPRx_C); \ 573 __set_IAMPR(r, 0); \ 574 goto found; \ 575 } 576 577 __steal_AMPR(1); 578 __steal_AMPR(2); 579 __steal_AMPR(3); 580 __steal_AMPR(4); 581 __steal_AMPR(5); 582 __steal_AMPR(6); 583 584 if (PSR_IMPLE(__get_PSR()) == PSR_IMPLE_FR551) { 585 __steal_AMPR(7); 586 __steal_AMPR(8); 587 __steal_AMPR(9); 588 __steal_AMPR(10); 589 __steal_AMPR(11); 590 __steal_AMPR(12); 591 __steal_AMPR(13); 592 __steal_AMPR(14); 593 } 594 595 /* unable to grant any DMA consistent memory */ 596 printk("No DMA consistent memory reserved\n"); 597 return; 598 599 found: 600 dma_coherent_mem_start = ampr & xAMPRx_PPFN; 601 ampr &= xAMPRx_SS; 602 ampr >>= 4; 603 ampr = 1 << (ampr - 3 + 20); 604 dma_coherent_mem_end = dma_coherent_mem_start + ampr; 605 606 printk("DMA consistent memory reserved %lx-%lx\n", 607 dma_coherent_mem_start, dma_coherent_mem_end); 608 609} /* end reserve_dma_coherent() */ 610#endif 611 612/*****************************************************************************/ 613/* 614 * calibrate the delay loop 615 */ 616void __cpuinit calibrate_delay(void) 617{ 618 loops_per_jiffy = __delay_loops_MHz * (1000000 / HZ); 619 620 printk("Calibrating delay loop... %lu.%02lu BogoMIPS\n", 621 loops_per_jiffy / (500000 / HZ), 622 (loops_per_jiffy / (5000 / HZ)) % 100); 623 624} /* end calibrate_delay() */ 625 626/*****************************************************************************/ 627/* 628 * look through the command line for some things we need to know immediately 629 */ 630static void __init parse_cmdline_early(char *cmdline) 631{ 632 if (!cmdline) 633 return; 634 635 while (*cmdline) { 636 if (*cmdline == ' ') 637 cmdline++; 638 639 if (!memcmp(cmdline, "mem=", 4)) { 640 unsigned long long mem_size; 641 642 mem_size = memparse(cmdline + 4, &cmdline); 643 memory_end = memory_start + mem_size; 644 } 645 646 while (*cmdline && *cmdline != ' ') 647 cmdline++; 648 } 649 650} /* end parse_cmdline_early() */ 651 652/*****************************************************************************/ 653/* 654 * 655 */ 656void __init setup_arch(char **cmdline_p) 657{ 658#ifdef CONFIG_MMU 659 printk("Linux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n"); 660#else 661 printk("uClinux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n"); 662#endif 663 664 memcpy(boot_command_line, redboot_command_line, COMMAND_LINE_SIZE); 665 666 determine_cpu(); 667 determine_clocks(1); 668 669 /* For printk-directly-beats-on-serial-hardware hack */ 670 console_set_baud(115200); 671#ifdef CONFIG_GDBSTUB 672 gdbstub_set_baud(115200); 673#endif 674 675#ifdef CONFIG_RESERVE_DMA_COHERENT 676 reserve_dma_coherent(); 677#endif 678 dump_memory_map(); 679 680#ifdef CONFIG_MB93090_MB00 681 if (mb93090_mb00_detected) 682 mb93090_display(); 683#endif 684 685 /* register those serial ports that are available */ 686#ifdef CONFIG_FRV_ONCPU_SERIAL 687#ifndef CONFIG_GDBSTUB_UART0 688 __reg(UART0_BASE + UART_IER * 8) = 0; 689 early_serial_setup(&__frv_uart0); 690#endif 691#ifndef CONFIG_GDBSTUB_UART1 692 __reg(UART1_BASE + UART_IER * 8) = 0; 693 early_serial_setup(&__frv_uart1); 694#endif 695#endif 696 697 /* deal with the command line - RedBoot may have passed one to the kernel */ 698 memcpy(command_line, boot_command_line, sizeof(command_line)); 699 *cmdline_p = &command_line[0]; 700 parse_cmdline_early(command_line); 701 702 /* set up the memory description 703 * - by now the stack is part of the init task */ 704 printk("Memory %08lx-%08lx\n", memory_start, memory_end); 705 706 BUG_ON(memory_start == memory_end); 707 708 init_mm.start_code = (unsigned long) &_stext; 709 init_mm.end_code = (unsigned long) &_etext; 710 init_mm.end_data = (unsigned long) &_edata; 711 init_mm.brk = (unsigned long) 0; 712 713#ifdef DEBUG 714 printk("KERNEL -> TEXT=0x%06x-0x%06x DATA=0x%06x-0x%06x BSS=0x%06x-0x%06x\n", 715 (int) &_stext, (int) &_etext, 716 (int) &_sdata, (int) &_edata, 717 (int) &_sbss, (int) &_ebss); 718#endif 719 720#ifdef CONFIG_VT 721#if defined(CONFIG_VGA_CONSOLE) 722 conswitchp = &vga_con; 723#elif defined(CONFIG_DUMMY_CONSOLE) 724 conswitchp = &dummy_con; 725#endif 726#endif 727 728#ifdef CONFIG_MMU 729 setup_linux_memory(); 730#else 731 setup_uclinux_memory(); 732#endif 733 734 /* get kmalloc into gear */ 735 paging_init(); 736 737 /* init DMA */ 738 frv_dma_init(); 739#ifdef DEBUG 740 printk("Done setup_arch\n"); 741#endif 742 743 /* start the decrement timer running */ 744// asm volatile("movgs %0,timerd" :: "r"(10000000)); 745// __set_HSR(0, __get_HSR(0) | HSR0_ETMD); 746 747} /* end setup_arch() */ 748 749 750/*****************************************************************************/ 751/* 752 * set up the memory map for normal MMU linux 753 */ 754#ifdef CONFIG_MMU 755static void __init setup_linux_memory(void) 756{ 757 unsigned long bootmap_size, low_top_pfn, kstart, kend, high_mem; 758 759 kstart = (unsigned long) &__kernel_image_start - PAGE_OFFSET; 760 kend = (unsigned long) &__kernel_image_end - PAGE_OFFSET; 761 762 kstart = kstart & PAGE_MASK; 763 kend = (kend + PAGE_SIZE - 1) & PAGE_MASK; 764 765 /* give all the memory to the bootmap allocator, tell it to put the 766 * boot mem_map immediately following the kernel image 767 */ 768 bootmap_size = init_bootmem_node(NODE_DATA(0), 769 kend >> PAGE_SHIFT, /* map addr */ 770 memory_start >> PAGE_SHIFT, /* start of RAM */ 771 memory_end >> PAGE_SHIFT /* end of RAM */ 772 ); 773 774 /* pass the memory that the kernel can immediately use over to the bootmem allocator */ 775 max_mapnr = num_physpages = (memory_end - memory_start) >> PAGE_SHIFT; 776 low_top_pfn = (KERNEL_LOWMEM_END - KERNEL_LOWMEM_START) >> PAGE_SHIFT; 777 high_mem = 0; 778 779 if (num_physpages > low_top_pfn) { 780#ifdef CONFIG_HIGHMEM 781 high_mem = num_physpages - low_top_pfn; 782#else 783 max_mapnr = num_physpages = low_top_pfn; 784#endif 785 } 786 else { 787 low_top_pfn = num_physpages; 788 } 789 790 min_low_pfn = memory_start >> PAGE_SHIFT; 791 max_low_pfn = low_top_pfn; 792 max_pfn = memory_end >> PAGE_SHIFT; 793 794 num_mappedpages = low_top_pfn; 795 796 printk(KERN_NOTICE "%ldMB LOWMEM available.\n", low_top_pfn >> (20 - PAGE_SHIFT)); 797 798 free_bootmem(memory_start, low_top_pfn << PAGE_SHIFT); 799 800#ifdef CONFIG_HIGHMEM 801 if (high_mem) 802 printk(KERN_NOTICE "%ldMB HIGHMEM available.\n", high_mem >> (20 - PAGE_SHIFT)); 803#endif 804 805 /* take back the memory occupied by the kernel image and the bootmem alloc map */ 806 reserve_bootmem(kstart, kend - kstart + bootmap_size, 807 BOOTMEM_DEFAULT); 808 809 /* reserve the memory occupied by the initial ramdisk */ 810#ifdef CONFIG_BLK_DEV_INITRD 811 if (LOADER_TYPE && INITRD_START) { 812 if (INITRD_START + INITRD_SIZE <= (low_top_pfn << PAGE_SHIFT)) { 813 reserve_bootmem(INITRD_START, INITRD_SIZE, 814 BOOTMEM_DEFAULT); 815 initrd_start = INITRD_START + PAGE_OFFSET; 816 initrd_end = initrd_start + INITRD_SIZE; 817 } 818 else { 819 printk(KERN_ERR 820 "initrd extends beyond end of memory (0x%08lx > 0x%08lx)\n" 821 "disabling initrd\n", 822 INITRD_START + INITRD_SIZE, 823 low_top_pfn << PAGE_SHIFT); 824 initrd_start = 0; 825 } 826 } 827#endif 828 829} /* end setup_linux_memory() */ 830#endif 831 832/*****************************************************************************/ 833/* 834 * set up the memory map for uClinux 835 */ 836#ifndef CONFIG_MMU 837static void __init setup_uclinux_memory(void) 838{ 839#ifdef CONFIG_PROTECT_KERNEL 840 unsigned long dampr; 841#endif 842 unsigned long kend; 843 int bootmap_size; 844 845 kend = (unsigned long) &__kernel_image_end; 846 kend = (kend + PAGE_SIZE - 1) & PAGE_MASK; 847 848 /* give all the memory to the bootmap allocator, tell it to put the 849 * boot mem_map immediately following the kernel image 850 */ 851 bootmap_size = init_bootmem_node(NODE_DATA(0), 852 kend >> PAGE_SHIFT, /* map addr */ 853 memory_start >> PAGE_SHIFT, /* start of RAM */ 854 memory_end >> PAGE_SHIFT /* end of RAM */ 855 ); 856 857 /* free all the usable memory */ 858 free_bootmem(memory_start, memory_end - memory_start); 859 860 high_memory = (void *) (memory_end & PAGE_MASK); 861 max_mapnr = num_physpages = ((unsigned long) high_memory - PAGE_OFFSET) >> PAGE_SHIFT; 862 863 min_low_pfn = memory_start >> PAGE_SHIFT; 864 max_low_pfn = memory_end >> PAGE_SHIFT; 865 max_pfn = max_low_pfn; 866 867 /* now take back the bits the core kernel is occupying */ 868#ifndef CONFIG_PROTECT_KERNEL 869 reserve_bootmem(kend, bootmap_size, BOOTMEM_DEFAULT); 870 reserve_bootmem((unsigned long) &__kernel_image_start, 871 kend - (unsigned long) &__kernel_image_start, 872 BOOTMEM_DEFAULT); 873 874#else 875 dampr = __get_DAMPR(0); 876 dampr &= xAMPRx_SS; 877 dampr = (dampr >> 4) + 17; 878 dampr = 1 << dampr; 879 880 reserve_bootmem(__get_DAMPR(0) & xAMPRx_PPFN, dampr, BOOTMEM_DEFAULT); 881#endif 882 883 /* reserve some memory to do uncached DMA through if requested */ 884#ifdef CONFIG_RESERVE_DMA_COHERENT 885 if (dma_coherent_mem_start) 886 reserve_bootmem(dma_coherent_mem_start, 887 dma_coherent_mem_end - dma_coherent_mem_start, 888 BOOTMEM_DEFAULT); 889#endif 890 891} /* end setup_uclinux_memory() */ 892#endif 893 894/*****************************************************************************/ 895/* 896 * get CPU information for use by procfs 897 */ 898static int show_cpuinfo(struct seq_file *m, void *v) 899{ 900 const char *gr, *fr, *fm, *fp, *cm, *nem, *ble; 901#ifdef CONFIG_PM 902 const char *sep; 903#endif 904 905 gr = cpu_hsr0_all & HSR0_GRHE ? "gr0-63" : "gr0-31"; 906 fr = cpu_hsr0_all & HSR0_FRHE ? "fr0-63" : "fr0-31"; 907 fm = cpu_psr_all & PSR_EM ? ", Media" : ""; 908 fp = cpu_psr_all & PSR_EF ? ", FPU" : ""; 909 cm = cpu_psr_all & PSR_CM ? ", CCCR" : ""; 910 nem = cpu_psr_all & PSR_NEM ? ", NE" : ""; 911 ble = cpu_psr_all & PSR_BE ? "BE" : "LE"; 912 913 seq_printf(m, 914 "CPU-Series:\t%s\n" 915 "CPU-Core:\t%s, %s, %s%s%s\n" 916 "CPU:\t\t%s\n" 917 "MMU:\t\t%s\n" 918 "FP-Media:\t%s%s%s\n" 919 "System:\t\t%s", 920 cpu_series, 921 cpu_core, gr, ble, cm, nem, 922 cpu_silicon, 923 cpu_mmu, 924 fr, fm, fp, 925 cpu_system); 926 927 if (cpu_board1) 928 seq_printf(m, ", %s", cpu_board1); 929 930 if (cpu_board2) 931 seq_printf(m, ", %s", cpu_board2); 932 933 seq_printf(m, "\n"); 934 935#ifdef CONFIG_PM 936 seq_printf(m, "PM-Controls:"); 937 sep = "\t"; 938 939 if (clock_bits_settable & CLOCK_BIT_CMODE) { 940 seq_printf(m, "%scmode=0x%04hx", sep, clock_cmodes_permitted); 941 sep = ", "; 942 } 943 944 if (clock_bits_settable & CLOCK_BIT_CM) { 945 seq_printf(m, "%scm=0x%lx", sep, clock_bits_settable & CLOCK_BIT_CM); 946 sep = ", "; 947 } 948 949 if (clock_bits_settable & CLOCK_BIT_P0) { 950 seq_printf(m, "%sp0=0x3", sep); 951 sep = ", "; 952 } 953 954 seq_printf(m, "%ssuspend=0x22\n", sep); 955#endif 956 957 seq_printf(m, 958 "PM-Status:\tcmode=%d, cm=%d, p0=%d\n", 959 clock_cmode_current, clock_cm_current, clock_p0_current); 960 961#define print_clk(TAG, VAR) \ 962 seq_printf(m, "Clock-" TAG ":\t%lu.%2.2lu MHz\n", VAR / 1000000, (VAR / 10000) % 100) 963 964 print_clk("In", __clkin_clock_speed_HZ); 965 print_clk("Core", __core_clock_speed_HZ); 966 print_clk("SDRAM", __sdram_clock_speed_HZ); 967 print_clk("CBus", __core_bus_clock_speed_HZ); 968 print_clk("Res", __res_bus_clock_speed_HZ); 969 print_clk("Ext", __ext_bus_clock_speed_HZ); 970 print_clk("DSU", __dsu_clock_speed_HZ); 971 972 seq_printf(m, 973 "BogoMips:\t%lu.%02lu\n", 974 (loops_per_jiffy * HZ) / 500000, ((loops_per_jiffy * HZ) / 5000) % 100); 975 976 return 0; 977} /* end show_cpuinfo() */ 978 979static void *c_start(struct seq_file *m, loff_t *pos) 980{ 981 return *pos < NR_CPUS ? (void *) 0x12345678 : NULL; 982} 983 984static void *c_next(struct seq_file *m, void *v, loff_t *pos) 985{ 986 ++*pos; 987 return c_start(m, pos); 988} 989 990static void c_stop(struct seq_file *m, void *v) 991{ 992} 993 994const struct seq_operations cpuinfo_op = { 995 .start = c_start, 996 .next = c_next, 997 .stop = c_stop, 998 .show = show_cpuinfo, 999}; 1000 1001void arch_gettod(int *year, int *mon, int *day, int *hour, 1002 int *min, int *sec) 1003{ 1004 *year = *mon = *day = *hour = *min = *sec = 0; 1005} 1006 1007/*****************************************************************************/ 1008/* 1009 * 1010 */ 1011#ifdef CONFIG_MB93090_MB00 1012static void __init mb93090_sendlcdcmd(uint32_t cmd) 1013{ 1014 unsigned long base = __addr_LCD(); 1015 int loop; 1016 1017 /* request reading of the busy flag */ 1018 __set_LCD(base, LCD_CMD_READ_BUSY); 1019 __set_LCD(base, LCD_CMD_READ_BUSY & ~LCD_E); 1020 1021 /* wait for the busy flag to become clear */ 1022 for (loop = 10000; loop > 0; loop--) 1023 if (!(__get_LCD(base) & 0x80)) 1024 break; 1025 1026 /* send the command */ 1027 __set_LCD(base, cmd); 1028 __set_LCD(base, cmd & ~LCD_E); 1029 1030} /* end mb93090_sendlcdcmd() */ 1031 1032/*****************************************************************************/ 1033/* 1034 * write to the MB93090 LEDs and LCD 1035 */ 1036static void __init mb93090_display(void) 1037{ 1038 const char *p; 1039 1040 __set_LEDS(0); 1041 1042 /* set up the LCD */ 1043 mb93090_sendlcdcmd(LCD_CMD_CLEAR); 1044 mb93090_sendlcdcmd(LCD_CMD_FUNCSET(1,1,0)); 1045 mb93090_sendlcdcmd(LCD_CMD_ON(0,0)); 1046 mb93090_sendlcdcmd(LCD_CMD_HOME); 1047 1048 mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(0)); 1049 for (p = mb93090_banner; *p; p++) 1050 mb93090_sendlcdcmd(LCD_DATA_WRITE(*p)); 1051 1052 mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(64)); 1053 for (p = mb93090_version; *p; p++) 1054 mb93090_sendlcdcmd(LCD_DATA_WRITE(*p)); 1055 1056} /* end mb93090_display() */ 1057 1058#endif // CONFIG_MB93090_MB00 1059