1/* 2 * The following devices are accessable using this driver using 3 * GPIO_MAJOR (120) and a couple of minor numbers. 4 * 5 * For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10): 6 * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction 7 * /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction 8 * /dev/leds minor 2, Access to leds depending on kernelconfig 9 * /dev/gpiog minor 3 10 * g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG 11 * g1-g7 and g25-g31 is both input and outputs but on different pins 12 * Also note that some bits change pins depending on what interfaces 13 * are enabled. 14 * 15 * For ETRAX FS (CONFIG_ETRAXFS): 16 * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction 17 * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction 18 * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction 19 * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction 20 * /dev/gpioe minor 5, 18 bit GPIO, each bit can change direction 21 * /dev/leds minor 2, Access to leds depending on kernelconfig 22 * 23 * For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3): 24 * /dev/gpioa minor 0, 32 bit GPIO, each bit can change direction 25 * /dev/gpiob minor 1, 32 bit GPIO, each bit can change direction 26 * /dev/gpioc minor 3, 16 bit GPIO, each bit can change direction 27 * /dev/gpiod minor 4, 32 bit GPIO, input only 28 * /dev/leds minor 2, Access to leds depending on kernelconfig 29 * /dev/pwm0 minor 16, PWM channel 0 on PA30 30 * /dev/pwm1 minor 17, PWM channel 1 on PA31 31 * /dev/pwm2 minor 18, PWM channel 2 on PB26 32 * /dev/ppwm minor 19, PPWM channel 33 * 34 */ 35#ifndef _ASM_ETRAXGPIO_H 36#define _ASM_ETRAXGPIO_H 37 38#define GPIO_MINOR_FIRST 0 39 40#define ETRAXGPIO_IOCTYPE 43 41 42/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */ 43#ifdef CONFIG_ETRAX_ARCH_V10 44#define GPIO_MINOR_A 0 45#define GPIO_MINOR_B 1 46#define GPIO_MINOR_LEDS 2 47#define GPIO_MINOR_G 3 48#define GPIO_MINOR_LAST 3 49#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST 50#endif 51 52#ifdef CONFIG_ETRAXFS 53#define GPIO_MINOR_A 0 54#define GPIO_MINOR_B 1 55#define GPIO_MINOR_LEDS 2 56#define GPIO_MINOR_C 3 57#define GPIO_MINOR_D 4 58#define GPIO_MINOR_E 5 59#ifdef CONFIG_ETRAX_VIRTUAL_GPIO 60#define GPIO_MINOR_V 6 61#define GPIO_MINOR_LAST 6 62#else 63#define GPIO_MINOR_LAST 5 64#endif 65#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST 66#endif 67 68#ifdef CONFIG_CRIS_MACH_ARTPEC3 69#define GPIO_MINOR_A 0 70#define GPIO_MINOR_B 1 71#define GPIO_MINOR_LEDS 2 72#define GPIO_MINOR_C 3 73#define GPIO_MINOR_D 4 74#ifdef CONFIG_ETRAX_VIRTUAL_GPIO 75#define GPIO_MINOR_V 6 76#define GPIO_MINOR_LAST 6 77#else 78#define GPIO_MINOR_LAST 4 79#endif 80#define GPIO_MINOR_FIRST_PWM 16 81#define GPIO_MINOR_PWM0 (GPIO_MINOR_FIRST_PWM+0) 82#define GPIO_MINOR_PWM1 (GPIO_MINOR_FIRST_PWM+1) 83#define GPIO_MINOR_PWM2 (GPIO_MINOR_FIRST_PWM+2) 84#define GPIO_MINOR_PPWM (GPIO_MINOR_FIRST_PWM+3) 85#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PPWM 86#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST_PWM 87#endif 88 89 90 91/* supported ioctl _IOC_NR's */ 92 93#define IO_READBITS 0x1 /* read and return current port bits (obsolete) */ 94#define IO_SETBITS 0x2 /* set the bits marked by 1 in the argument */ 95#define IO_CLRBITS 0x3 /* clear the bits marked by 1 in the argument */ 96 97/* the alarm is waited for by select() */ 98 99#define IO_HIGHALARM 0x4 /* set alarm on high for bits marked by 1 */ 100#define IO_LOWALARM 0x5 /* set alarm on low for bits marked by 1 */ 101#define IO_CLRALARM 0x6 /* clear alarm for bits marked by 1 */ 102 103/* LED ioctl */ 104#define IO_LEDACTIVE_SET 0x7 /* set active led 105 * 0=off, 1=green, 2=red, 3=yellow */ 106 107/* GPIO direction ioctl's */ 108#define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */ 109#define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input, 110 returns mask with current inputs (obsolete) */ 111#define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output, 112 returns mask with current outputs (obsolete)*/ 113 114/* LED ioctl extended */ 115#define IO_LED_SETBIT 0xB 116#define IO_LED_CLRBIT 0xC 117 118/* SHUTDOWN ioctl */ 119#define IO_SHUTDOWN 0xD 120#define IO_GET_PWR_BT 0xE 121 122/* Bit toggling in driver settings */ 123/* bit set in low byte0 is CLK mask (0x00FF), 124 bit set in byte1 is DATA mask (0xFF00) 125 msb, data_mask[7:0] , clk_mask[7:0] 126 */ 127#define IO_CFG_WRITE_MODE 0xF 128#define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \ 129 ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) ) 130 131/* The following 4 ioctl's take a pointer as argument and handles 132 * 32 bit ports (port G) properly. 133 * These replaces IO_READBITS,IO_SETINPUT AND IO_SETOUTPUT 134 */ 135#define IO_READ_INBITS 0x10 /* *arg is result of reading the input pins */ 136#define IO_READ_OUTBITS 0x11 /* *arg is result of reading the output shadow */ 137#define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input, */ 138 /* *arg updated with current input pins. */ 139#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, */ 140 /* *arg updated with current output pins. */ 141 142/* The following ioctl's are applicable to the PWM channels only */ 143 144#define IO_PWM_SET_MODE 0x20 145 146enum io_pwm_mode { 147 PWM_OFF = 0, /* disabled, deallocated */ 148 PWM_STANDARD = 1, /* 390 kHz, duty cycle 0..255/256 */ 149 PWM_FAST = 2, /* variable freq, w/ 10ns active pulse len */ 150 PWM_VARFREQ = 3, /* individually configurable high/low periods */ 151 PWM_SOFT = 4 /* software generated */ 152}; 153 154struct io_pwm_set_mode { 155 enum io_pwm_mode mode; 156}; 157 158/* Only for mode PWM_VARFREQ. Period lo/high set in increments of 10ns 159 * from 10ns (value = 0) to 81920ns (value = 8191) 160 * (Resulting frequencies range from 50 MHz (10ns + 10ns) down to 161 * 6.1 kHz (81920ns + 81920ns) at 50% duty cycle, to 12.2 kHz at min/max duty 162 * cycle (81920 + 10ns or 10ns + 81920ns, respectively).) 163 */ 164#define IO_PWM_SET_PERIOD 0x21 165 166struct io_pwm_set_period { 167 unsigned int lo; /* 0..8191 */ 168 unsigned int hi; /* 0..8191 */ 169}; 170 171/* Only for modes PWM_STANDARD and PWM_FAST. 172 * For PWM_STANDARD, set duty cycle of 390 kHz PWM output signal, from 173 * 0 (value = 0) to 255/256 (value = 255). 174 * For PWM_FAST, set duty cycle of PWM output signal from 175 * 0% (value = 0) to 100% (value = 255). Output signal in this mode 176 * is a 10ns pulse surrounded by a high or low level depending on duty 177 * cycle (except for 0% and 100% which result in a constant output). 178 * Resulting output frequency varies from 50 MHz at 50% duty cycle, 179 * down to 390 kHz at min/max duty cycle. 180 */ 181#define IO_PWM_SET_DUTY 0x22 182 183struct io_pwm_set_duty { 184 int duty; /* 0..255 */ 185}; 186 187/* Returns information about the latest PWM pulse. 188 * lo: Length of the latest low period, in units of 10ns. 189 * hi: Length of the latest high period, in units of 10ns. 190 * cnt: Time since last detected edge, in units of 10ns. 191 * 192 * The input source to PWM is decied by IO_PWM_SET_INPUT_SRC. 193 * 194 * NOTE: All PWM devices is connected to the same input source. 195 */ 196#define IO_PWM_GET_PERIOD 0x23 197 198struct io_pwm_get_period { 199 unsigned int lo; 200 unsigned int hi; 201 unsigned int cnt; 202}; 203 204/* Sets the input source for the PWM input. For the src value see the 205 * register description for gio:rw_pwm_in_cfg. 206 * 207 * NOTE: All PWM devices is connected to the same input source. 208 */ 209#define IO_PWM_SET_INPUT_SRC 0x24 210struct io_pwm_set_input_src { 211 unsigned int src; /* 0..7 */ 212}; 213 214/* Sets the duty cycles in steps of 1/256, 0 = 0%, 255 = 100% duty cycle */ 215#define IO_PPWM_SET_DUTY 0x25 216 217struct io_ppwm_set_duty { 218 int duty; /* 0..255 */ 219}; 220 221/* Configuraton struct for the IO_PWMCLK_SET_CONFIG ioctl to configure 222 * PWM capable gpio pins: 223 */ 224#define IO_PWMCLK_SETGET_CONFIG 0x26 225struct gpio_pwmclk_conf { 226 unsigned int gpiopin; /* The pin number based on the opened device */ 227 unsigned int baseclk; /* The base clock to use, or sw will select one close*/ 228 unsigned int low; /* The number of low periods of the baseclk */ 229 unsigned int high; /* The number of high periods of the baseclk */ 230}; 231 232/* Examples: 233 * To get a symmetric 12 MHz clock without knowing anything about the hardware: 234 * baseclk = 12000000, low = 0, high = 0 235 * To just get info of current setting: 236 * baseclk = 0, low = 0, high = 0, the values will be updated by driver. 237 */ 238 239#endif 240