1/* 2 * DO NOT EDIT THIS FILE 3 * This file is under version control at 4 * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ 5 * and can be replaced with that version at any time 6 * DO NOT EDIT THIS FILE 7 * 8 * Copyright 2004-2010 Analog Devices Inc. 9 * Licensed under the ADI BSD license. 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 11 */ 12 13/* This file should be up to date with: 14 * - Revision E, 01/26/2010; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List 15 */ 16 17/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */ 18#if __SILICON_REVISION__ < 0 19# error will not work on BF518 silicon version 20#endif 21 22#ifndef _MACH_ANOMALY_H_ 23#define _MACH_ANOMALY_H_ 24 25/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ 26#define ANOMALY_05000074 (1) 27/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ 28#define ANOMALY_05000119 (1) 29/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 30#define ANOMALY_05000122 (1) 31/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 32#define ANOMALY_05000245 (1) 33/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ 34#define ANOMALY_05000254 (1) 35/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 36#define ANOMALY_05000265 (1) 37/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 38#define ANOMALY_05000310 (1) 39/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ 40#define ANOMALY_05000366 (1) 41/* Lockbox SESR Firmware Does Not Save/Restore Full Context */ 42#define ANOMALY_05000405 (1) 43/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ 44#define ANOMALY_05000408 (1) 45/* Speculative Fetches Can Cause Undesired External FIFO Operations */ 46#define ANOMALY_05000416 (1) 47/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */ 48#define ANOMALY_05000421 (1) 49/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */ 50#define ANOMALY_05000422 (1) 51/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ 52#define ANOMALY_05000426 (1) 53/* Software System Reset Corrupts PLL_LOCKCNT Register */ 54#define ANOMALY_05000430 (__SILICON_REVISION__ < 1) 55/* Incorrect Use of Stack in Lockbox Firmware During Authentication */ 56#define ANOMALY_05000431 (1) 57/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */ 58#define ANOMALY_05000434 (1) 59/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ 60#define ANOMALY_05000435 (__SILICON_REVISION__ < 1) 61/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */ 62#define ANOMALY_05000438 (__SILICON_REVISION__ < 1) 63/* Preboot Cannot be Used to Alter the PLL_DIV Register */ 64#define ANOMALY_05000439 (__SILICON_REVISION__ < 1) 65/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ 66#define ANOMALY_05000440 (__SILICON_REVISION__ < 1) 67/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 68#define ANOMALY_05000443 (1) 69/* Incorrect L1 Instruction Bank B Memory Map Location */ 70#define ANOMALY_05000444 (__SILICON_REVISION__ < 1) 71/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ 72#define ANOMALY_05000452 (__SILICON_REVISION__ < 1) 73/* PWM_TRIPB Signal Not Available on PG10 */ 74#define ANOMALY_05000453 (__SILICON_REVISION__ < 1) 75/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */ 76#define ANOMALY_05000455 (__SILICON_REVISION__ < 1) 77/* False Hardware Error when RETI Points to Invalid Memory */ 78#define ANOMALY_05000461 (1) 79/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ 80#define ANOMALY_05000462 (1) 81/* PLL Latches Incorrect Settings During Reset */ 82#define ANOMALY_05000469 (1) 83/* Incorrect Default MSEL Value in PLL_CTL */ 84#define ANOMALY_05000472 (1) 85/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ 86#define ANOMALY_05000473 (1) 87/* TESTSET Instruction Cannot Be Interrupted */ 88#define ANOMALY_05000477 (1) 89/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ 90#define ANOMALY_05000481 (1) 91/* IFLUSH sucks at life */ 92#define ANOMALY_05000491 (1) 93 94/* Anomalies that don't exist on this proc */ 95#define ANOMALY_05000099 (0) 96#define ANOMALY_05000120 (0) 97#define ANOMALY_05000125 (0) 98#define ANOMALY_05000149 (0) 99#define ANOMALY_05000158 (0) 100#define ANOMALY_05000171 (0) 101#define ANOMALY_05000179 (0) 102#define ANOMALY_05000182 (0) 103#define ANOMALY_05000183 (0) 104#define ANOMALY_05000189 (0) 105#define ANOMALY_05000198 (0) 106#define ANOMALY_05000202 (0) 107#define ANOMALY_05000215 (0) 108#define ANOMALY_05000219 (0) 109#define ANOMALY_05000220 (0) 110#define ANOMALY_05000227 (0) 111#define ANOMALY_05000230 (0) 112#define ANOMALY_05000231 (0) 113#define ANOMALY_05000233 (0) 114#define ANOMALY_05000234 (0) 115#define ANOMALY_05000242 (0) 116#define ANOMALY_05000244 (0) 117#define ANOMALY_05000248 (0) 118#define ANOMALY_05000250 (0) 119#define ANOMALY_05000257 (0) 120#define ANOMALY_05000261 (0) 121#define ANOMALY_05000263 (0) 122#define ANOMALY_05000266 (0) 123#define ANOMALY_05000273 (0) 124#define ANOMALY_05000274 (0) 125#define ANOMALY_05000278 (0) 126#define ANOMALY_05000281 (0) 127#define ANOMALY_05000283 (0) 128#define ANOMALY_05000285 (0) 129#define ANOMALY_05000287 (0) 130#define ANOMALY_05000301 (0) 131#define ANOMALY_05000305 (0) 132#define ANOMALY_05000307 (0) 133#define ANOMALY_05000311 (0) 134#define ANOMALY_05000312 (0) 135#define ANOMALY_05000315 (0) 136#define ANOMALY_05000323 (0) 137#define ANOMALY_05000353 (0) 138#define ANOMALY_05000357 (0) 139#define ANOMALY_05000362 (1) 140#define ANOMALY_05000363 (0) 141#define ANOMALY_05000364 (0) 142#define ANOMALY_05000371 (0) 143#define ANOMALY_05000380 (0) 144#define ANOMALY_05000386 (0) 145#define ANOMALY_05000389 (0) 146#define ANOMALY_05000400 (0) 147#define ANOMALY_05000402 (0) 148#define ANOMALY_05000412 (0) 149#define ANOMALY_05000432 (0) 150#define ANOMALY_05000447 (0) 151#define ANOMALY_05000448 (0) 152#define ANOMALY_05000456 (0) 153#define ANOMALY_05000450 (0) 154#define ANOMALY_05000465 (0) 155#define ANOMALY_05000467 (0) 156#define ANOMALY_05000474 (0) 157#define ANOMALY_05000475 (0) 158#define ANOMALY_05000485 (0) 159 160#endif 161