1/* 2 * linux/arch/arm/mm/proc-arm6,7.S 3 * 4 * Copyright (C) 1997-2000 Russell King 5 * hacked for non-paged-MM by Hyok S. Choi, 2003. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * These are the low level assembler for performing cache and TLB 12 * functions on the ARM610 & ARM710. 13 */ 14#include <linux/linkage.h> 15#include <linux/init.h> 16#include <asm/assembler.h> 17#include <asm/asm-offsets.h> 18#include <asm/hwcap.h> 19#include <asm/pgtable-hwdef.h> 20#include <asm/pgtable.h> 21#include <asm/ptrace.h> 22 23#include "proc-macros.S" 24 25ENTRY(cpu_arm6_dcache_clean_area) 26ENTRY(cpu_arm7_dcache_clean_area) 27 mov pc, lr 28 29/* 30 * Function: arm6_7_data_abort () 31 * 32 * Params : r2 = address of aborted instruction 33 * : sp = pointer to registers 34 * 35 * Purpose : obtain information about current aborted instruction 36 * 37 * Returns : r0 = address of abort 38 * : r1 = FSR 39 */ 40 41ENTRY(cpu_arm7_data_abort) 42 mrc p15, 0, r1, c5, c0, 0 @ get FSR 43 mrc p15, 0, r0, c6, c0, 0 @ get FAR 44 ldr r8, [r2] @ read arm instruction 45 tst r8, #1 << 20 @ L = 0 -> write? 46 orreq r1, r1, #1 << 11 @ yes. 47 and r7, r8, #15 << 24 48 add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine 49 nop 50 51/* 0 */ b .data_unknown 52/* 1 */ mov pc, lr @ swp 53/* 2 */ b .data_unknown 54/* 3 */ b .data_unknown 55/* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m 56/* 5 */ b .data_arm_lateldrpreconst @ ldr rd, [rn, #m] 57/* 6 */ b .data_arm_lateldrpostreg @ ldr rd, [rn], rm 58/* 7 */ b .data_arm_lateldrprereg @ ldr rd, [rn, rm] 59/* 8 */ b .data_arm_ldmstm @ ldm*a rn, <rlist> 60/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist> 61/* a */ b .data_unknown 62/* b */ b .data_unknown 63/* c */ mov pc, lr @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m 64/* d */ mov pc, lr @ ldc rd, [rn, #m] 65/* e */ b .data_unknown 66/* f */ 67.data_unknown: @ Part of jumptable 68 mov r0, r2 69 mov r1, r8 70 mov r2, sp 71 bl baddataabort 72 b ret_from_exception 73 74ENTRY(cpu_arm6_data_abort) 75 mrc p15, 0, r1, c5, c0, 0 @ get FSR 76 mrc p15, 0, r0, c6, c0, 0 @ get FAR 77 ldr r8, [r2] @ read arm instruction 78 tst r8, #1 << 20 @ L = 0 -> write? 79 orreq r1, r1, #1 << 11 @ yes. 80 and r7, r8, #14 << 24 81 teq r7, #8 << 24 @ was it ldm/stm 82 movne pc, lr 83 84.data_arm_ldmstm: 85 tst r8, #1 << 21 @ check writeback bit 86 moveq pc, lr @ no writeback -> no fixup 87 mov r7, #0x11 88 orr r7, r7, #0x1100 89 and r6, r8, r7 90 and r2, r8, r7, lsl #1 91 add r6, r6, r2, lsr #1 92 and r2, r8, r7, lsl #2 93 add r6, r6, r2, lsr #2 94 and r2, r8, r7, lsl #3 95 add r6, r6, r2, lsr #3 96 add r6, r6, r6, lsr #8 97 add r6, r6, r6, lsr #4 98 and r6, r6, #15 @ r6 = no. of registers to transfer. 99 and r5, r8, #15 << 16 @ Extract 'n' from instruction 100 ldr r7, [sp, r5, lsr #14] @ Get register 'Rn' 101 tst r8, #1 << 23 @ Check U bit 102 subne r7, r7, r6, lsl #2 @ Undo increment 103 addeq r7, r7, r6, lsl #2 @ Undo decrement 104 str r7, [sp, r5, lsr #14] @ Put register 'Rn' 105 mov pc, lr 106 107.data_arm_apply_r6_and_rn: 108 and r5, r8, #15 << 16 @ Extract 'n' from instruction 109 ldr r7, [sp, r5, lsr #14] @ Get register 'Rn' 110 tst r8, #1 << 23 @ Check U bit 111 subne r7, r7, r6 @ Undo incrmenet 112 addeq r7, r7, r6 @ Undo decrement 113 str r7, [sp, r5, lsr #14] @ Put register 'Rn' 114 mov pc, lr 115 116.data_arm_lateldrpreconst: 117 tst r8, #1 << 21 @ check writeback bit 118 moveq pc, lr @ no writeback -> no fixup 119.data_arm_lateldrpostconst: 120 movs r2, r8, lsl #20 @ Get offset 121 moveq pc, lr @ zero -> no fixup 122 and r5, r8, #15 << 16 @ Extract 'n' from instruction 123 ldr r7, [sp, r5, lsr #14] @ Get register 'Rn' 124 tst r8, #1 << 23 @ Check U bit 125 subne r7, r7, r2, lsr #20 @ Undo increment 126 addeq r7, r7, r2, lsr #20 @ Undo decrement 127 str r7, [sp, r5, lsr #14] @ Put register 'Rn' 128 mov pc, lr 129 130.data_arm_lateldrprereg: 131 tst r8, #1 << 21 @ check writeback bit 132 moveq pc, lr @ no writeback -> no fixup 133.data_arm_lateldrpostreg: 134 and r7, r8, #15 @ Extract 'm' from instruction 135 ldr r6, [sp, r7, lsl #2] @ Get register 'Rm' 136 mov r5, r8, lsr #7 @ get shift count 137 ands r5, r5, #31 138 and r7, r8, #0x70 @ get shift type 139 orreq r7, r7, #8 @ shift count = 0 140 add pc, pc, r7 141 nop 142 143 mov r6, r6, lsl r5 @ 0: LSL #!0 144 b .data_arm_apply_r6_and_rn 145 b .data_arm_apply_r6_and_rn @ 1: LSL #0 146 nop 147 b .data_unknown @ 2: MUL? 148 nop 149 b .data_unknown @ 3: MUL? 150 nop 151 mov r6, r6, lsr r5 @ 4: LSR #!0 152 b .data_arm_apply_r6_and_rn 153 mov r6, r6, lsr #32 @ 5: LSR #32 154 b .data_arm_apply_r6_and_rn 155 b .data_unknown @ 6: MUL? 156 nop 157 b .data_unknown @ 7: MUL? 158 nop 159 mov r6, r6, asr r5 @ 8: ASR #!0 160 b .data_arm_apply_r6_and_rn 161 mov r6, r6, asr #32 @ 9: ASR #32 162 b .data_arm_apply_r6_and_rn 163 b .data_unknown @ A: MUL? 164 nop 165 b .data_unknown @ B: MUL? 166 nop 167 mov r6, r6, ror r5 @ C: ROR #!0 168 b .data_arm_apply_r6_and_rn 169 mov r6, r6, rrx @ D: RRX 170 b .data_arm_apply_r6_and_rn 171 b .data_unknown @ E: MUL? 172 nop 173 b .data_unknown @ F: MUL? 174 175/* 176 * Function: arm6_7_proc_init (void) 177 * : arm6_7_proc_fin (void) 178 * 179 * Notes : This processor does not require these 180 */ 181ENTRY(cpu_arm6_proc_init) 182ENTRY(cpu_arm7_proc_init) 183 mov pc, lr 184 185ENTRY(cpu_arm6_proc_fin) 186ENTRY(cpu_arm7_proc_fin) 187 mov r0, #0x31 @ ....S..DP...M 188 mcr p15, 0, r0, c1, c0, 0 @ disable caches 189 mov pc, lr 190 191ENTRY(cpu_arm6_do_idle) 192ENTRY(cpu_arm7_do_idle) 193 mov pc, lr 194 195/* 196 * Function: arm6_7_switch_mm(unsigned long pgd_phys) 197 * Params : pgd_phys Physical address of page table 198 * Purpose : Perform a task switch, saving the old processes state, and restoring 199 * the new. 200 */ 201ENTRY(cpu_arm6_switch_mm) 202ENTRY(cpu_arm7_switch_mm) 203#ifdef CONFIG_MMU 204 mov r1, #0 205 mcr p15, 0, r1, c7, c0, 0 @ flush cache 206 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr 207 mcr p15, 0, r1, c5, c0, 0 @ flush TLBs 208#endif 209 mov pc, lr 210 211/* 212 * Function: arm6_7_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext) 213 * Params : r0 = Address to set 214 * : r1 = value to set 215 * Purpose : Set a PTE and flush it out of any WB cache 216 */ 217 .align 5 218ENTRY(cpu_arm6_set_pte_ext) 219ENTRY(cpu_arm7_set_pte_ext) 220#ifdef CONFIG_MMU 221 armv3_set_pte_ext wc_disable=0 222#endif /* CONFIG_MMU */ 223 mov pc, lr 224 225/* 226 * Function: _arm6_7_reset 227 * Params : r0 = address to jump to 228 * Notes : This sets up everything for a reset 229 */ 230ENTRY(cpu_arm6_reset) 231ENTRY(cpu_arm7_reset) 232 mov r1, #0 233 mcr p15, 0, r1, c7, c0, 0 @ flush cache 234#ifdef CONFIG_MMU 235 mcr p15, 0, r1, c5, c0, 0 @ flush TLB 236#endif 237 mov r1, #0x30 238 mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc 239 mov pc, r0 240 241 __INIT 242 243 .type __arm6_setup, #function 244__arm6_setup: mov r0, #0 245 mcr p15, 0, r0, c7, c0 @ flush caches on v3 246#ifdef CONFIG_MMU 247 mcr p15, 0, r0, c5, c0 @ flush TLBs on v3 248 mov r0, #0x3d @ . ..RS BLDP WCAM 249 orr r0, r0, #0x100 @ . ..01 0011 1101 250#else 251 mov r0, #0x3c @ . ..RS BLDP WCA. 252#endif 253 mov pc, lr 254 .size __arm6_setup, . - __arm6_setup 255 256 .type __arm7_setup, #function 257__arm7_setup: mov r0, #0 258 mcr p15, 0, r0, c7, c0 @ flush caches on v3 259#ifdef CONFIG_MMU 260 mcr p15, 0, r0, c5, c0 @ flush TLBs on v3 261 mcr p15, 0, r0, c3, c0 @ load domain access register 262 mov r0, #0x7d @ . ..RS BLDP WCAM 263 orr r0, r0, #0x100 @ . ..01 0111 1101 264#else 265 mov r0, #0x7c @ . ..RS BLDP WCA. 266#endif 267 mov pc, lr 268 .size __arm7_setup, . - __arm7_setup 269 270 __INITDATA 271 272/* 273 * Purpose : Function pointers used to access above functions - all calls 274 * come through these 275 */ 276 .type arm6_processor_functions, #object 277ENTRY(arm6_processor_functions) 278 .word cpu_arm6_data_abort 279 .word legacy_pabort 280 .word cpu_arm6_proc_init 281 .word cpu_arm6_proc_fin 282 .word cpu_arm6_reset 283 .word cpu_arm6_do_idle 284 .word cpu_arm6_dcache_clean_area 285 .word cpu_arm6_switch_mm 286 .word cpu_arm6_set_pte_ext 287 .size arm6_processor_functions, . - arm6_processor_functions 288 289/* 290 * Purpose : Function pointers used to access above functions - all calls 291 * come through these 292 */ 293 .type arm7_processor_functions, #object 294ENTRY(arm7_processor_functions) 295 .word cpu_arm7_data_abort 296 .word legacy_pabort 297 .word cpu_arm7_proc_init 298 .word cpu_arm7_proc_fin 299 .word cpu_arm7_reset 300 .word cpu_arm7_do_idle 301 .word cpu_arm7_dcache_clean_area 302 .word cpu_arm7_switch_mm 303 .word cpu_arm7_set_pte_ext 304 .size arm7_processor_functions, . - arm7_processor_functions 305 306 .section ".rodata" 307 308 .type cpu_arch_name, #object 309cpu_arch_name: .asciz "armv3" 310 .size cpu_arch_name, . - cpu_arch_name 311 312 .type cpu_elf_name, #object 313cpu_elf_name: .asciz "v3" 314 .size cpu_elf_name, . - cpu_elf_name 315 316 .type cpu_arm6_name, #object 317cpu_arm6_name: .asciz "ARM6" 318 .size cpu_arm6_name, . - cpu_arm6_name 319 320 .type cpu_arm610_name, #object 321cpu_arm610_name: 322 .asciz "ARM610" 323 .size cpu_arm610_name, . - cpu_arm610_name 324 325 .type cpu_arm7_name, #object 326cpu_arm7_name: .asciz "ARM7" 327 .size cpu_arm7_name, . - cpu_arm7_name 328 329 .type cpu_arm710_name, #object 330cpu_arm710_name: 331 .asciz "ARM710" 332 .size cpu_arm710_name, . - cpu_arm710_name 333 334 .align 335 336 .section ".proc.info.init", #alloc, #execinstr 337 338 .type __arm6_proc_info, #object 339__arm6_proc_info: 340 .long 0x41560600 341 .long 0xfffffff0 342 .long 0x00000c1e 343 .long PMD_TYPE_SECT | \ 344 PMD_BIT4 | \ 345 PMD_SECT_AP_WRITE | \ 346 PMD_SECT_AP_READ 347 b __arm6_setup 348 .long cpu_arch_name 349 .long cpu_elf_name 350 .long HWCAP_SWP | HWCAP_26BIT 351 .long cpu_arm6_name 352 .long arm6_processor_functions 353 .long v3_tlb_fns 354 .long v3_user_fns 355 .long v3_cache_fns 356 .size __arm6_proc_info, . - __arm6_proc_info 357 358 .type __arm610_proc_info, #object 359__arm610_proc_info: 360 .long 0x41560610 361 .long 0xfffffff0 362 .long 0x00000c1e 363 .long PMD_TYPE_SECT | \ 364 PMD_BIT4 | \ 365 PMD_SECT_AP_WRITE | \ 366 PMD_SECT_AP_READ 367 b __arm6_setup 368 .long cpu_arch_name 369 .long cpu_elf_name 370 .long HWCAP_SWP | HWCAP_26BIT 371 .long cpu_arm610_name 372 .long arm6_processor_functions 373 .long v3_tlb_fns 374 .long v3_user_fns 375 .long v3_cache_fns 376 .size __arm610_proc_info, . - __arm610_proc_info 377 378 .type __arm7_proc_info, #object 379__arm7_proc_info: 380 .long 0x41007000 381 .long 0xffffff00 382 .long 0x00000c1e 383 .long PMD_TYPE_SECT | \ 384 PMD_BIT4 | \ 385 PMD_SECT_AP_WRITE | \ 386 PMD_SECT_AP_READ 387 b __arm7_setup 388 .long cpu_arch_name 389 .long cpu_elf_name 390 .long HWCAP_SWP | HWCAP_26BIT 391 .long cpu_arm7_name 392 .long arm7_processor_functions 393 .long v3_tlb_fns 394 .long v3_user_fns 395 .long v3_cache_fns 396 .size __arm7_proc_info, . - __arm7_proc_info 397 398 .type __arm710_proc_info, #object 399__arm710_proc_info: 400 .long 0x41007100 401 .long 0xfff8ff00 402 .long PMD_TYPE_SECT | \ 403 PMD_SECT_BUFFERABLE | \ 404 PMD_SECT_CACHEABLE | \ 405 PMD_BIT4 | \ 406 PMD_SECT_AP_WRITE | \ 407 PMD_SECT_AP_READ 408 .long PMD_TYPE_SECT | \ 409 PMD_BIT4 | \ 410 PMD_SECT_AP_WRITE | \ 411 PMD_SECT_AP_READ 412 b __arm7_setup 413 .long cpu_arch_name 414 .long cpu_elf_name 415 .long HWCAP_SWP | HWCAP_26BIT 416 .long cpu_arm710_name 417 .long arm7_processor_functions 418 .long v3_tlb_fns 419 .long v3_user_fns 420 .long v3_cache_fns 421 .size __arm710_proc_info, . - __arm710_proc_info 422