1/* 2 * linux/arch/arm/mach-versatile/pci.c 3 * 4 * (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved. 5 * You can redistribute and/or modify this software under the terms of version 2 6 * of the GNU General Public License as published by the Free Software Foundation. 7 * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED 8 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU 9 * General Public License for more details. 10 * Koninklijke Philips Electronics nor its subsidiaries is obligated to provide any support for this software. 11 * 12 * ARM Versatile PCI driver. 13 * 14 * 14/04/2005 Initial version, colin.king@philips.com 15 * 16 */ 17#include <linux/kernel.h> 18#include <linux/pci.h> 19#include <linux/ioport.h> 20#include <linux/interrupt.h> 21#include <linux/spinlock.h> 22#include <linux/init.h> 23#include <linux/io.h> 24 25#include <mach/hardware.h> 26#include <asm/irq.h> 27#include <asm/system.h> 28#include <asm/mach/pci.h> 29 30/* 31 * these spaces are mapped using the following base registers: 32 * 33 * Usage Local Bus Memory Base/Map registers used 34 * 35 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0, non prefetch 36 * Mem 60000000 - 6FFFFFFF LB_BASE1/LB_MAP1, prefetch 37 * IO 44000000 - 4FFFFFFF LB_BASE2/LB_MAP2, IO 38 * Cfg 42000000 - 42FFFFFF PCI config 39 * 40 */ 41#define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n)) 42#define SYS_PCICTL __IO_ADDRESS(VERSATILE_SYS_PCICTL) 43#define PCI_IMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0) 44#define PCI_IMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4) 45#define PCI_IMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8) 46#define PCI_SMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x10) 47#define PCI_SMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14) 48#define PCI_SMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18) 49#define PCI_SELFID __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc) 50 51#define DEVICE_ID_OFFSET 0x00 52#define CSR_OFFSET 0x04 53#define CLASS_ID_OFFSET 0x08 54 55#define VP_PCI_DEVICE_ID 0x030010ee 56#define VP_PCI_CLASS_ID 0x0b400000 57 58static unsigned long pci_slot_ignore = 0; 59 60static int __init versatile_pci_slot_ignore(char *str) 61{ 62 int retval; 63 int slot; 64 65 while ((retval = get_option(&str,&slot))) { 66 if ((slot < 0) || (slot > 31)) { 67 printk("Illegal slot value: %d\n",slot); 68 } else { 69 pci_slot_ignore |= (1 << slot); 70 } 71 } 72 return 1; 73} 74 75__setup("pci_slot_ignore=", versatile_pci_slot_ignore); 76 77 78static void __iomem *__pci_addr(struct pci_bus *bus, 79 unsigned int devfn, int offset) 80{ 81 unsigned int busnr = bus->number; 82 83 /* 84 * Trap out illegal values 85 */ 86 if (offset > 255) 87 BUG(); 88 if (busnr > 255) 89 BUG(); 90 if (devfn > 255) 91 BUG(); 92 93 return VERSATILE_PCI_CFG_VIRT_BASE + ((busnr << 16) | 94 (PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | offset); 95} 96 97static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where, 98 int size, u32 *val) 99{ 100 void __iomem *addr = __pci_addr(bus, devfn, where & ~3); 101 u32 v; 102 int slot = PCI_SLOT(devfn); 103 104 if (pci_slot_ignore & (1 << slot)) { 105 /* Ignore this slot */ 106 switch (size) { 107 case 1: 108 v = 0xff; 109 break; 110 case 2: 111 v = 0xffff; 112 break; 113 default: 114 v = 0xffffffff; 115 } 116 } else { 117 switch (size) { 118 case 1: 119 v = __raw_readl(addr); 120 if (where & 2) v >>= 16; 121 if (where & 1) v >>= 8; 122 v &= 0xff; 123 break; 124 125 case 2: 126 v = __raw_readl(addr); 127 if (where & 2) v >>= 16; 128 v &= 0xffff; 129 break; 130 131 default: 132 v = __raw_readl(addr); 133 break; 134 } 135 } 136 137 *val = v; 138 return PCIBIOS_SUCCESSFUL; 139} 140 141static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where, 142 int size, u32 val) 143{ 144 void __iomem *addr = __pci_addr(bus, devfn, where); 145 int slot = PCI_SLOT(devfn); 146 147 if (pci_slot_ignore & (1 << slot)) { 148 return PCIBIOS_SUCCESSFUL; 149 } 150 151 switch (size) { 152 case 1: 153 __raw_writeb((u8)val, addr); 154 break; 155 156 case 2: 157 __raw_writew((u16)val, addr); 158 break; 159 160 case 4: 161 __raw_writel(val, addr); 162 break; 163 } 164 165 return PCIBIOS_SUCCESSFUL; 166} 167 168static struct pci_ops pci_versatile_ops = { 169 .read = versatile_read_config, 170 .write = versatile_write_config, 171}; 172 173static struct resource io_mem = { 174 .name = "PCI I/O space", 175 .start = VERSATILE_PCI_MEM_BASE0, 176 .end = VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1, 177 .flags = IORESOURCE_IO, 178}; 179 180static struct resource non_mem = { 181 .name = "PCI non-prefetchable", 182 .start = VERSATILE_PCI_MEM_BASE1, 183 .end = VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1, 184 .flags = IORESOURCE_MEM, 185}; 186 187static struct resource pre_mem = { 188 .name = "PCI prefetchable", 189 .start = VERSATILE_PCI_MEM_BASE2, 190 .end = VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1, 191 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH, 192}; 193 194static int __init pci_versatile_setup_resources(struct resource **resource) 195{ 196 int ret = 0; 197 198 ret = request_resource(&iomem_resource, &io_mem); 199 if (ret) { 200 printk(KERN_ERR "PCI: unable to allocate I/O " 201 "memory region (%d)\n", ret); 202 goto out; 203 } 204 ret = request_resource(&iomem_resource, &non_mem); 205 if (ret) { 206 printk(KERN_ERR "PCI: unable to allocate non-prefetchable " 207 "memory region (%d)\n", ret); 208 goto release_io_mem; 209 } 210 ret = request_resource(&iomem_resource, &pre_mem); 211 if (ret) { 212 printk(KERN_ERR "PCI: unable to allocate prefetchable " 213 "memory region (%d)\n", ret); 214 goto release_non_mem; 215 } 216 217 /* 218 * bus->resource[0] is the IO resource for this bus 219 * bus->resource[1] is the mem resource for this bus 220 * bus->resource[2] is the prefetch mem resource for this bus 221 */ 222 resource[0] = &io_mem; 223 resource[1] = &non_mem; 224 resource[2] = &pre_mem; 225 226 goto out; 227 228 release_non_mem: 229 release_resource(&non_mem); 230 release_io_mem: 231 release_resource(&io_mem); 232 out: 233 return ret; 234} 235 236int __init pci_versatile_setup(int nr, struct pci_sys_data *sys) 237{ 238 int ret = 0; 239 int i; 240 int myslot = -1; 241 unsigned long val; 242 void __iomem *local_pci_cfg_base; 243 244 val = __raw_readl(SYS_PCICTL); 245 if (!(val & 1)) { 246 printk("Not plugged into PCI backplane!\n"); 247 ret = -EIO; 248 goto out; 249 } 250 251 if (nr == 0) { 252 sys->mem_offset = 0; 253 ret = pci_versatile_setup_resources(sys->resource); 254 if (ret < 0) { 255 printk("pci_versatile_setup: resources... oops?\n"); 256 goto out; 257 } 258 } else { 259 printk("pci_versatile_setup: resources... nr == 0??\n"); 260 goto out; 261 } 262 263 /* 264 * We need to discover the PCI core first to configure itself 265 * before the main PCI probing is performed 266 */ 267 for (i=0; i<32; i++) 268 if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) && 269 (__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) { 270 myslot = i; 271 break; 272 } 273 274 if (myslot == -1) { 275 printk("Cannot find PCI core!\n"); 276 ret = -EIO; 277 goto out; 278 } 279 280 printk("PCI core found (slot %d)\n",myslot); 281 282 __raw_writel(myslot, PCI_SELFID); 283 local_pci_cfg_base = VERSATILE_PCI_CFG_VIRT_BASE + (myslot << 11); 284 285 val = __raw_readl(local_pci_cfg_base + CSR_OFFSET); 286 val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE; 287 __raw_writel(val, local_pci_cfg_base + CSR_OFFSET); 288 289 /* 290 * Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM 291 */ 292 __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0); 293 __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1); 294 __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2); 295 296 /* 297 * Do not to map Versatile FPGA PCI device into memory space 298 */ 299 pci_slot_ignore |= (1 << myslot); 300 ret = 1; 301 302 out: 303 return ret; 304} 305 306 307struct pci_bus * __init pci_versatile_scan_bus(int nr, struct pci_sys_data *sys) 308{ 309 return pci_scan_bus(sys->busnr, &pci_versatile_ops, sys); 310} 311 312void __init pci_versatile_preinit(void) 313{ 314 __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0); 315 __raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1); 316 __raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2); 317 318 __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP0); 319 __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP1); 320 __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP2); 321 322 __raw_writel(1, SYS_PCICTL); 323} 324 325/* 326 * map the specified device/slot/pin to an IRQ. Different backplanes may need to modify this. 327 */ 328static int __init versatile_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 329{ 330 int irq; 331 int devslot = PCI_SLOT(dev->devfn); 332 333 /* slot, pin, irq 334 * 24 1 27 335 * 25 1 28 336 * 26 1 29 337 * 27 1 30 338 */ 339 irq = 27 + ((slot + pin - 1) & 3); 340 341 printk("PCI map irq: slot %d, pin %d, devslot %d, irq: %d\n",slot,pin,devslot,irq); 342 343 return irq; 344} 345 346static struct hw_pci versatile_pci __initdata = { 347 .swizzle = NULL, 348 .map_irq = versatile_map_irq, 349 .nr_controllers = 1, 350 .setup = pci_versatile_setup, 351 .scan = pci_versatile_scan_bus, 352 .preinit = pci_versatile_preinit, 353}; 354 355static int __init versatile_pci_init(void) 356{ 357 pci_common_init(&versatile_pci); 358 return 0; 359} 360 361subsys_initcall(versatile_pci_init); 362