1/* 2 * arch/arm/mach-tegra/include/mach/irqs.h 3 * 4 * Copyright (C) 2010 Google, Inc. 5 * 6 * Author: 7 * Colin Cross <ccross@google.com> 8 * Erik Gilling <konkers@google.com> 9 * 10 * This software is licensed under the terms of the GNU General Public 11 * License version 2, as published by the Free Software Foundation, and 12 * may be copied, distributed, and modified under those terms. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 */ 20 21#ifndef __MACH_TEGRA_IRQS_H 22#define __MACH_TEGRA_IRQS_H 23 24#define INT_GIC_BASE 0 25 26#define IRQ_LOCALTIMER 29 27 28/* Primary Interrupt Controller */ 29#define INT_PRI_BASE (INT_GIC_BASE + 32) 30#define INT_TMR1 (INT_PRI_BASE + 0) 31#define INT_TMR2 (INT_PRI_BASE + 1) 32#define INT_RTC (INT_PRI_BASE + 2) 33#define INT_I2S2 (INT_PRI_BASE + 3) 34#define INT_SHR_SEM_INBOX_IBF (INT_PRI_BASE + 4) 35#define INT_SHR_SEM_INBOX_IBE (INT_PRI_BASE + 5) 36#define INT_SHR_SEM_OUTBOX_IBF (INT_PRI_BASE + 6) 37#define INT_SHR_SEM_OUTBOX_IBE (INT_PRI_BASE + 7) 38#define INT_VDE_UCQ_ERROR (INT_PRI_BASE + 8) 39#define INT_VDE_SYNC_TOKEN (INT_PRI_BASE + 9) 40#define INT_VDE_BSE_V (INT_PRI_BASE + 10) 41#define INT_VDE_BSE_A (INT_PRI_BASE + 11) 42#define INT_VDE_SXE (INT_PRI_BASE + 12) 43#define INT_I2S1 (INT_PRI_BASE + 13) 44#define INT_SDMMC1 (INT_PRI_BASE + 14) 45#define INT_SDMMC2 (INT_PRI_BASE + 15) 46#define INT_XIO (INT_PRI_BASE + 16) 47#define INT_VDE (INT_PRI_BASE + 17) 48#define INT_AVP_UCQ (INT_PRI_BASE + 18) 49#define INT_SDMMC3 (INT_PRI_BASE + 19) 50#define INT_USB (INT_PRI_BASE + 20) 51#define INT_USB2 (INT_PRI_BASE + 21) 52#define INT_PRI_RES_22 (INT_PRI_BASE + 22) 53#define INT_EIDE (INT_PRI_BASE + 23) 54#define INT_NANDFLASH (INT_PRI_BASE + 24) 55#define INT_VCP (INT_PRI_BASE + 25) 56#define INT_APB_DMA (INT_PRI_BASE + 26) 57#define INT_AHB_DMA (INT_PRI_BASE + 27) 58#define INT_GNT_0 (INT_PRI_BASE + 28) 59#define INT_GNT_1 (INT_PRI_BASE + 29) 60#define INT_OWR (INT_PRI_BASE + 30) 61#define INT_SDMMC4 (INT_PRI_BASE + 31) 62 63/* Secondary Interrupt Controller */ 64#define INT_SEC_BASE (INT_PRI_BASE + 32) 65#define INT_GPIO1 (INT_SEC_BASE + 0) 66#define INT_GPIO2 (INT_SEC_BASE + 1) 67#define INT_GPIO3 (INT_SEC_BASE + 2) 68#define INT_GPIO4 (INT_SEC_BASE + 3) 69#define INT_UARTA (INT_SEC_BASE + 4) 70#define INT_UARTB (INT_SEC_BASE + 5) 71#define INT_I2C (INT_SEC_BASE + 6) 72#define INT_SPI (INT_SEC_BASE + 7) 73#define INT_TWC (INT_SEC_BASE + 8) 74#define INT_TMR3 (INT_SEC_BASE + 9) 75#define INT_TMR4 (INT_SEC_BASE + 10) 76#define INT_FLOW_RSM0 (INT_SEC_BASE + 11) 77#define INT_FLOW_RSM1 (INT_SEC_BASE + 12) 78#define INT_SPDIF (INT_SEC_BASE + 13) 79#define INT_UARTC (INT_SEC_BASE + 14) 80#define INT_MIPI (INT_SEC_BASE + 15) 81#define INT_EVENTA (INT_SEC_BASE + 16) 82#define INT_EVENTB (INT_SEC_BASE + 17) 83#define INT_EVENTC (INT_SEC_BASE + 18) 84#define INT_EVENTD (INT_SEC_BASE + 19) 85#define INT_VFIR (INT_SEC_BASE + 20) 86#define INT_DVC (INT_SEC_BASE + 21) 87#define INT_SYS_STATS_MON (INT_SEC_BASE + 22) 88#define INT_GPIO5 (INT_SEC_BASE + 23) 89#define INT_CPU0_PMU_INTR (INT_SEC_BASE + 24) 90#define INT_CPU2_PMU_INTR (INT_SEC_BASE + 25) 91#define INT_SEC_RES_26 (INT_SEC_BASE + 26) 92#define INT_S_LINK1 (INT_SEC_BASE + 27) 93#define INT_APB_DMA_COP (INT_SEC_BASE + 28) 94#define INT_AHB_DMA_COP (INT_SEC_BASE + 29) 95#define INT_DMA_TX (INT_SEC_BASE + 30) 96#define INT_DMA_RX (INT_SEC_BASE + 31) 97 98/* Tertiary Interrupt Controller */ 99#define INT_TRI_BASE (INT_SEC_BASE + 32) 100#define INT_HOST1X_COP_SYNCPT (INT_TRI_BASE + 0) 101#define INT_HOST1X_MPCORE_SYNCPT (INT_TRI_BASE + 1) 102#define INT_HOST1X_COP_GENERAL (INT_TRI_BASE + 2) 103#define INT_HOST1X_MPCORE_GENERAL (INT_TRI_BASE + 3) 104#define INT_MPE_GENERAL (INT_TRI_BASE + 4) 105#define INT_VI_GENERAL (INT_TRI_BASE + 5) 106#define INT_EPP_GENERAL (INT_TRI_BASE + 6) 107#define INT_ISP_GENERAL (INT_TRI_BASE + 7) 108#define INT_2D_GENERAL (INT_TRI_BASE + 8) 109#define INT_DISPLAY_GENERAL (INT_TRI_BASE + 9) 110#define INT_DISPLAY_B_GENERAL (INT_TRI_BASE + 10) 111#define INT_HDMI (INT_TRI_BASE + 11) 112#define INT_TVO_GENERAL (INT_TRI_BASE + 12) 113#define INT_MC_GENERAL (INT_TRI_BASE + 13) 114#define INT_EMC_GENERAL (INT_TRI_BASE + 14) 115#define INT_TRI_RES_15 (INT_TRI_BASE + 15) 116#define INT_TRI_RES_16 (INT_TRI_BASE + 16) 117#define INT_AC97 (INT_TRI_BASE + 17) 118#define INT_SPI_2 (INT_TRI_BASE + 18) 119#define INT_SPI_3 (INT_TRI_BASE + 19) 120#define INT_I2C2 (INT_TRI_BASE + 20) 121#define INT_KBC (INT_TRI_BASE + 21) 122#define INT_EXTERNAL_PMU (INT_TRI_BASE + 22) 123#define INT_GPIO6 (INT_TRI_BASE + 23) 124#define INT_TVDAC (INT_TRI_BASE + 24) 125#define INT_GPIO7 (INT_TRI_BASE + 25) 126#define INT_UARTD (INT_TRI_BASE + 26) 127#define INT_UARTE (INT_TRI_BASE + 27) 128#define INT_I2C3 (INT_TRI_BASE + 28) 129#define INT_SPI_4 (INT_TRI_BASE + 29) 130#define INT_TRI_RES_30 (INT_TRI_BASE + 30) 131#define INT_SW_RESERVED (INT_TRI_BASE + 31) 132 133/* Quaternary Interrupt Controller */ 134#define INT_QUAD_BASE (INT_TRI_BASE + 32) 135#define INT_SNOR (INT_QUAD_BASE + 0) 136#define INT_USB3 (INT_QUAD_BASE + 1) 137#define INT_PCIE_INTR (INT_QUAD_BASE + 2) 138#define INT_PCIE_MSI (INT_QUAD_BASE + 3) 139#define INT_QUAD_RES_4 (INT_QUAD_BASE + 4) 140#define INT_QUAD_RES_5 (INT_QUAD_BASE + 5) 141#define INT_QUAD_RES_6 (INT_QUAD_BASE + 6) 142#define INT_QUAD_RES_7 (INT_QUAD_BASE + 7) 143#define INT_APB_DMA_CH0 (INT_QUAD_BASE + 8) 144#define INT_APB_DMA_CH1 (INT_QUAD_BASE + 9) 145#define INT_APB_DMA_CH2 (INT_QUAD_BASE + 10) 146#define INT_APB_DMA_CH3 (INT_QUAD_BASE + 11) 147#define INT_APB_DMA_CH4 (INT_QUAD_BASE + 12) 148#define INT_APB_DMA_CH5 (INT_QUAD_BASE + 13) 149#define INT_APB_DMA_CH6 (INT_QUAD_BASE + 14) 150#define INT_APB_DMA_CH7 (INT_QUAD_BASE + 15) 151#define INT_APB_DMA_CH8 (INT_QUAD_BASE + 16) 152#define INT_APB_DMA_CH9 (INT_QUAD_BASE + 17) 153#define INT_APB_DMA_CH10 (INT_QUAD_BASE + 18) 154#define INT_APB_DMA_CH11 (INT_QUAD_BASE + 19) 155#define INT_APB_DMA_CH12 (INT_QUAD_BASE + 20) 156#define INT_APB_DMA_CH13 (INT_QUAD_BASE + 21) 157#define INT_APB_DMA_CH14 (INT_QUAD_BASE + 22) 158#define INT_APB_DMA_CH15 (INT_QUAD_BASE + 23) 159#define INT_QUAD_RES_24 (INT_QUAD_BASE + 24) 160#define INT_QUAD_RES_25 (INT_QUAD_BASE + 25) 161#define INT_QUAD_RES_26 (INT_QUAD_BASE + 26) 162#define INT_QUAD_RES_27 (INT_QUAD_BASE + 27) 163#define INT_QUAD_RES_28 (INT_QUAD_BASE + 28) 164#define INT_QUAD_RES_29 (INT_QUAD_BASE + 29) 165#define INT_QUAD_RES_30 (INT_QUAD_BASE + 30) 166#define INT_QUAD_RES_31 (INT_QUAD_BASE + 31) 167 168#define INT_GPIO_BASE (INT_QUAD_BASE + 32) 169#define INT_GPIO_NR (28 * 8) 170 171#define NR_IRQS (INT_GPIO_BASE + INT_GPIO_NR) 172 173#endif 174