1#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H 2#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H 3 4/* 5 * OMAP3430 Clock Management register bits 6 * 7 * Copyright (C) 2007-2008 Texas Instruments, Inc. 8 * Copyright (C) 2007-2008 Nokia Corporation 9 * 10 * Written by Paul Walmsley 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17#include "cm.h" 18 19/* Bits shared between registers */ 20 21/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ 22#define OMAP3430ES2_EN_MMC3_MASK (1 << 30) 23#define OMAP3430ES2_EN_MMC3_SHIFT 30 24#define OMAP3430_EN_MSPRO_MASK (1 << 23) 25#define OMAP3430_EN_MSPRO_SHIFT 23 26#define OMAP3430_EN_HDQ_MASK (1 << 22) 27#define OMAP3430_EN_HDQ_SHIFT 22 28#define OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5) 29#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 30#define OMAP3430ES1_EN_D2D_MASK (1 << 3) 31#define OMAP3430ES1_EN_D2D_SHIFT 3 32#define OMAP3430_EN_SSI_MASK (1 << 0) 33#define OMAP3430_EN_SSI_SHIFT 0 34 35/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ 36#define OMAP3430ES2_EN_USBTLL_SHIFT 2 37#define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) 38 39/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ 40#define OMAP3430_EN_WDT2_MASK (1 << 5) 41#define OMAP3430_EN_WDT2_SHIFT 5 42 43/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ 44#define OMAP3430_EN_CAM_MASK (1 << 0) 45#define OMAP3430_EN_CAM_SHIFT 0 46 47/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ 48#define OMAP3430_EN_WDT3_MASK (1 << 12) 49#define OMAP3430_EN_WDT3_SHIFT 12 50 51/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ 52#define OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19) 53 54 55/* Bits specific to each register */ 56 57/* CM_FCLKEN_IVA2 */ 58#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) 59#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 60 61/* CM_CLKEN_PLL_IVA2 */ 62#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8 63#define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8) 64#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4 65#define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) 66#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 67#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3) 68#define OMAP3430_EN_IVA2_DPLL_SHIFT 0 69#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) 70 71/* CM_IDLEST_IVA2 */ 72#define OMAP3430_ST_IVA2_MASK (1 << 0) 73 74/* CM_IDLEST_PLL_IVA2 */ 75#define OMAP3430_ST_IVA2_CLK_SHIFT 0 76#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) 77 78/* CM_AUTOIDLE_PLL_IVA2 */ 79#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 80#define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) 81 82/* CM_CLKSEL1_PLL_IVA2 */ 83#define OMAP3430_IVA2_CLK_SRC_SHIFT 19 84#define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19) 85#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 86#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) 87#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 88#define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) 89 90/* CM_CLKSEL2_PLL_IVA2 */ 91#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 92#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 93 94/* CM_CLKSTCTRL_IVA2 */ 95#define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 96#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) 97 98/* CM_CLKSTST_IVA2 */ 99#define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0 100#define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) 101 102/* CM_REVISION specific bits */ 103 104/* CM_SYSCONFIG specific bits */ 105 106/* CM_CLKEN_PLL_MPU */ 107#define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8 108#define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8) 109#define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4 110#define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) 111#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 112#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3) 113#define OMAP3430_EN_MPU_DPLL_SHIFT 0 114#define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) 115 116/* CM_IDLEST_MPU */ 117#define OMAP3430_ST_MPU_MASK (1 << 0) 118 119/* CM_IDLEST_PLL_MPU */ 120#define OMAP3430_ST_MPU_CLK_SHIFT 0 121#define OMAP3430_ST_MPU_CLK_MASK (1 << 0) 122 123/* CM_AUTOIDLE_PLL_MPU */ 124#define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 125#define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) 126 127/* CM_CLKSEL1_PLL_MPU */ 128#define OMAP3430_MPU_CLK_SRC_SHIFT 19 129#define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19) 130#define OMAP3430_MPU_DPLL_MULT_SHIFT 8 131#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) 132#define OMAP3430_MPU_DPLL_DIV_SHIFT 0 133#define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) 134 135/* CM_CLKSEL2_PLL_MPU */ 136#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 137#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 138 139/* CM_CLKSTCTRL_MPU */ 140#define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 141#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) 142 143/* CM_CLKSTST_MPU */ 144#define OMAP3430_CLKACTIVITY_MPU_SHIFT 0 145#define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) 146 147/* CM_FCLKEN1_CORE specific bits */ 148#define OMAP3430_EN_MODEM_MASK (1 << 31) 149#define OMAP3430_EN_MODEM_SHIFT 31 150 151/* CM_ICLKEN1_CORE specific bits */ 152#define OMAP3430_EN_ICR_MASK (1 << 29) 153#define OMAP3430_EN_ICR_SHIFT 29 154#define OMAP3430_EN_AES2_MASK (1 << 28) 155#define OMAP3430_EN_AES2_SHIFT 28 156#define OMAP3430_EN_SHA12_MASK (1 << 27) 157#define OMAP3430_EN_SHA12_SHIFT 27 158#define OMAP3430_EN_DES2_MASK (1 << 26) 159#define OMAP3430_EN_DES2_SHIFT 26 160#define OMAP3430ES1_EN_FAC_MASK (1 << 8) 161#define OMAP3430ES1_EN_FAC_SHIFT 8 162#define OMAP3430_EN_MAILBOXES_MASK (1 << 7) 163#define OMAP3430_EN_MAILBOXES_SHIFT 7 164#define OMAP3430_EN_OMAPCTRL_MASK (1 << 6) 165#define OMAP3430_EN_OMAPCTRL_SHIFT 6 166#define OMAP3430_EN_SAD2D_MASK (1 << 3) 167#define OMAP3430_EN_SAD2D_SHIFT 3 168#define OMAP3430_EN_SDRC_MASK (1 << 1) 169#define OMAP3430_EN_SDRC_SHIFT 1 170 171/* AM35XX specific CM_ICLKEN1_CORE bits */ 172#define AM35XX_EN_IPSS_MASK (1 << 4) 173#define AM35XX_EN_IPSS_SHIFT 4 174#define AM35XX_EN_UART4_MASK (1 << 23) 175#define AM35XX_EN_UART4_SHIFT 23 176 177/* CM_ICLKEN2_CORE */ 178#define OMAP3430_EN_PKA_MASK (1 << 4) 179#define OMAP3430_EN_PKA_SHIFT 4 180#define OMAP3430_EN_AES1_MASK (1 << 3) 181#define OMAP3430_EN_AES1_SHIFT 3 182#define OMAP3430_EN_RNG_MASK (1 << 2) 183#define OMAP3430_EN_RNG_SHIFT 2 184#define OMAP3430_EN_SHA11_MASK (1 << 1) 185#define OMAP3430_EN_SHA11_SHIFT 1 186#define OMAP3430_EN_DES1_MASK (1 << 0) 187#define OMAP3430_EN_DES1_SHIFT 0 188 189/* CM_ICLKEN3_CORE */ 190#define OMAP3430_EN_MAD2D_SHIFT 3 191#define OMAP3430_EN_MAD2D_MASK (1 << 3) 192 193/* CM_FCLKEN3_CORE specific bits */ 194#define OMAP3430ES2_EN_TS_SHIFT 1 195#define OMAP3430ES2_EN_TS_MASK (1 << 1) 196#define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 197#define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) 198 199/* CM_IDLEST1_CORE specific bits */ 200#define OMAP3430ES2_ST_MMC3_SHIFT 30 201#define OMAP3430ES2_ST_MMC3_MASK (1 << 30) 202#define OMAP3430_ST_ICR_SHIFT 29 203#define OMAP3430_ST_ICR_MASK (1 << 29) 204#define OMAP3430_ST_AES2_SHIFT 28 205#define OMAP3430_ST_AES2_MASK (1 << 28) 206#define OMAP3430_ST_SHA12_SHIFT 27 207#define OMAP3430_ST_SHA12_MASK (1 << 27) 208#define OMAP3430_ST_DES2_SHIFT 26 209#define OMAP3430_ST_DES2_MASK (1 << 26) 210#define OMAP3430_ST_MSPRO_SHIFT 23 211#define OMAP3430_ST_MSPRO_MASK (1 << 23) 212#define OMAP3430_ST_HDQ_SHIFT 22 213#define OMAP3430_ST_HDQ_MASK (1 << 22) 214#define OMAP3430ES1_ST_FAC_SHIFT 8 215#define OMAP3430ES1_ST_FAC_MASK (1 << 8) 216#define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 217#define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8) 218#define OMAP3430_ST_MAILBOXES_SHIFT 7 219#define OMAP3430_ST_MAILBOXES_MASK (1 << 7) 220#define OMAP3430_ST_OMAPCTRL_SHIFT 6 221#define OMAP3430_ST_OMAPCTRL_MASK (1 << 6) 222#define OMAP3430_ST_SDMA_SHIFT 2 223#define OMAP3430_ST_SDMA_MASK (1 << 2) 224#define OMAP3430_ST_SDRC_SHIFT 1 225#define OMAP3430_ST_SDRC_MASK (1 << 1) 226#define OMAP3430_ST_SSI_STDBY_SHIFT 0 227#define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) 228 229/* AM35xx specific CM_IDLEST1_CORE bits */ 230#define AM35XX_ST_IPSS_SHIFT 5 231#define AM35XX_ST_IPSS_MASK (1 << 5) 232 233/* CM_IDLEST2_CORE */ 234#define OMAP3430_ST_PKA_SHIFT 4 235#define OMAP3430_ST_PKA_MASK (1 << 4) 236#define OMAP3430_ST_AES1_SHIFT 3 237#define OMAP3430_ST_AES1_MASK (1 << 3) 238#define OMAP3430_ST_RNG_SHIFT 2 239#define OMAP3430_ST_RNG_MASK (1 << 2) 240#define OMAP3430_ST_SHA11_SHIFT 1 241#define OMAP3430_ST_SHA11_MASK (1 << 1) 242#define OMAP3430_ST_DES1_SHIFT 0 243#define OMAP3430_ST_DES1_MASK (1 << 0) 244 245/* CM_IDLEST3_CORE */ 246#define OMAP3430ES2_ST_USBTLL_SHIFT 2 247#define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) 248#define OMAP3430ES2_ST_CPEFUSE_SHIFT 0 249#define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) 250 251/* CM_AUTOIDLE1_CORE */ 252#define OMAP3430_AUTO_MODEM_MASK (1 << 31) 253#define OMAP3430_AUTO_MODEM_SHIFT 31 254#define OMAP3430ES2_AUTO_MMC3_MASK (1 << 30) 255#define OMAP3430ES2_AUTO_MMC3_SHIFT 30 256#define OMAP3430ES2_AUTO_ICR_MASK (1 << 29) 257#define OMAP3430ES2_AUTO_ICR_SHIFT 29 258#define OMAP3430_AUTO_AES2_MASK (1 << 28) 259#define OMAP3430_AUTO_AES2_SHIFT 28 260#define OMAP3430_AUTO_SHA12_MASK (1 << 27) 261#define OMAP3430_AUTO_SHA12_SHIFT 27 262#define OMAP3430_AUTO_DES2_MASK (1 << 26) 263#define OMAP3430_AUTO_DES2_SHIFT 26 264#define OMAP3430_AUTO_MMC2_MASK (1 << 25) 265#define OMAP3430_AUTO_MMC2_SHIFT 25 266#define OMAP3430_AUTO_MMC1_MASK (1 << 24) 267#define OMAP3430_AUTO_MMC1_SHIFT 24 268#define OMAP3430_AUTO_MSPRO_MASK (1 << 23) 269#define OMAP3430_AUTO_MSPRO_SHIFT 23 270#define OMAP3430_AUTO_HDQ_MASK (1 << 22) 271#define OMAP3430_AUTO_HDQ_SHIFT 22 272#define OMAP3430_AUTO_MCSPI4_MASK (1 << 21) 273#define OMAP3430_AUTO_MCSPI4_SHIFT 21 274#define OMAP3430_AUTO_MCSPI3_MASK (1 << 20) 275#define OMAP3430_AUTO_MCSPI3_SHIFT 20 276#define OMAP3430_AUTO_MCSPI2_MASK (1 << 19) 277#define OMAP3430_AUTO_MCSPI2_SHIFT 19 278#define OMAP3430_AUTO_MCSPI1_MASK (1 << 18) 279#define OMAP3430_AUTO_MCSPI1_SHIFT 18 280#define OMAP3430_AUTO_I2C3_MASK (1 << 17) 281#define OMAP3430_AUTO_I2C3_SHIFT 17 282#define OMAP3430_AUTO_I2C2_MASK (1 << 16) 283#define OMAP3430_AUTO_I2C2_SHIFT 16 284#define OMAP3430_AUTO_I2C1_MASK (1 << 15) 285#define OMAP3430_AUTO_I2C1_SHIFT 15 286#define OMAP3430_AUTO_UART2_MASK (1 << 14) 287#define OMAP3430_AUTO_UART2_SHIFT 14 288#define OMAP3430_AUTO_UART1_MASK (1 << 13) 289#define OMAP3430_AUTO_UART1_SHIFT 13 290#define OMAP3430_AUTO_GPT11_MASK (1 << 12) 291#define OMAP3430_AUTO_GPT11_SHIFT 12 292#define OMAP3430_AUTO_GPT10_MASK (1 << 11) 293#define OMAP3430_AUTO_GPT10_SHIFT 11 294#define OMAP3430_AUTO_MCBSP5_MASK (1 << 10) 295#define OMAP3430_AUTO_MCBSP5_SHIFT 10 296#define OMAP3430_AUTO_MCBSP1_MASK (1 << 9) 297#define OMAP3430_AUTO_MCBSP1_SHIFT 9 298#define OMAP3430ES1_AUTO_FAC_MASK (1 << 8) 299#define OMAP3430ES1_AUTO_FAC_SHIFT 8 300#define OMAP3430_AUTO_MAILBOXES_MASK (1 << 7) 301#define OMAP3430_AUTO_MAILBOXES_SHIFT 7 302#define OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6) 303#define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 304#define OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5) 305#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 306#define OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4) 307#define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 308#define OMAP3430ES1_AUTO_D2D_MASK (1 << 3) 309#define OMAP3430ES1_AUTO_D2D_SHIFT 3 310#define OMAP3430_AUTO_SAD2D_MASK (1 << 3) 311#define OMAP3430_AUTO_SAD2D_SHIFT 3 312#define OMAP3430_AUTO_SSI_MASK (1 << 0) 313#define OMAP3430_AUTO_SSI_SHIFT 0 314 315/* CM_AUTOIDLE2_CORE */ 316#define OMAP3430_AUTO_PKA_MASK (1 << 4) 317#define OMAP3430_AUTO_PKA_SHIFT 4 318#define OMAP3430_AUTO_AES1_MASK (1 << 3) 319#define OMAP3430_AUTO_AES1_SHIFT 3 320#define OMAP3430_AUTO_RNG_MASK (1 << 2) 321#define OMAP3430_AUTO_RNG_SHIFT 2 322#define OMAP3430_AUTO_SHA11_MASK (1 << 1) 323#define OMAP3430_AUTO_SHA11_SHIFT 1 324#define OMAP3430_AUTO_DES1_MASK (1 << 0) 325#define OMAP3430_AUTO_DES1_SHIFT 0 326 327/* CM_AUTOIDLE3_CORE */ 328#define OMAP3430ES2_AUTO_USBHOST (1 << 0) 329#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 330#define OMAP3430ES2_AUTO_USBTLL (1 << 2) 331#define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 332#define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) 333#define OMAP3430_AUTO_MAD2D_SHIFT 3 334#define OMAP3430_AUTO_MAD2D_MASK (1 << 3) 335 336/* CM_CLKSEL_CORE */ 337#define OMAP3430_CLKSEL_SSI_SHIFT 8 338#define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) 339#define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) 340#define OMAP3430_CLKSEL_GPT11_SHIFT 7 341#define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) 342#define OMAP3430_CLKSEL_GPT10_SHIFT 6 343#define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4 344#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) 345#define OMAP3430_CLKSEL_L4_SHIFT 2 346#define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) 347#define OMAP3430_CLKSEL_L3_SHIFT 0 348#define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) 349#define OMAP3630_CLKSEL_96M_SHIFT 12 350#define OMAP3630_CLKSEL_96M_MASK (0x3 << 12) 351 352/* CM_CLKSTCTRL_CORE */ 353#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 354#define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) 355#define OMAP3430_CLKTRCTRL_L4_SHIFT 2 356#define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) 357#define OMAP3430_CLKTRCTRL_L3_SHIFT 0 358#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) 359 360/* CM_CLKSTST_CORE */ 361#define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2 362#define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2) 363#define OMAP3430_CLKACTIVITY_L4_SHIFT 1 364#define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1) 365#define OMAP3430_CLKACTIVITY_L3_SHIFT 0 366#define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0) 367 368/* CM_FCLKEN_GFX */ 369#define OMAP3430ES1_EN_3D_MASK (1 << 2) 370#define OMAP3430ES1_EN_3D_SHIFT 2 371#define OMAP3430ES1_EN_2D_MASK (1 << 1) 372#define OMAP3430ES1_EN_2D_SHIFT 1 373 374/* CM_ICLKEN_GFX specific bits */ 375 376/* CM_IDLEST_GFX specific bits */ 377 378/* CM_CLKSEL_GFX specific bits */ 379 380/* CM_SLEEPDEP_GFX specific bits */ 381 382/* CM_CLKSTCTRL_GFX */ 383#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0 384#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) 385 386/* CM_CLKSTST_GFX */ 387#define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0 388#define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) 389 390/* CM_FCLKEN_SGX */ 391#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 392#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) 393 394/* CM_IDLEST_SGX */ 395#define OMAP3430ES2_ST_SGX_SHIFT 1 396#define OMAP3430ES2_ST_SGX_MASK (1 << 1) 397 398/* CM_ICLKEN_SGX */ 399#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 400#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) 401 402/* CM_CLKSEL_SGX */ 403#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 404#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) 405 406/* CM_CLKSTCTRL_SGX */ 407#define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0 408#define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) 409 410/* CM_CLKSTST_SGX */ 411#define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0 412#define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0) 413 414/* CM_FCLKEN_WKUP specific bits */ 415#define OMAP3430ES2_EN_USIMOCP_SHIFT 9 416#define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) 417 418/* CM_ICLKEN_WKUP specific bits */ 419#define OMAP3430_EN_WDT1_MASK (1 << 4) 420#define OMAP3430_EN_WDT1_SHIFT 4 421#define OMAP3430_EN_32KSYNC_MASK (1 << 2) 422#define OMAP3430_EN_32KSYNC_SHIFT 2 423 424/* CM_IDLEST_WKUP specific bits */ 425#define OMAP3430ES2_ST_USIMOCP_SHIFT 9 426#define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9) 427#define OMAP3430_ST_WDT2_SHIFT 5 428#define OMAP3430_ST_WDT2_MASK (1 << 5) 429#define OMAP3430_ST_WDT1_SHIFT 4 430#define OMAP3430_ST_WDT1_MASK (1 << 4) 431#define OMAP3430_ST_32KSYNC_SHIFT 2 432#define OMAP3430_ST_32KSYNC_MASK (1 << 2) 433 434/* CM_AUTOIDLE_WKUP */ 435#define OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9) 436#define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 437#define OMAP3430_AUTO_WDT2_MASK (1 << 5) 438#define OMAP3430_AUTO_WDT2_SHIFT 5 439#define OMAP3430_AUTO_WDT1_MASK (1 << 4) 440#define OMAP3430_AUTO_WDT1_SHIFT 4 441#define OMAP3430_AUTO_GPIO1_MASK (1 << 3) 442#define OMAP3430_AUTO_GPIO1_SHIFT 3 443#define OMAP3430_AUTO_32KSYNC_MASK (1 << 2) 444#define OMAP3430_AUTO_32KSYNC_SHIFT 2 445#define OMAP3430_AUTO_GPT12_MASK (1 << 1) 446#define OMAP3430_AUTO_GPT12_SHIFT 1 447#define OMAP3430_AUTO_GPT1_MASK (1 << 0) 448#define OMAP3430_AUTO_GPT1_SHIFT 0 449 450/* CM_CLKSEL_WKUP */ 451#define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) 452#define OMAP3430_CLKSEL_RM_SHIFT 1 453#define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) 454#define OMAP3430_CLKSEL_GPT1_SHIFT 0 455#define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) 456 457/* CM_CLKEN_PLL */ 458#define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 459#define OMAP3430_PWRDN_CAM_SHIFT 30 460#define OMAP3430_PWRDN_DSS1_SHIFT 29 461#define OMAP3430_PWRDN_TV_SHIFT 28 462#define OMAP3430_PWRDN_96M_SHIFT 27 463#define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24 464#define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24) 465#define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20 466#define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) 467#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 468#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19) 469#define OMAP3430_EN_PERIPH_DPLL_SHIFT 16 470#define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) 471#define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 472#define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8 473#define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8) 474#define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4 475#define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) 476#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 477#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3) 478#define OMAP3430_EN_CORE_DPLL_SHIFT 0 479#define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) 480 481/* CM_CLKEN2_PLL */ 482#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 483#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) 484#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 485#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) 486#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 487#define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0 488#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) 489 490/* CM_IDLEST_CKGEN */ 491#define OMAP3430_ST_54M_CLK_MASK (1 << 5) 492#define OMAP3430_ST_12M_CLK_MASK (1 << 4) 493#define OMAP3430_ST_48M_CLK_MASK (1 << 3) 494#define OMAP3430_ST_96M_CLK_MASK (1 << 2) 495#define OMAP3430_ST_PERIPH_CLK_SHIFT 1 496#define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) 497#define OMAP3430_ST_CORE_CLK_SHIFT 0 498#define OMAP3430_ST_CORE_CLK_MASK (1 << 0) 499 500/* CM_IDLEST2_CKGEN */ 501#define OMAP3430ES2_ST_USIM_CLK_SHIFT 2 502#define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2) 503#define OMAP3430ES2_ST_120M_CLK_SHIFT 1 504#define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) 505#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 506#define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) 507 508/* CM_AUTOIDLE_PLL */ 509#define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3 510#define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) 511#define OMAP3430_AUTO_CORE_DPLL_SHIFT 0 512#define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) 513 514/* CM_AUTOIDLE2_PLL */ 515#define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0 516#define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0) 517 518/* CM_CLKSEL1_PLL */ 519/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ 520#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 521#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) 522#define OMAP3430_CORE_DPLL_MULT_SHIFT 16 523#define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) 524#define OMAP3430_CORE_DPLL_DIV_SHIFT 8 525#define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) 526#define OMAP3430_SOURCE_96M_SHIFT 6 527#define OMAP3430_SOURCE_96M_MASK (1 << 6) 528#define OMAP3430_SOURCE_54M_SHIFT 5 529#define OMAP3430_SOURCE_54M_MASK (1 << 5) 530#define OMAP3430_SOURCE_48M_SHIFT 3 531#define OMAP3430_SOURCE_48M_MASK (1 << 3) 532 533/* CM_CLKSEL2_PLL */ 534#define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 535#define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) 536#define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8) 537#define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 538#define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) 539#define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT 21 540#define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21) 541#define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT 24 542#define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24) 543 544/* CM_CLKSEL3_PLL */ 545#define OMAP3430_DIV_96M_SHIFT 0 546#define OMAP3430_DIV_96M_MASK (0x1f << 0) 547#define OMAP3630_DIV_96M_MASK (0x3f << 0) 548 549/* CM_CLKSEL4_PLL */ 550#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 551#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) 552#define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0 553#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) 554 555/* CM_CLKSEL5_PLL */ 556#define OMAP3430ES2_DIV_120M_SHIFT 0 557#define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) 558 559/* CM_CLKOUT_CTRL */ 560#define OMAP3430_CLKOUT2_EN_SHIFT 7 561#define OMAP3430_CLKOUT2_EN_MASK (1 << 7) 562#define OMAP3430_CLKOUT2_DIV_SHIFT 3 563#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) 564#define OMAP3430_CLKOUT2SOURCE_SHIFT 0 565#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) 566 567/* CM_FCLKEN_DSS */ 568#define OMAP3430_EN_TV_MASK (1 << 2) 569#define OMAP3430_EN_TV_SHIFT 2 570#define OMAP3430_EN_DSS2_MASK (1 << 1) 571#define OMAP3430_EN_DSS2_SHIFT 1 572#define OMAP3430_EN_DSS1_MASK (1 << 0) 573#define OMAP3430_EN_DSS1_SHIFT 0 574 575/* CM_ICLKEN_DSS */ 576#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0) 577#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 578 579/* CM_IDLEST_DSS */ 580#define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 581#define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1) 582#define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 583#define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0) 584#define OMAP3430ES1_ST_DSS_SHIFT 0 585#define OMAP3430ES1_ST_DSS_MASK (1 << 0) 586 587/* CM_AUTOIDLE_DSS */ 588#define OMAP3430_AUTO_DSS_MASK (1 << 0) 589#define OMAP3430_AUTO_DSS_SHIFT 0 590 591/* CM_CLKSEL_DSS */ 592#define OMAP3430_CLKSEL_TV_SHIFT 8 593#define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) 594#define OMAP3630_CLKSEL_TV_MASK (0x3f << 8) 595#define OMAP3430_CLKSEL_DSS1_SHIFT 0 596#define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) 597#define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0) 598 599/* CM_SLEEPDEP_DSS specific bits */ 600 601/* CM_CLKSTCTRL_DSS */ 602#define OMAP3430_CLKTRCTRL_DSS_SHIFT 0 603#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) 604 605/* CM_CLKSTST_DSS */ 606#define OMAP3430_CLKACTIVITY_DSS_SHIFT 0 607#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) 608 609/* CM_FCLKEN_CAM specific bits */ 610#define OMAP3430_EN_CSI2_MASK (1 << 1) 611#define OMAP3430_EN_CSI2_SHIFT 1 612 613/* CM_ICLKEN_CAM specific bits */ 614 615/* CM_IDLEST_CAM */ 616#define OMAP3430_ST_CAM_MASK (1 << 0) 617 618/* CM_AUTOIDLE_CAM */ 619#define OMAP3430_AUTO_CAM_MASK (1 << 0) 620#define OMAP3430_AUTO_CAM_SHIFT 0 621 622/* CM_CLKSEL_CAM */ 623#define OMAP3430_CLKSEL_CAM_SHIFT 0 624#define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) 625#define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0) 626 627/* CM_SLEEPDEP_CAM specific bits */ 628 629/* CM_CLKSTCTRL_CAM */ 630#define OMAP3430_CLKTRCTRL_CAM_SHIFT 0 631#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) 632 633/* CM_CLKSTST_CAM */ 634#define OMAP3430_CLKACTIVITY_CAM_SHIFT 0 635#define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0) 636 637/* CM_FCLKEN_PER specific bits */ 638 639/* CM_ICLKEN_PER specific bits */ 640 641/* CM_IDLEST_PER */ 642#define OMAP3430_ST_WDT3_SHIFT 12 643#define OMAP3430_ST_WDT3_MASK (1 << 12) 644#define OMAP3430_ST_MCBSP4_SHIFT 2 645#define OMAP3430_ST_MCBSP4_MASK (1 << 2) 646#define OMAP3430_ST_MCBSP3_SHIFT 1 647#define OMAP3430_ST_MCBSP3_MASK (1 << 1) 648#define OMAP3430_ST_MCBSP2_SHIFT 0 649#define OMAP3430_ST_MCBSP2_MASK (1 << 0) 650 651/* CM_AUTOIDLE_PER */ 652#define OMAP3430_AUTO_GPIO6_MASK (1 << 17) 653#define OMAP3430_AUTO_GPIO6_SHIFT 17 654#define OMAP3430_AUTO_GPIO5_MASK (1 << 16) 655#define OMAP3430_AUTO_GPIO5_SHIFT 16 656#define OMAP3430_AUTO_GPIO4_MASK (1 << 15) 657#define OMAP3430_AUTO_GPIO4_SHIFT 15 658#define OMAP3430_AUTO_GPIO3_MASK (1 << 14) 659#define OMAP3430_AUTO_GPIO3_SHIFT 14 660#define OMAP3430_AUTO_GPIO2_MASK (1 << 13) 661#define OMAP3430_AUTO_GPIO2_SHIFT 13 662#define OMAP3430_AUTO_WDT3_MASK (1 << 12) 663#define OMAP3430_AUTO_WDT3_SHIFT 12 664#define OMAP3430_AUTO_UART3_MASK (1 << 11) 665#define OMAP3430_AUTO_UART3_SHIFT 11 666#define OMAP3430_AUTO_GPT9_MASK (1 << 10) 667#define OMAP3430_AUTO_GPT9_SHIFT 10 668#define OMAP3430_AUTO_GPT8_MASK (1 << 9) 669#define OMAP3430_AUTO_GPT8_SHIFT 9 670#define OMAP3430_AUTO_GPT7_MASK (1 << 8) 671#define OMAP3430_AUTO_GPT7_SHIFT 8 672#define OMAP3430_AUTO_GPT6_MASK (1 << 7) 673#define OMAP3430_AUTO_GPT6_SHIFT 7 674#define OMAP3430_AUTO_GPT5_MASK (1 << 6) 675#define OMAP3430_AUTO_GPT5_SHIFT 6 676#define OMAP3430_AUTO_GPT4_MASK (1 << 5) 677#define OMAP3430_AUTO_GPT4_SHIFT 5 678#define OMAP3430_AUTO_GPT3_MASK (1 << 4) 679#define OMAP3430_AUTO_GPT3_SHIFT 4 680#define OMAP3430_AUTO_GPT2_MASK (1 << 3) 681#define OMAP3430_AUTO_GPT2_SHIFT 3 682#define OMAP3430_AUTO_MCBSP4_MASK (1 << 2) 683#define OMAP3430_AUTO_MCBSP4_SHIFT 2 684#define OMAP3430_AUTO_MCBSP3_MASK (1 << 1) 685#define OMAP3430_AUTO_MCBSP3_SHIFT 1 686#define OMAP3430_AUTO_MCBSP2_MASK (1 << 0) 687#define OMAP3430_AUTO_MCBSP2_SHIFT 0 688 689/* CM_CLKSEL_PER */ 690#define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) 691#define OMAP3430_CLKSEL_GPT9_SHIFT 7 692#define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) 693#define OMAP3430_CLKSEL_GPT8_SHIFT 6 694#define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) 695#define OMAP3430_CLKSEL_GPT7_SHIFT 5 696#define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) 697#define OMAP3430_CLKSEL_GPT6_SHIFT 4 698#define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) 699#define OMAP3430_CLKSEL_GPT5_SHIFT 3 700#define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) 701#define OMAP3430_CLKSEL_GPT4_SHIFT 2 702#define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) 703#define OMAP3430_CLKSEL_GPT3_SHIFT 1 704#define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) 705#define OMAP3430_CLKSEL_GPT2_SHIFT 0 706 707/* CM_SLEEPDEP_PER specific bits */ 708#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2) 709 710/* CM_CLKSTCTRL_PER */ 711#define OMAP3430_CLKTRCTRL_PER_SHIFT 0 712#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) 713 714/* CM_CLKSTST_PER */ 715#define OMAP3430_CLKACTIVITY_PER_SHIFT 0 716#define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0) 717 718/* CM_CLKSEL1_EMU */ 719#define OMAP3430_DIV_DPLL4_SHIFT 24 720#define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) 721#define OMAP3630_DIV_DPLL4_MASK (0x3f << 24) 722#define OMAP3430_DIV_DPLL3_SHIFT 16 723#define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) 724#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 725#define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) 726#define OMAP3430_CLKSEL_PCLK_SHIFT 8 727#define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) 728#define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 729#define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) 730#define OMAP3430_CLKSEL_ATCLK_SHIFT 4 731#define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) 732#define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 733#define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) 734#define OMAP3430_MUX_CTRL_SHIFT 0 735#define OMAP3430_MUX_CTRL_MASK (0x3 << 0) 736 737/* CM_CLKSTCTRL_EMU */ 738#define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 739#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) 740 741/* CM_CLKSTST_EMU */ 742#define OMAP3430_CLKACTIVITY_EMU_SHIFT 0 743#define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0) 744 745/* CM_CLKSEL2_EMU specific bits */ 746#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 747#define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) 748#define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0 749#define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) 750 751/* CM_CLKSEL3_EMU specific bits */ 752#define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8 753#define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8) 754#define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0 755#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) 756 757/* CM_POLCTRL */ 758#define OMAP3430_CLKOUT2_POL_MASK (1 << 0) 759 760/* CM_IDLEST_NEON */ 761#define OMAP3430_ST_NEON_MASK (1 << 0) 762 763/* CM_CLKSTCTRL_NEON */ 764#define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 765#define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) 766 767/* CM_FCLKEN_USBHOST */ 768#define OMAP3430ES2_EN_USBHOST2_SHIFT 1 769#define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1) 770#define OMAP3430ES2_EN_USBHOST1_SHIFT 0 771#define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0) 772 773/* CM_ICLKEN_USBHOST */ 774#define OMAP3430ES2_EN_USBHOST_SHIFT 0 775#define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) 776 777/* CM_IDLEST_USBHOST */ 778#define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 779#define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1) 780#define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 781#define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0) 782 783/* CM_AUTOIDLE_USBHOST */ 784#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 785#define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0) 786 787/* CM_SLEEPDEP_USBHOST */ 788#define OMAP3430ES2_EN_MPU_SHIFT 1 789#define OMAP3430ES2_EN_MPU_MASK (1 << 1) 790#define OMAP3430ES2_EN_IVA2_SHIFT 2 791#define OMAP3430ES2_EN_IVA2_MASK (1 << 2) 792 793/* CM_CLKSTCTRL_USBHOST */ 794#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 795#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) 796 797/* CM_CLKSTST_USBHOST */ 798#define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0 799#define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0) 800 801#endif 802