1/* 2 * OMAP34xx M2 divider clock code 3 * 4 * Copyright (C) 2007-2008 Texas Instruments, Inc. 5 * Copyright (C) 2007-2010 Nokia Corporation 6 * 7 * Paul Walmsley 8 * Jouni H��gander 9 * 10 * Parts of this code are based on code written by 11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License version 2 as 15 * published by the Free Software Foundation. 16 */ 17#undef DEBUG 18 19#include <linux/kernel.h> 20#include <linux/errno.h> 21#include <linux/clk.h> 22#include <linux/io.h> 23 24#include <plat/clock.h> 25#include <plat/sram.h> 26#include <plat/sdrc.h> 27 28#include "clock.h" 29#include "clock3xxx.h" 30#include "clock34xx.h" 31#include "sdrc.h" 32 33#define CYCLES_PER_MHZ 1000000 34 35/* 36 * CORE DPLL (DPLL3) M2 divider rate programming functions 37 * 38 * These call into SRAM code to do the actual CM writes, since the SDRAM 39 * is clocked from DPLL3. 40 */ 41 42/** 43 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider 44 * @clk: struct clk * of DPLL to set 45 * @rate: rounded target rate 46 * 47 * Program the DPLL M2 divider with the rounded target rate. Returns 48 * -EINVAL upon error, or 0 upon success. 49 */ 50int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) 51{ 52 u32 new_div = 0; 53 u32 unlock_dll = 0; 54 u32 c; 55 unsigned long validrate, sdrcrate, _mpurate; 56 struct omap_sdrc_params *sdrc_cs0; 57 struct omap_sdrc_params *sdrc_cs1; 58 int ret; 59 60 if (!clk || !rate) 61 return -EINVAL; 62 63 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); 64 if (validrate != rate) 65 return -EINVAL; 66 67 sdrcrate = sdrc_ick_p->rate; 68 if (rate > clk->rate) 69 sdrcrate <<= ((rate / clk->rate) >> 1); 70 else 71 sdrcrate >>= ((clk->rate / rate) >> 1); 72 73 ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1); 74 if (ret) 75 return -EINVAL; 76 77 if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) { 78 pr_debug("clock: will unlock SDRC DLL\n"); 79 unlock_dll = 1; 80 } 81 82 _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ; 83 c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; 84 c += 1; /* for safety */ 85 c *= SDRC_MPURATE_LOOPS; 86 c >>= SDRC_MPURATE_SCALE; 87 if (c == 0) 88 c = 1; 89 90 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, 91 validrate); 92 pr_debug("clock: SDRC CS0 timing params used:" 93 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", 94 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, 95 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr); 96 if (sdrc_cs1) 97 pr_debug("clock: SDRC CS1 timing params used: " 98 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", 99 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, 100 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); 101 102 if (sdrc_cs1) 103 omap3_configure_core_dpll( 104 new_div, unlock_dll, c, rate > clk->rate, 105 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, 106 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, 107 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, 108 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); 109 else 110 omap3_configure_core_dpll( 111 new_div, unlock_dll, c, rate > clk->rate, 112 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, 113 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, 114 0, 0, 0, 0); 115 116 return 0; 117} 118