1/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. 2 * 3 * Redistribution and use in source and binary forms, with or without 4 * modification, are permitted provided that the following conditions are 5 * met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above 9 * copyright notice, this list of conditions and the following 10 * disclaimer in the documentation and/or other materials provided 11 * with the distribution. 12 * * Neither the name of Code Aurora Forum, Inc. nor the names of its 13 * contributors may be used to endorse or promote products derived 14 * from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30#ifndef __ASM_ARCH_MSM_SIRC_H 31#define __ASM_ARCH_MSM_SIRC_H 32 33struct sirc_regs_t { 34 void *int_enable; 35 void *int_enable_clear; 36 void *int_enable_set; 37 void *int_type; 38 void *int_polarity; 39 void *int_clear; 40}; 41 42struct sirc_cascade_regs { 43 void *int_status; 44 unsigned int cascade_irq; 45}; 46 47void msm_init_sirc(void); 48void msm_sirc_enter_sleep(void); 49void msm_sirc_exit_sleep(void); 50 51#if defined(CONFIG_ARCH_MSM_SCORPION) 52 53#include <mach/msm_iomap.h> 54 55/* 56 * Secondary interrupt controller interrupts 57 */ 58 59#define FIRST_SIRC_IRQ (NR_MSM_IRQS + NR_GPIO_IRQS) 60 61#define INT_UART1 (FIRST_SIRC_IRQ + 0) 62#define INT_UART2 (FIRST_SIRC_IRQ + 1) 63#define INT_UART3 (FIRST_SIRC_IRQ + 2) 64#define INT_UART1_RX (FIRST_SIRC_IRQ + 3) 65#define INT_UART2_RX (FIRST_SIRC_IRQ + 4) 66#define INT_UART3_RX (FIRST_SIRC_IRQ + 5) 67#define INT_SPI_INPUT (FIRST_SIRC_IRQ + 6) 68#define INT_SPI_OUTPUT (FIRST_SIRC_IRQ + 7) 69#define INT_SPI_ERROR (FIRST_SIRC_IRQ + 8) 70#define INT_GPIO_GROUP1 (FIRST_SIRC_IRQ + 9) 71#define INT_GPIO_GROUP2 (FIRST_SIRC_IRQ + 10) 72#define INT_GPIO_GROUP1_SECURE (FIRST_SIRC_IRQ + 11) 73#define INT_GPIO_GROUP2_SECURE (FIRST_SIRC_IRQ + 12) 74#define INT_AVS_SVIC (FIRST_SIRC_IRQ + 13) 75#define INT_AVS_REQ_UP (FIRST_SIRC_IRQ + 14) 76#define INT_AVS_REQ_DOWN (FIRST_SIRC_IRQ + 15) 77#define INT_PBUS_ERR (FIRST_SIRC_IRQ + 16) 78#define INT_AXI_ERR (FIRST_SIRC_IRQ + 17) 79#define INT_SMI_ERR (FIRST_SIRC_IRQ + 18) 80#define INT_EBI1_ERR (FIRST_SIRC_IRQ + 19) 81#define INT_IMEM_ERR (FIRST_SIRC_IRQ + 20) 82#define INT_TEMP_SENSOR (FIRST_SIRC_IRQ + 21) 83#define INT_TV_ENC (FIRST_SIRC_IRQ + 22) 84#define INT_GRP2D (FIRST_SIRC_IRQ + 23) 85#define INT_GSBI_QUP (FIRST_SIRC_IRQ + 24) 86#define INT_SC_ACG (FIRST_SIRC_IRQ + 25) 87#define INT_WDT0 (FIRST_SIRC_IRQ + 26) 88#define INT_WDT1 (FIRST_SIRC_IRQ + 27) 89 90#if defined(CONFIG_MSM_SOC_REV_A) 91#define NR_SIRC_IRQS 28 92#define SIRC_MASK 0x0FFFFFFF 93#else 94#define NR_SIRC_IRQS 23 95#define SIRC_MASK 0x007FFFFF 96#endif 97 98#define LAST_SIRC_IRQ (FIRST_SIRC_IRQ + NR_SIRC_IRQS - 1) 99 100#define SPSS_SIRC_INT_SELECT (MSM_SIRC_BASE + 0x00) 101#define SPSS_SIRC_INT_ENABLE (MSM_SIRC_BASE + 0x04) 102#define SPSS_SIRC_INT_ENABLE_CLEAR (MSM_SIRC_BASE + 0x08) 103#define SPSS_SIRC_INT_ENABLE_SET (MSM_SIRC_BASE + 0x0C) 104#define SPSS_SIRC_INT_TYPE (MSM_SIRC_BASE + 0x10) 105#define SPSS_SIRC_INT_POLARITY (MSM_SIRC_BASE + 0x14) 106#define SPSS_SIRC_SECURITY (MSM_SIRC_BASE + 0x18) 107#define SPSS_SIRC_IRQ_STATUS (MSM_SIRC_BASE + 0x1C) 108#define SPSS_SIRC_IRQ1_STATUS (MSM_SIRC_BASE + 0x20) 109#define SPSS_SIRC_RAW_STATUS (MSM_SIRC_BASE + 0x24) 110#define SPSS_SIRC_INT_CLEAR (MSM_SIRC_BASE + 0x28) 111#define SPSS_SIRC_SOFT_INT (MSM_SIRC_BASE + 0x2C) 112 113#endif 114 115#endif 116