1/* 2 * Clock and PLL control for DaVinci devices 3 * 4 * Copyright (C) 2006-2007 Texas Instruments. 5 * Copyright (C) 2008-2009 Deep Root Systems, LLC 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13#include <linux/module.h> 14#include <linux/kernel.h> 15#include <linux/init.h> 16#include <linux/errno.h> 17#include <linux/clk.h> 18#include <linux/err.h> 19#include <linux/mutex.h> 20#include <linux/io.h> 21#include <linux/delay.h> 22 23#include <mach/hardware.h> 24 25#include <mach/clock.h> 26#include <mach/psc.h> 27#include <mach/cputype.h> 28#include "clock.h" 29 30static LIST_HEAD(clocks); 31static DEFINE_MUTEX(clocks_mutex); 32static DEFINE_SPINLOCK(clockfw_lock); 33 34static unsigned psc_domain(struct clk *clk) 35{ 36 return (clk->flags & PSC_DSP) 37 ? DAVINCI_GPSC_DSPDOMAIN 38 : DAVINCI_GPSC_ARMDOMAIN; 39} 40 41static void __clk_enable(struct clk *clk) 42{ 43 if (clk->parent) 44 __clk_enable(clk->parent); 45 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) 46 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 47 PSC_STATE_ENABLE); 48} 49 50static void __clk_disable(struct clk *clk) 51{ 52 if (WARN_ON(clk->usecount == 0)) 53 return; 54 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) && 55 (clk->flags & CLK_PSC)) 56 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 57 (clk->flags & PSC_SWRSTDISABLE) ? 58 PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE); 59 if (clk->parent) 60 __clk_disable(clk->parent); 61} 62 63int clk_enable(struct clk *clk) 64{ 65 unsigned long flags; 66 67 if (clk == NULL || IS_ERR(clk)) 68 return -EINVAL; 69 70 spin_lock_irqsave(&clockfw_lock, flags); 71 __clk_enable(clk); 72 spin_unlock_irqrestore(&clockfw_lock, flags); 73 74 return 0; 75} 76EXPORT_SYMBOL(clk_enable); 77 78void clk_disable(struct clk *clk) 79{ 80 unsigned long flags; 81 82 if (clk == NULL || IS_ERR(clk)) 83 return; 84 85 spin_lock_irqsave(&clockfw_lock, flags); 86 __clk_disable(clk); 87 spin_unlock_irqrestore(&clockfw_lock, flags); 88} 89EXPORT_SYMBOL(clk_disable); 90 91unsigned long clk_get_rate(struct clk *clk) 92{ 93 if (clk == NULL || IS_ERR(clk)) 94 return -EINVAL; 95 96 return clk->rate; 97} 98EXPORT_SYMBOL(clk_get_rate); 99 100long clk_round_rate(struct clk *clk, unsigned long rate) 101{ 102 if (clk == NULL || IS_ERR(clk)) 103 return -EINVAL; 104 105 if (clk->round_rate) 106 return clk->round_rate(clk, rate); 107 108 return clk->rate; 109} 110EXPORT_SYMBOL(clk_round_rate); 111 112/* Propagate rate to children */ 113static void propagate_rate(struct clk *root) 114{ 115 struct clk *clk; 116 117 list_for_each_entry(clk, &root->children, childnode) { 118 if (clk->recalc) 119 clk->rate = clk->recalc(clk); 120 propagate_rate(clk); 121 } 122} 123 124int clk_set_rate(struct clk *clk, unsigned long rate) 125{ 126 unsigned long flags; 127 int ret = -EINVAL; 128 129 if (clk == NULL || IS_ERR(clk)) 130 return ret; 131 132 if (clk->set_rate) 133 ret = clk->set_rate(clk, rate); 134 135 spin_lock_irqsave(&clockfw_lock, flags); 136 if (ret == 0) { 137 if (clk->recalc) 138 clk->rate = clk->recalc(clk); 139 propagate_rate(clk); 140 } 141 spin_unlock_irqrestore(&clockfw_lock, flags); 142 143 return ret; 144} 145EXPORT_SYMBOL(clk_set_rate); 146 147int clk_set_parent(struct clk *clk, struct clk *parent) 148{ 149 unsigned long flags; 150 151 if (clk == NULL || IS_ERR(clk)) 152 return -EINVAL; 153 154 /* Cannot change parent on enabled clock */ 155 if (WARN_ON(clk->usecount)) 156 return -EINVAL; 157 158 mutex_lock(&clocks_mutex); 159 clk->parent = parent; 160 list_del_init(&clk->childnode); 161 list_add(&clk->childnode, &clk->parent->children); 162 mutex_unlock(&clocks_mutex); 163 164 spin_lock_irqsave(&clockfw_lock, flags); 165 if (clk->recalc) 166 clk->rate = clk->recalc(clk); 167 propagate_rate(clk); 168 spin_unlock_irqrestore(&clockfw_lock, flags); 169 170 return 0; 171} 172EXPORT_SYMBOL(clk_set_parent); 173 174int clk_register(struct clk *clk) 175{ 176 if (clk == NULL || IS_ERR(clk)) 177 return -EINVAL; 178 179 if (WARN(clk->parent && !clk->parent->rate, 180 "CLK: %s parent %s has no rate!\n", 181 clk->name, clk->parent->name)) 182 return -EINVAL; 183 184 INIT_LIST_HEAD(&clk->children); 185 186 mutex_lock(&clocks_mutex); 187 list_add_tail(&clk->node, &clocks); 188 if (clk->parent) 189 list_add_tail(&clk->childnode, &clk->parent->children); 190 mutex_unlock(&clocks_mutex); 191 192 /* If rate is already set, use it */ 193 if (clk->rate) 194 return 0; 195 196 /* Else, see if there is a way to calculate it */ 197 if (clk->recalc) 198 clk->rate = clk->recalc(clk); 199 200 /* Otherwise, default to parent rate */ 201 else if (clk->parent) 202 clk->rate = clk->parent->rate; 203 204 return 0; 205} 206EXPORT_SYMBOL(clk_register); 207 208void clk_unregister(struct clk *clk) 209{ 210 if (clk == NULL || IS_ERR(clk)) 211 return; 212 213 mutex_lock(&clocks_mutex); 214 list_del(&clk->node); 215 list_del(&clk->childnode); 216 mutex_unlock(&clocks_mutex); 217} 218EXPORT_SYMBOL(clk_unregister); 219 220#ifdef CONFIG_DAVINCI_RESET_CLOCKS 221/* 222 * Disable any unused clocks left on by the bootloader 223 */ 224static int __init clk_disable_unused(void) 225{ 226 struct clk *ck; 227 228 spin_lock_irq(&clockfw_lock); 229 list_for_each_entry(ck, &clocks, node) { 230 if (ck->usecount > 0) 231 continue; 232 if (!(ck->flags & CLK_PSC)) 233 continue; 234 235 /* ignore if in Disabled or SwRstDisable states */ 236 if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc)) 237 continue; 238 239 pr_info("Clocks: disable unused %s\n", ck->name); 240 241 davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc, 242 (ck->flags & PSC_SWRSTDISABLE) ? 243 PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE); 244 } 245 spin_unlock_irq(&clockfw_lock); 246 247 return 0; 248} 249late_initcall(clk_disable_unused); 250#endif 251 252static unsigned long clk_sysclk_recalc(struct clk *clk) 253{ 254 u32 v, plldiv; 255 struct pll_data *pll; 256 unsigned long rate = clk->rate; 257 258 /* If this is the PLL base clock, no more calculations needed */ 259 if (clk->pll_data) 260 return rate; 261 262 if (WARN_ON(!clk->parent)) 263 return rate; 264 265 rate = clk->parent->rate; 266 267 /* Otherwise, the parent must be a PLL */ 268 if (WARN_ON(!clk->parent->pll_data)) 269 return rate; 270 271 pll = clk->parent->pll_data; 272 273 /* If pre-PLL, source clock is before the multiplier and divider(s) */ 274 if (clk->flags & PRE_PLL) 275 rate = pll->input_rate; 276 277 if (!clk->div_reg) 278 return rate; 279 280 v = __raw_readl(pll->base + clk->div_reg); 281 if (v & PLLDIV_EN) { 282 plldiv = (v & pll->div_ratio_mask) + 1; 283 if (plldiv) 284 rate /= plldiv; 285 } 286 287 return rate; 288} 289 290static unsigned long clk_leafclk_recalc(struct clk *clk) 291{ 292 if (WARN_ON(!clk->parent)) 293 return clk->rate; 294 295 return clk->parent->rate; 296} 297 298static unsigned long clk_pllclk_recalc(struct clk *clk) 299{ 300 u32 ctrl, mult = 1, prediv = 1, postdiv = 1; 301 u8 bypass; 302 struct pll_data *pll = clk->pll_data; 303 unsigned long rate = clk->rate; 304 305 ctrl = __raw_readl(pll->base + PLLCTL); 306 rate = pll->input_rate = clk->parent->rate; 307 308 if (ctrl & PLLCTL_PLLEN) { 309 bypass = 0; 310 mult = __raw_readl(pll->base + PLLM); 311 if (cpu_is_davinci_dm365()) 312 mult = 2 * (mult & PLLM_PLLM_MASK); 313 else 314 mult = (mult & PLLM_PLLM_MASK) + 1; 315 } else 316 bypass = 1; 317 318 if (pll->flags & PLL_HAS_PREDIV) { 319 prediv = __raw_readl(pll->base + PREDIV); 320 if (prediv & PLLDIV_EN) 321 prediv = (prediv & pll->div_ratio_mask) + 1; 322 else 323 prediv = 1; 324 } 325 326 /* pre-divider is fixed, but (some?) chips won't report that */ 327 if (cpu_is_davinci_dm355() && pll->num == 1) 328 prediv = 8; 329 330 if (pll->flags & PLL_HAS_POSTDIV) { 331 postdiv = __raw_readl(pll->base + POSTDIV); 332 if (postdiv & PLLDIV_EN) 333 postdiv = (postdiv & pll->div_ratio_mask) + 1; 334 else 335 postdiv = 1; 336 } 337 338 if (!bypass) { 339 rate /= prediv; 340 rate *= mult; 341 rate /= postdiv; 342 } 343 344 pr_debug("PLL%d: input = %lu MHz [ ", 345 pll->num, clk->parent->rate / 1000000); 346 if (bypass) 347 pr_debug("bypass "); 348 if (prediv > 1) 349 pr_debug("/ %d ", prediv); 350 if (mult > 1) 351 pr_debug("* %d ", mult); 352 if (postdiv > 1) 353 pr_debug("/ %d ", postdiv); 354 pr_debug("] --> %lu MHz output.\n", rate / 1000000); 355 356 return rate; 357} 358 359/** 360 * davinci_set_pllrate - set the output rate of a given PLL. 361 * 362 * Note: Currently tested to work with OMAP-L138 only. 363 * 364 * @pll: pll whose rate needs to be changed. 365 * @prediv: The pre divider value. Passing 0 disables the pre-divider. 366 * @pllm: The multiplier value. Passing 0 leads to multiply-by-one. 367 * @postdiv: The post divider value. Passing 0 disables the post-divider. 368 */ 369int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, 370 unsigned int mult, unsigned int postdiv) 371{ 372 u32 ctrl; 373 unsigned int locktime; 374 unsigned long flags; 375 376 if (pll->base == NULL) 377 return -EINVAL; 378 379 /* 380 * PLL lock time required per OMAP-L138 datasheet is 381 * (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm) 382 * as 4 and OSCIN cycle as 25 MHz. 383 */ 384 if (prediv) { 385 locktime = ((2000 * prediv) / 100); 386 prediv = (prediv - 1) | PLLDIV_EN; 387 } else { 388 locktime = PLL_LOCK_TIME; 389 } 390 if (postdiv) 391 postdiv = (postdiv - 1) | PLLDIV_EN; 392 if (mult) 393 mult = mult - 1; 394 395 /* Protect against simultaneous calls to PLL setting seqeunce */ 396 spin_lock_irqsave(&clockfw_lock, flags); 397 398 ctrl = __raw_readl(pll->base + PLLCTL); 399 400 /* Switch the PLL to bypass mode */ 401 ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); 402 __raw_writel(ctrl, pll->base + PLLCTL); 403 404 udelay(PLL_BYPASS_TIME); 405 406 /* Reset and enable PLL */ 407 ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS); 408 __raw_writel(ctrl, pll->base + PLLCTL); 409 410 if (pll->flags & PLL_HAS_PREDIV) 411 __raw_writel(prediv, pll->base + PREDIV); 412 413 __raw_writel(mult, pll->base + PLLM); 414 415 if (pll->flags & PLL_HAS_POSTDIV) 416 __raw_writel(postdiv, pll->base + POSTDIV); 417 418 udelay(PLL_RESET_TIME); 419 420 /* Bring PLL out of reset */ 421 ctrl |= PLLCTL_PLLRST; 422 __raw_writel(ctrl, pll->base + PLLCTL); 423 424 udelay(locktime); 425 426 /* Remove PLL from bypass mode */ 427 ctrl |= PLLCTL_PLLEN; 428 __raw_writel(ctrl, pll->base + PLLCTL); 429 430 spin_unlock_irqrestore(&clockfw_lock, flags); 431 432 return 0; 433} 434EXPORT_SYMBOL(davinci_set_pllrate); 435 436int __init davinci_clk_init(struct clk_lookup *clocks) 437 { 438 struct clk_lookup *c; 439 struct clk *clk; 440 size_t num_clocks = 0; 441 442 for (c = clocks; c->clk; c++) { 443 clk = c->clk; 444 445 if (!clk->recalc) { 446 447 /* Check if clock is a PLL */ 448 if (clk->pll_data) 449 clk->recalc = clk_pllclk_recalc; 450 451 /* Else, if it is a PLL-derived clock */ 452 else if (clk->flags & CLK_PLL) 453 clk->recalc = clk_sysclk_recalc; 454 455 /* Otherwise, it is a leaf clock (PSC clock) */ 456 else if (clk->parent) 457 clk->recalc = clk_leafclk_recalc; 458 } 459 460 if (clk->pll_data) { 461 struct pll_data *pll = clk->pll_data; 462 463 if (!pll->div_ratio_mask) 464 pll->div_ratio_mask = PLLDIV_RATIO_MASK; 465 466 if (pll->phys_base && !pll->base) { 467 pll->base = ioremap(pll->phys_base, SZ_4K); 468 WARN_ON(!pll->base); 469 } 470 } 471 472 if (clk->recalc) 473 clk->rate = clk->recalc(clk); 474 475 if (clk->lpsc) 476 clk->flags |= CLK_PSC; 477 478 clk_register(clk); 479 num_clocks++; 480 481 /* Turn on clocks that Linux doesn't otherwise manage */ 482 if (clk->flags & ALWAYS_ENABLED) 483 clk_enable(clk); 484 } 485 486 clkdev_add_table(clocks, num_clocks); 487 488 return 0; 489} 490 491#ifdef CONFIG_DEBUG_FS 492 493#include <linux/debugfs.h> 494#include <linux/seq_file.h> 495 496#define CLKNAME_MAX 10 /* longest clock name */ 497#define NEST_DELTA 2 498#define NEST_MAX 4 499 500static void 501dump_clock(struct seq_file *s, unsigned nest, struct clk *parent) 502{ 503 char *state; 504 char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX]; 505 struct clk *clk; 506 unsigned i; 507 508 if (parent->flags & CLK_PLL) 509 state = "pll"; 510 else if (parent->flags & CLK_PSC) 511 state = "psc"; 512 else 513 state = ""; 514 515 /* <nest spaces> name <pad to end> */ 516 memset(buf, ' ', sizeof(buf) - 1); 517 buf[sizeof(buf) - 1] = 0; 518 i = strlen(parent->name); 519 memcpy(buf + nest, parent->name, 520 min(i, (unsigned)(sizeof(buf) - 1 - nest))); 521 522 seq_printf(s, "%s users=%2d %-3s %9ld Hz\n", 523 buf, parent->usecount, state, clk_get_rate(parent)); 524 /* REVISIT show device associations too */ 525 526 /* cost is now small, but not linear... */ 527 list_for_each_entry(clk, &parent->children, childnode) { 528 dump_clock(s, nest + NEST_DELTA, clk); 529 } 530} 531 532static int davinci_ck_show(struct seq_file *m, void *v) 533{ 534 struct clk *clk; 535 536 /* 537 * Show clock tree; We trust nonzero usecounts equate to PSC enables... 538 */ 539 mutex_lock(&clocks_mutex); 540 list_for_each_entry(clk, &clocks, node) 541 if (!clk->parent) 542 dump_clock(m, 0, clk); 543 mutex_unlock(&clocks_mutex); 544 545 return 0; 546} 547 548static int davinci_ck_open(struct inode *inode, struct file *file) 549{ 550 return single_open(file, davinci_ck_show, NULL); 551} 552 553static const struct file_operations davinci_ck_operations = { 554 .open = davinci_ck_open, 555 .read = seq_read, 556 .llseek = seq_lseek, 557 .release = single_release, 558}; 559 560static int __init davinci_clk_debugfs_init(void) 561{ 562 debugfs_create_file("davinci_clocks", S_IFREG | S_IRUGO, NULL, NULL, 563 &davinci_ck_operations); 564 return 0; 565 566} 567device_initcall(davinci_clk_debugfs_init); 568#endif /* CONFIG_DEBUG_FS */ 569