1/* 2 * Copyright (C) 2007 Atmel Corporation 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file COPYING in the main directory of this archive for 6 * more details. 7 */ 8 9#include <asm/mach/arch.h> 10#include <asm/mach/map.h> 11 12#include <linux/dma-mapping.h> 13#include <linux/platform_device.h> 14#include <linux/i2c-gpio.h> 15 16#include <linux/fb.h> 17#include <video/atmel_lcdc.h> 18 19#include <mach/board.h> 20#include <mach/gpio.h> 21#include <mach/at91sam9rl.h> 22#include <mach/at91sam9rl_matrix.h> 23#include <mach/at91sam9_smc.h> 24#include <mach/at_hdmac.h> 25 26#include "generic.h" 27 28 29/* -------------------------------------------------------------------- 30 * HDMAC - AHB DMA Controller 31 * -------------------------------------------------------------------- */ 32 33#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE) 34static u64 hdmac_dmamask = DMA_BIT_MASK(32); 35 36static struct at_dma_platform_data atdma_pdata = { 37 .nr_channels = 2, 38}; 39 40static struct resource hdmac_resources[] = { 41 [0] = { 42 .start = AT91_BASE_SYS + AT91_DMA, 43 .end = AT91_BASE_SYS + AT91_DMA + SZ_512 - 1, 44 .flags = IORESOURCE_MEM, 45 }, 46 [2] = { 47 .start = AT91SAM9RL_ID_DMA, 48 .end = AT91SAM9RL_ID_DMA, 49 .flags = IORESOURCE_IRQ, 50 }, 51}; 52 53static struct platform_device at_hdmac_device = { 54 .name = "at_hdmac", 55 .id = -1, 56 .dev = { 57 .dma_mask = &hdmac_dmamask, 58 .coherent_dma_mask = DMA_BIT_MASK(32), 59 .platform_data = &atdma_pdata, 60 }, 61 .resource = hdmac_resources, 62 .num_resources = ARRAY_SIZE(hdmac_resources), 63}; 64 65void __init at91_add_device_hdmac(void) 66{ 67 dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask); 68 platform_device_register(&at_hdmac_device); 69} 70#else 71void __init at91_add_device_hdmac(void) {} 72#endif 73 74/* -------------------------------------------------------------------- 75 * USB HS Device (Gadget) 76 * -------------------------------------------------------------------- */ 77 78#if defined(CONFIG_USB_GADGET_ATMEL_USBA) || \ 79 defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE) 80 81static struct resource usba_udc_resources[] = { 82 [0] = { 83 .start = AT91SAM9RL_UDPHS_FIFO, 84 .end = AT91SAM9RL_UDPHS_FIFO + SZ_512K - 1, 85 .flags = IORESOURCE_MEM, 86 }, 87 [1] = { 88 .start = AT91SAM9RL_BASE_UDPHS, 89 .end = AT91SAM9RL_BASE_UDPHS + SZ_1K - 1, 90 .flags = IORESOURCE_MEM, 91 }, 92 [2] = { 93 .start = AT91SAM9RL_ID_UDPHS, 94 .end = AT91SAM9RL_ID_UDPHS, 95 .flags = IORESOURCE_IRQ, 96 }, 97}; 98 99#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \ 100 [idx] = { \ 101 .name = nam, \ 102 .index = idx, \ 103 .fifo_size = maxpkt, \ 104 .nr_banks = maxbk, \ 105 .can_dma = dma, \ 106 .can_isoc = isoc, \ 107 } 108 109static struct usba_ep_data usba_udc_ep[] __initdata = { 110 EP("ep0", 0, 64, 1, 0, 0), 111 EP("ep1", 1, 1024, 2, 1, 1), 112 EP("ep2", 2, 1024, 2, 1, 1), 113 EP("ep3", 3, 1024, 3, 1, 0), 114 EP("ep4", 4, 1024, 3, 1, 0), 115 EP("ep5", 5, 1024, 3, 1, 1), 116 EP("ep6", 6, 1024, 3, 1, 1), 117}; 118 119#undef EP 120 121/* 122 * pdata doesn't have room for any endpoints, so we need to 123 * append room for the ones we need right after it. 124 */ 125static struct { 126 struct usba_platform_data pdata; 127 struct usba_ep_data ep[7]; 128} usba_udc_data; 129 130static struct platform_device at91_usba_udc_device = { 131 .name = "atmel_usba_udc", 132 .id = -1, 133 .dev = { 134 .platform_data = &usba_udc_data.pdata, 135 }, 136 .resource = usba_udc_resources, 137 .num_resources = ARRAY_SIZE(usba_udc_resources), 138}; 139 140void __init at91_add_device_usba(struct usba_platform_data *data) 141{ 142 /* 143 * Invalid pins are 0 on AT91, but the usba driver is shared 144 * with AVR32, which use negative values instead. Once/if 145 * gpio_is_valid() is ported to AT91, revisit this code. 146 */ 147 usba_udc_data.pdata.vbus_pin = -EINVAL; 148 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep); 149 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));; 150 151 if (data && data->vbus_pin > 0) { 152 at91_set_gpio_input(data->vbus_pin, 0); 153 at91_set_deglitch(data->vbus_pin, 1); 154 usba_udc_data.pdata.vbus_pin = data->vbus_pin; 155 } 156 157 /* Pullup pin is handled internally by USB device peripheral */ 158 159 /* Clocks */ 160 at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk"); 161 at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk"); 162 163 platform_device_register(&at91_usba_udc_device); 164} 165#else 166void __init at91_add_device_usba(struct usba_platform_data *data) {} 167#endif 168 169 170/* -------------------------------------------------------------------- 171 * MMC / SD 172 * -------------------------------------------------------------------- */ 173 174#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE) 175static u64 mmc_dmamask = DMA_BIT_MASK(32); 176static struct at91_mmc_data mmc_data; 177 178static struct resource mmc_resources[] = { 179 [0] = { 180 .start = AT91SAM9RL_BASE_MCI, 181 .end = AT91SAM9RL_BASE_MCI + SZ_16K - 1, 182 .flags = IORESOURCE_MEM, 183 }, 184 [1] = { 185 .start = AT91SAM9RL_ID_MCI, 186 .end = AT91SAM9RL_ID_MCI, 187 .flags = IORESOURCE_IRQ, 188 }, 189}; 190 191static struct platform_device at91sam9rl_mmc_device = { 192 .name = "at91_mci", 193 .id = -1, 194 .dev = { 195 .dma_mask = &mmc_dmamask, 196 .coherent_dma_mask = DMA_BIT_MASK(32), 197 .platform_data = &mmc_data, 198 }, 199 .resource = mmc_resources, 200 .num_resources = ARRAY_SIZE(mmc_resources), 201}; 202 203void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) 204{ 205 if (!data) 206 return; 207 208 /* input/irq */ 209 if (data->det_pin) { 210 at91_set_gpio_input(data->det_pin, 1); 211 at91_set_deglitch(data->det_pin, 1); 212 } 213 if (data->wp_pin) 214 at91_set_gpio_input(data->wp_pin, 1); 215 if (data->vcc_pin) 216 at91_set_gpio_output(data->vcc_pin, 0); 217 218 /* CLK */ 219 at91_set_A_periph(AT91_PIN_PA2, 0); 220 221 /* CMD */ 222 at91_set_A_periph(AT91_PIN_PA1, 1); 223 224 /* DAT0, maybe DAT1..DAT3 */ 225 at91_set_A_periph(AT91_PIN_PA0, 1); 226 if (data->wire4) { 227 at91_set_A_periph(AT91_PIN_PA3, 1); 228 at91_set_A_periph(AT91_PIN_PA4, 1); 229 at91_set_A_periph(AT91_PIN_PA5, 1); 230 } 231 232 mmc_data = *data; 233 platform_device_register(&at91sam9rl_mmc_device); 234} 235#else 236void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {} 237#endif 238 239 240/* -------------------------------------------------------------------- 241 * NAND / SmartMedia 242 * -------------------------------------------------------------------- */ 243 244#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE) 245static struct atmel_nand_data nand_data; 246 247#define NAND_BASE AT91_CHIPSELECT_3 248 249static struct resource nand_resources[] = { 250 [0] = { 251 .start = NAND_BASE, 252 .end = NAND_BASE + SZ_256M - 1, 253 .flags = IORESOURCE_MEM, 254 }, 255 [1] = { 256 .start = AT91_BASE_SYS + AT91_ECC, 257 .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1, 258 .flags = IORESOURCE_MEM, 259 } 260}; 261 262static struct platform_device atmel_nand_device = { 263 .name = "atmel_nand", 264 .id = -1, 265 .dev = { 266 .platform_data = &nand_data, 267 }, 268 .resource = nand_resources, 269 .num_resources = ARRAY_SIZE(nand_resources), 270}; 271 272void __init at91_add_device_nand(struct atmel_nand_data *data) 273{ 274 unsigned long csa; 275 276 if (!data) 277 return; 278 279 csa = at91_sys_read(AT91_MATRIX_EBICSA); 280 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 281 282 /* enable pin */ 283 if (data->enable_pin) 284 at91_set_gpio_output(data->enable_pin, 1); 285 286 /* ready/busy pin */ 287 if (data->rdy_pin) 288 at91_set_gpio_input(data->rdy_pin, 1); 289 290 /* card detect pin */ 291 if (data->det_pin) 292 at91_set_gpio_input(data->det_pin, 1); 293 294 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */ 295 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */ 296 297 nand_data = *data; 298 platform_device_register(&atmel_nand_device); 299} 300 301#else 302void __init at91_add_device_nand(struct atmel_nand_data *data) {} 303#endif 304 305 306/* -------------------------------------------------------------------- 307 * TWI (i2c) 308 * -------------------------------------------------------------------- */ 309 310/* 311 * Prefer the GPIO code since the TWI controller isn't robust 312 * (gets overruns and underruns under load) and can only issue 313 * repeated STARTs in one scenario (the driver doesn't yet handle them). 314 */ 315#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) 316 317static struct i2c_gpio_platform_data pdata = { 318 .sda_pin = AT91_PIN_PA23, 319 .sda_is_open_drain = 1, 320 .scl_pin = AT91_PIN_PA24, 321 .scl_is_open_drain = 1, 322 .udelay = 2, /* ~100 kHz */ 323}; 324 325static struct platform_device at91sam9rl_twi_device = { 326 .name = "i2c-gpio", 327 .id = -1, 328 .dev.platform_data = &pdata, 329}; 330 331void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) 332{ 333 at91_set_GPIO_periph(AT91_PIN_PA23, 1); /* TWD (SDA) */ 334 at91_set_multi_drive(AT91_PIN_PA23, 1); 335 336 at91_set_GPIO_periph(AT91_PIN_PA24, 1); /* TWCK (SCL) */ 337 at91_set_multi_drive(AT91_PIN_PA24, 1); 338 339 i2c_register_board_info(0, devices, nr_devices); 340 platform_device_register(&at91sam9rl_twi_device); 341} 342 343#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE) 344 345static struct resource twi_resources[] = { 346 [0] = { 347 .start = AT91SAM9RL_BASE_TWI0, 348 .end = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1, 349 .flags = IORESOURCE_MEM, 350 }, 351 [1] = { 352 .start = AT91SAM9RL_ID_TWI0, 353 .end = AT91SAM9RL_ID_TWI0, 354 .flags = IORESOURCE_IRQ, 355 }, 356}; 357 358static struct platform_device at91sam9rl_twi_device = { 359 .name = "at91_i2c", 360 .id = -1, 361 .resource = twi_resources, 362 .num_resources = ARRAY_SIZE(twi_resources), 363}; 364 365void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) 366{ 367 /* pins used for TWI interface */ 368 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */ 369 at91_set_multi_drive(AT91_PIN_PA23, 1); 370 371 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */ 372 at91_set_multi_drive(AT91_PIN_PA24, 1); 373 374 i2c_register_board_info(0, devices, nr_devices); 375 platform_device_register(&at91sam9rl_twi_device); 376} 377#else 378void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {} 379#endif 380 381 382/* -------------------------------------------------------------------- 383 * SPI 384 * -------------------------------------------------------------------- */ 385 386#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) 387static u64 spi_dmamask = DMA_BIT_MASK(32); 388 389static struct resource spi_resources[] = { 390 [0] = { 391 .start = AT91SAM9RL_BASE_SPI, 392 .end = AT91SAM9RL_BASE_SPI + SZ_16K - 1, 393 .flags = IORESOURCE_MEM, 394 }, 395 [1] = { 396 .start = AT91SAM9RL_ID_SPI, 397 .end = AT91SAM9RL_ID_SPI, 398 .flags = IORESOURCE_IRQ, 399 }, 400}; 401 402static struct platform_device at91sam9rl_spi_device = { 403 .name = "atmel_spi", 404 .id = 0, 405 .dev = { 406 .dma_mask = &spi_dmamask, 407 .coherent_dma_mask = DMA_BIT_MASK(32), 408 }, 409 .resource = spi_resources, 410 .num_resources = ARRAY_SIZE(spi_resources), 411}; 412 413static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 }; 414 415 416void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) 417{ 418 int i; 419 unsigned long cs_pin; 420 421 at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */ 422 at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */ 423 at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */ 424 425 /* Enable SPI chip-selects */ 426 for (i = 0; i < nr_devices; i++) { 427 if (devices[i].controller_data) 428 cs_pin = (unsigned long) devices[i].controller_data; 429 else 430 cs_pin = spi_standard_cs[devices[i].chip_select]; 431 432 /* enable chip-select pin */ 433 at91_set_gpio_output(cs_pin, 1); 434 435 /* pass chip-select pin to driver */ 436 devices[i].controller_data = (void *) cs_pin; 437 } 438 439 spi_register_board_info(devices, nr_devices); 440 platform_device_register(&at91sam9rl_spi_device); 441} 442#else 443void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {} 444#endif 445 446 447/* -------------------------------------------------------------------- 448 * AC97 449 * -------------------------------------------------------------------- */ 450 451#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE) 452static u64 ac97_dmamask = DMA_BIT_MASK(32); 453static struct ac97c_platform_data ac97_data; 454 455static struct resource ac97_resources[] = { 456 [0] = { 457 .start = AT91SAM9RL_BASE_AC97C, 458 .end = AT91SAM9RL_BASE_AC97C + SZ_16K - 1, 459 .flags = IORESOURCE_MEM, 460 }, 461 [1] = { 462 .start = AT91SAM9RL_ID_AC97C, 463 .end = AT91SAM9RL_ID_AC97C, 464 .flags = IORESOURCE_IRQ, 465 }, 466}; 467 468static struct platform_device at91sam9rl_ac97_device = { 469 .name = "atmel_ac97c", 470 .id = 0, 471 .dev = { 472 .dma_mask = &ac97_dmamask, 473 .coherent_dma_mask = DMA_BIT_MASK(32), 474 .platform_data = &ac97_data, 475 }, 476 .resource = ac97_resources, 477 .num_resources = ARRAY_SIZE(ac97_resources), 478}; 479 480void __init at91_add_device_ac97(struct ac97c_platform_data *data) 481{ 482 if (!data) 483 return; 484 485 at91_set_A_periph(AT91_PIN_PD1, 0); /* AC97FS */ 486 at91_set_A_periph(AT91_PIN_PD2, 0); /* AC97CK */ 487 at91_set_A_periph(AT91_PIN_PD3, 0); /* AC97TX */ 488 at91_set_A_periph(AT91_PIN_PD4, 0); /* AC97RX */ 489 490 /* reset */ 491 if (data->reset_pin) 492 at91_set_gpio_output(data->reset_pin, 0); 493 494 ac97_data = *data; 495 platform_device_register(&at91sam9rl_ac97_device); 496} 497#else 498void __init at91_add_device_ac97(struct ac97c_platform_data *data) {} 499#endif 500 501 502/* -------------------------------------------------------------------- 503 * LCD Controller 504 * -------------------------------------------------------------------- */ 505 506#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) 507static u64 lcdc_dmamask = DMA_BIT_MASK(32); 508static struct atmel_lcdfb_info lcdc_data; 509 510static struct resource lcdc_resources[] = { 511 [0] = { 512 .start = AT91SAM9RL_LCDC_BASE, 513 .end = AT91SAM9RL_LCDC_BASE + SZ_4K - 1, 514 .flags = IORESOURCE_MEM, 515 }, 516 [1] = { 517 .start = AT91SAM9RL_ID_LCDC, 518 .end = AT91SAM9RL_ID_LCDC, 519 .flags = IORESOURCE_IRQ, 520 }, 521}; 522 523static struct platform_device at91_lcdc_device = { 524 .name = "atmel_lcdfb", 525 .id = 0, 526 .dev = { 527 .dma_mask = &lcdc_dmamask, 528 .coherent_dma_mask = DMA_BIT_MASK(32), 529 .platform_data = &lcdc_data, 530 }, 531 .resource = lcdc_resources, 532 .num_resources = ARRAY_SIZE(lcdc_resources), 533}; 534 535void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) 536{ 537 if (!data) { 538 return; 539 } 540 541 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */ 542 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */ 543 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */ 544 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */ 545 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */ 546 at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */ 547 at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */ 548 at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */ 549 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */ 550 at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */ 551 at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */ 552 at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */ 553 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */ 554 at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */ 555 at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */ 556 at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */ 557 at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */ 558 at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */ 559 at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */ 560 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */ 561 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */ 562 563 lcdc_data = *data; 564 platform_device_register(&at91_lcdc_device); 565} 566#else 567void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} 568#endif 569 570 571/* -------------------------------------------------------------------- 572 * Timer/Counter block 573 * -------------------------------------------------------------------- */ 574 575#ifdef CONFIG_ATMEL_TCLIB 576 577static struct resource tcb_resources[] = { 578 [0] = { 579 .start = AT91SAM9RL_BASE_TCB0, 580 .end = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1, 581 .flags = IORESOURCE_MEM, 582 }, 583 [1] = { 584 .start = AT91SAM9RL_ID_TC0, 585 .end = AT91SAM9RL_ID_TC0, 586 .flags = IORESOURCE_IRQ, 587 }, 588 [2] = { 589 .start = AT91SAM9RL_ID_TC1, 590 .end = AT91SAM9RL_ID_TC1, 591 .flags = IORESOURCE_IRQ, 592 }, 593 [3] = { 594 .start = AT91SAM9RL_ID_TC2, 595 .end = AT91SAM9RL_ID_TC2, 596 .flags = IORESOURCE_IRQ, 597 }, 598}; 599 600static struct platform_device at91sam9rl_tcb_device = { 601 .name = "atmel_tcb", 602 .id = 0, 603 .resource = tcb_resources, 604 .num_resources = ARRAY_SIZE(tcb_resources), 605}; 606 607static void __init at91_add_device_tc(void) 608{ 609 /* this chip has a separate clock and irq for each TC channel */ 610 at91_clock_associate("tc0_clk", &at91sam9rl_tcb_device.dev, "t0_clk"); 611 at91_clock_associate("tc1_clk", &at91sam9rl_tcb_device.dev, "t1_clk"); 612 at91_clock_associate("tc2_clk", &at91sam9rl_tcb_device.dev, "t2_clk"); 613 platform_device_register(&at91sam9rl_tcb_device); 614} 615#else 616static void __init at91_add_device_tc(void) { } 617#endif 618 619 620/* -------------------------------------------------------------------- 621 * Touchscreen 622 * -------------------------------------------------------------------- */ 623 624#if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || \ 625 defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE) 626static u64 tsadcc_dmamask = DMA_BIT_MASK(32); 627static struct at91_tsadcc_data tsadcc_data; 628 629static struct resource tsadcc_resources[] = { 630 [0] = { 631 .start = AT91SAM9RL_BASE_TSC, 632 .end = AT91SAM9RL_BASE_TSC + SZ_16K - 1, 633 .flags = IORESOURCE_MEM, 634 }, 635 [1] = { 636 .start = AT91SAM9RL_ID_TSC, 637 .end = AT91SAM9RL_ID_TSC, 638 .flags = IORESOURCE_IRQ, 639 } 640}; 641 642static struct platform_device at91sam9rl_tsadcc_device = { 643 .name = "atmel_tsadcc", 644 .id = -1, 645 .dev = { 646 .dma_mask = &tsadcc_dmamask, 647 .coherent_dma_mask = DMA_BIT_MASK(32), 648 .platform_data = &tsadcc_data, 649 }, 650 .resource = tsadcc_resources, 651 .num_resources = ARRAY_SIZE(tsadcc_resources), 652}; 653 654void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) 655{ 656 if (!data) 657 return; 658 659 at91_set_A_periph(AT91_PIN_PA17, 0); /* AD0_XR */ 660 at91_set_A_periph(AT91_PIN_PA18, 0); /* AD1_XL */ 661 at91_set_A_periph(AT91_PIN_PA19, 0); /* AD2_YT */ 662 at91_set_A_periph(AT91_PIN_PA20, 0); /* AD3_TB */ 663 664 tsadcc_data = *data; 665 platform_device_register(&at91sam9rl_tsadcc_device); 666} 667#else 668void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {} 669#endif 670 671 672/* -------------------------------------------------------------------- 673 * RTC 674 * -------------------------------------------------------------------- */ 675 676#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE) 677static struct platform_device at91sam9rl_rtc_device = { 678 .name = "at91_rtc", 679 .id = -1, 680 .num_resources = 0, 681}; 682 683static void __init at91_add_device_rtc(void) 684{ 685 platform_device_register(&at91sam9rl_rtc_device); 686} 687#else 688static void __init at91_add_device_rtc(void) {} 689#endif 690 691 692/* -------------------------------------------------------------------- 693 * RTT 694 * -------------------------------------------------------------------- */ 695 696static struct resource rtt_resources[] = { 697 { 698 .start = AT91_BASE_SYS + AT91_RTT, 699 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1, 700 .flags = IORESOURCE_MEM, 701 } 702}; 703 704static struct platform_device at91sam9rl_rtt_device = { 705 .name = "at91_rtt", 706 .id = 0, 707 .resource = rtt_resources, 708 .num_resources = ARRAY_SIZE(rtt_resources), 709}; 710 711static void __init at91_add_device_rtt(void) 712{ 713 platform_device_register(&at91sam9rl_rtt_device); 714} 715 716 717/* -------------------------------------------------------------------- 718 * Watchdog 719 * -------------------------------------------------------------------- */ 720 721#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE) 722static struct platform_device at91sam9rl_wdt_device = { 723 .name = "at91_wdt", 724 .id = -1, 725 .num_resources = 0, 726}; 727 728static void __init at91_add_device_watchdog(void) 729{ 730 platform_device_register(&at91sam9rl_wdt_device); 731} 732#else 733static void __init at91_add_device_watchdog(void) {} 734#endif 735 736 737/* -------------------------------------------------------------------- 738 * PWM 739 * --------------------------------------------------------------------*/ 740 741#if defined(CONFIG_ATMEL_PWM) 742static u32 pwm_mask; 743 744static struct resource pwm_resources[] = { 745 [0] = { 746 .start = AT91SAM9RL_BASE_PWMC, 747 .end = AT91SAM9RL_BASE_PWMC + SZ_16K - 1, 748 .flags = IORESOURCE_MEM, 749 }, 750 [1] = { 751 .start = AT91SAM9RL_ID_PWMC, 752 .end = AT91SAM9RL_ID_PWMC, 753 .flags = IORESOURCE_IRQ, 754 }, 755}; 756 757static struct platform_device at91sam9rl_pwm0_device = { 758 .name = "atmel_pwm", 759 .id = -1, 760 .dev = { 761 .platform_data = &pwm_mask, 762 }, 763 .resource = pwm_resources, 764 .num_resources = ARRAY_SIZE(pwm_resources), 765}; 766 767void __init at91_add_device_pwm(u32 mask) 768{ 769 if (mask & (1 << AT91_PWM0)) 770 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM0 */ 771 772 if (mask & (1 << AT91_PWM1)) 773 at91_set_B_periph(AT91_PIN_PB9, 1); /* enable PWM1 */ 774 775 if (mask & (1 << AT91_PWM2)) 776 at91_set_B_periph(AT91_PIN_PD5, 1); /* enable PWM2 */ 777 778 if (mask & (1 << AT91_PWM3)) 779 at91_set_B_periph(AT91_PIN_PD8, 1); /* enable PWM3 */ 780 781 pwm_mask = mask; 782 783 platform_device_register(&at91sam9rl_pwm0_device); 784} 785#else 786void __init at91_add_device_pwm(u32 mask) {} 787#endif 788 789 790/* -------------------------------------------------------------------- 791 * SSC -- Synchronous Serial Controller 792 * -------------------------------------------------------------------- */ 793 794#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE) 795static u64 ssc0_dmamask = DMA_BIT_MASK(32); 796 797static struct resource ssc0_resources[] = { 798 [0] = { 799 .start = AT91SAM9RL_BASE_SSC0, 800 .end = AT91SAM9RL_BASE_SSC0 + SZ_16K - 1, 801 .flags = IORESOURCE_MEM, 802 }, 803 [1] = { 804 .start = AT91SAM9RL_ID_SSC0, 805 .end = AT91SAM9RL_ID_SSC0, 806 .flags = IORESOURCE_IRQ, 807 }, 808}; 809 810static struct platform_device at91sam9rl_ssc0_device = { 811 .name = "ssc", 812 .id = 0, 813 .dev = { 814 .dma_mask = &ssc0_dmamask, 815 .coherent_dma_mask = DMA_BIT_MASK(32), 816 }, 817 .resource = ssc0_resources, 818 .num_resources = ARRAY_SIZE(ssc0_resources), 819}; 820 821static inline void configure_ssc0_pins(unsigned pins) 822{ 823 if (pins & ATMEL_SSC_TF) 824 at91_set_A_periph(AT91_PIN_PC0, 1); 825 if (pins & ATMEL_SSC_TK) 826 at91_set_A_periph(AT91_PIN_PC1, 1); 827 if (pins & ATMEL_SSC_TD) 828 at91_set_A_periph(AT91_PIN_PA15, 1); 829 if (pins & ATMEL_SSC_RD) 830 at91_set_A_periph(AT91_PIN_PA16, 1); 831 if (pins & ATMEL_SSC_RK) 832 at91_set_B_periph(AT91_PIN_PA10, 1); 833 if (pins & ATMEL_SSC_RF) 834 at91_set_B_periph(AT91_PIN_PA22, 1); 835} 836 837static u64 ssc1_dmamask = DMA_BIT_MASK(32); 838 839static struct resource ssc1_resources[] = { 840 [0] = { 841 .start = AT91SAM9RL_BASE_SSC1, 842 .end = AT91SAM9RL_BASE_SSC1 + SZ_16K - 1, 843 .flags = IORESOURCE_MEM, 844 }, 845 [1] = { 846 .start = AT91SAM9RL_ID_SSC1, 847 .end = AT91SAM9RL_ID_SSC1, 848 .flags = IORESOURCE_IRQ, 849 }, 850}; 851 852static struct platform_device at91sam9rl_ssc1_device = { 853 .name = "ssc", 854 .id = 1, 855 .dev = { 856 .dma_mask = &ssc1_dmamask, 857 .coherent_dma_mask = DMA_BIT_MASK(32), 858 }, 859 .resource = ssc1_resources, 860 .num_resources = ARRAY_SIZE(ssc1_resources), 861}; 862 863static inline void configure_ssc1_pins(unsigned pins) 864{ 865 if (pins & ATMEL_SSC_TF) 866 at91_set_B_periph(AT91_PIN_PA29, 1); 867 if (pins & ATMEL_SSC_TK) 868 at91_set_B_periph(AT91_PIN_PA30, 1); 869 if (pins & ATMEL_SSC_TD) 870 at91_set_B_periph(AT91_PIN_PA13, 1); 871 if (pins & ATMEL_SSC_RD) 872 at91_set_B_periph(AT91_PIN_PA14, 1); 873 if (pins & ATMEL_SSC_RK) 874 at91_set_B_periph(AT91_PIN_PA9, 1); 875 if (pins & ATMEL_SSC_RF) 876 at91_set_B_periph(AT91_PIN_PA8, 1); 877} 878 879/* 880 * SSC controllers are accessed through library code, instead of any 881 * kind of all-singing/all-dancing driver. For example one could be 882 * used by a particular I2S audio codec's driver, while another one 883 * on the same system might be used by a custom data capture driver. 884 */ 885void __init at91_add_device_ssc(unsigned id, unsigned pins) 886{ 887 struct platform_device *pdev; 888 889 /* 890 * NOTE: caller is responsible for passing information matching 891 * "pins" to whatever will be using each particular controller. 892 */ 893 switch (id) { 894 case AT91SAM9RL_ID_SSC0: 895 pdev = &at91sam9rl_ssc0_device; 896 configure_ssc0_pins(pins); 897 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk"); 898 break; 899 case AT91SAM9RL_ID_SSC1: 900 pdev = &at91sam9rl_ssc1_device; 901 configure_ssc1_pins(pins); 902 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk"); 903 break; 904 default: 905 return; 906 } 907 908 platform_device_register(pdev); 909} 910 911#else 912void __init at91_add_device_ssc(unsigned id, unsigned pins) {} 913#endif 914 915 916/* -------------------------------------------------------------------- 917 * UART 918 * -------------------------------------------------------------------- */ 919 920#if defined(CONFIG_SERIAL_ATMEL) 921static struct resource dbgu_resources[] = { 922 [0] = { 923 .start = AT91_VA_BASE_SYS + AT91_DBGU, 924 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1, 925 .flags = IORESOURCE_MEM, 926 }, 927 [1] = { 928 .start = AT91_ID_SYS, 929 .end = AT91_ID_SYS, 930 .flags = IORESOURCE_IRQ, 931 }, 932}; 933 934static struct atmel_uart_data dbgu_data = { 935 .use_dma_tx = 0, 936 .use_dma_rx = 0, /* DBGU not capable of receive DMA */ 937 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU), 938}; 939 940static u64 dbgu_dmamask = DMA_BIT_MASK(32); 941 942static struct platform_device at91sam9rl_dbgu_device = { 943 .name = "atmel_usart", 944 .id = 0, 945 .dev = { 946 .dma_mask = &dbgu_dmamask, 947 .coherent_dma_mask = DMA_BIT_MASK(32), 948 .platform_data = &dbgu_data, 949 }, 950 .resource = dbgu_resources, 951 .num_resources = ARRAY_SIZE(dbgu_resources), 952}; 953 954static inline void configure_dbgu_pins(void) 955{ 956 at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */ 957 at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */ 958} 959 960static struct resource uart0_resources[] = { 961 [0] = { 962 .start = AT91SAM9RL_BASE_US0, 963 .end = AT91SAM9RL_BASE_US0 + SZ_16K - 1, 964 .flags = IORESOURCE_MEM, 965 }, 966 [1] = { 967 .start = AT91SAM9RL_ID_US0, 968 .end = AT91SAM9RL_ID_US0, 969 .flags = IORESOURCE_IRQ, 970 }, 971}; 972 973static struct atmel_uart_data uart0_data = { 974 .use_dma_tx = 1, 975 .use_dma_rx = 1, 976}; 977 978static u64 uart0_dmamask = DMA_BIT_MASK(32); 979 980static struct platform_device at91sam9rl_uart0_device = { 981 .name = "atmel_usart", 982 .id = 1, 983 .dev = { 984 .dma_mask = &uart0_dmamask, 985 .coherent_dma_mask = DMA_BIT_MASK(32), 986 .platform_data = &uart0_data, 987 }, 988 .resource = uart0_resources, 989 .num_resources = ARRAY_SIZE(uart0_resources), 990}; 991 992static inline void configure_usart0_pins(unsigned pins) 993{ 994 at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */ 995 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */ 996 997 if (pins & ATMEL_UART_RTS) 998 at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */ 999 if (pins & ATMEL_UART_CTS) 1000 at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */ 1001 if (pins & ATMEL_UART_DSR) 1002 at91_set_A_periph(AT91_PIN_PD14, 0); /* DSR0 */ 1003 if (pins & ATMEL_UART_DTR) 1004 at91_set_A_periph(AT91_PIN_PD15, 0); /* DTR0 */ 1005 if (pins & ATMEL_UART_DCD) 1006 at91_set_A_periph(AT91_PIN_PD16, 0); /* DCD0 */ 1007 if (pins & ATMEL_UART_RI) 1008 at91_set_A_periph(AT91_PIN_PD17, 0); /* RI0 */ 1009} 1010 1011static struct resource uart1_resources[] = { 1012 [0] = { 1013 .start = AT91SAM9RL_BASE_US1, 1014 .end = AT91SAM9RL_BASE_US1 + SZ_16K - 1, 1015 .flags = IORESOURCE_MEM, 1016 }, 1017 [1] = { 1018 .start = AT91SAM9RL_ID_US1, 1019 .end = AT91SAM9RL_ID_US1, 1020 .flags = IORESOURCE_IRQ, 1021 }, 1022}; 1023 1024static struct atmel_uart_data uart1_data = { 1025 .use_dma_tx = 1, 1026 .use_dma_rx = 1, 1027}; 1028 1029static u64 uart1_dmamask = DMA_BIT_MASK(32); 1030 1031static struct platform_device at91sam9rl_uart1_device = { 1032 .name = "atmel_usart", 1033 .id = 2, 1034 .dev = { 1035 .dma_mask = &uart1_dmamask, 1036 .coherent_dma_mask = DMA_BIT_MASK(32), 1037 .platform_data = &uart1_data, 1038 }, 1039 .resource = uart1_resources, 1040 .num_resources = ARRAY_SIZE(uart1_resources), 1041}; 1042 1043static inline void configure_usart1_pins(unsigned pins) 1044{ 1045 at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */ 1046 at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */ 1047 1048 if (pins & ATMEL_UART_RTS) 1049 at91_set_B_periph(AT91_PIN_PA18, 0); /* RTS1 */ 1050 if (pins & ATMEL_UART_CTS) 1051 at91_set_B_periph(AT91_PIN_PA19, 0); /* CTS1 */ 1052} 1053 1054static struct resource uart2_resources[] = { 1055 [0] = { 1056 .start = AT91SAM9RL_BASE_US2, 1057 .end = AT91SAM9RL_BASE_US2 + SZ_16K - 1, 1058 .flags = IORESOURCE_MEM, 1059 }, 1060 [1] = { 1061 .start = AT91SAM9RL_ID_US2, 1062 .end = AT91SAM9RL_ID_US2, 1063 .flags = IORESOURCE_IRQ, 1064 }, 1065}; 1066 1067static struct atmel_uart_data uart2_data = { 1068 .use_dma_tx = 1, 1069 .use_dma_rx = 1, 1070}; 1071 1072static u64 uart2_dmamask = DMA_BIT_MASK(32); 1073 1074static struct platform_device at91sam9rl_uart2_device = { 1075 .name = "atmel_usart", 1076 .id = 3, 1077 .dev = { 1078 .dma_mask = &uart2_dmamask, 1079 .coherent_dma_mask = DMA_BIT_MASK(32), 1080 .platform_data = &uart2_data, 1081 }, 1082 .resource = uart2_resources, 1083 .num_resources = ARRAY_SIZE(uart2_resources), 1084}; 1085 1086static inline void configure_usart2_pins(unsigned pins) 1087{ 1088 at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */ 1089 at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */ 1090 1091 if (pins & ATMEL_UART_RTS) 1092 at91_set_A_periph(AT91_PIN_PA29, 0); /* RTS2 */ 1093 if (pins & ATMEL_UART_CTS) 1094 at91_set_A_periph(AT91_PIN_PA30, 0); /* CTS2 */ 1095} 1096 1097static struct resource uart3_resources[] = { 1098 [0] = { 1099 .start = AT91SAM9RL_BASE_US3, 1100 .end = AT91SAM9RL_BASE_US3 + SZ_16K - 1, 1101 .flags = IORESOURCE_MEM, 1102 }, 1103 [1] = { 1104 .start = AT91SAM9RL_ID_US3, 1105 .end = AT91SAM9RL_ID_US3, 1106 .flags = IORESOURCE_IRQ, 1107 }, 1108}; 1109 1110static struct atmel_uart_data uart3_data = { 1111 .use_dma_tx = 1, 1112 .use_dma_rx = 1, 1113}; 1114 1115static u64 uart3_dmamask = DMA_BIT_MASK(32); 1116 1117static struct platform_device at91sam9rl_uart3_device = { 1118 .name = "atmel_usart", 1119 .id = 4, 1120 .dev = { 1121 .dma_mask = &uart3_dmamask, 1122 .coherent_dma_mask = DMA_BIT_MASK(32), 1123 .platform_data = &uart3_data, 1124 }, 1125 .resource = uart3_resources, 1126 .num_resources = ARRAY_SIZE(uart3_resources), 1127}; 1128 1129static inline void configure_usart3_pins(unsigned pins) 1130{ 1131 at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */ 1132 at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */ 1133 1134 if (pins & ATMEL_UART_RTS) 1135 at91_set_B_periph(AT91_PIN_PD4, 0); /* RTS3 */ 1136 if (pins & ATMEL_UART_CTS) 1137 at91_set_B_periph(AT91_PIN_PD3, 0); /* CTS3 */ 1138} 1139 1140static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ 1141struct platform_device *atmel_default_console_device; /* the serial console device */ 1142 1143void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) 1144{ 1145 struct platform_device *pdev; 1146 1147 switch (id) { 1148 case 0: /* DBGU */ 1149 pdev = &at91sam9rl_dbgu_device; 1150 configure_dbgu_pins(); 1151 at91_clock_associate("mck", &pdev->dev, "usart"); 1152 break; 1153 case AT91SAM9RL_ID_US0: 1154 pdev = &at91sam9rl_uart0_device; 1155 configure_usart0_pins(pins); 1156 at91_clock_associate("usart0_clk", &pdev->dev, "usart"); 1157 break; 1158 case AT91SAM9RL_ID_US1: 1159 pdev = &at91sam9rl_uart1_device; 1160 configure_usart1_pins(pins); 1161 at91_clock_associate("usart1_clk", &pdev->dev, "usart"); 1162 break; 1163 case AT91SAM9RL_ID_US2: 1164 pdev = &at91sam9rl_uart2_device; 1165 configure_usart2_pins(pins); 1166 at91_clock_associate("usart2_clk", &pdev->dev, "usart"); 1167 break; 1168 case AT91SAM9RL_ID_US3: 1169 pdev = &at91sam9rl_uart3_device; 1170 configure_usart3_pins(pins); 1171 at91_clock_associate("usart3_clk", &pdev->dev, "usart"); 1172 break; 1173 default: 1174 return; 1175 } 1176 pdev->id = portnr; /* update to mapped ID */ 1177 1178 if (portnr < ATMEL_MAX_UART) 1179 at91_uarts[portnr] = pdev; 1180} 1181 1182void __init at91_set_serial_console(unsigned portnr) 1183{ 1184 if (portnr < ATMEL_MAX_UART) 1185 atmel_default_console_device = at91_uarts[portnr]; 1186} 1187 1188void __init at91_add_device_serial(void) 1189{ 1190 int i; 1191 1192 for (i = 0; i < ATMEL_MAX_UART; i++) { 1193 if (at91_uarts[i]) 1194 platform_device_register(at91_uarts[i]); 1195 } 1196 1197 if (!atmel_default_console_device) 1198 printk(KERN_INFO "AT91: No default serial console defined.\n"); 1199} 1200#else 1201void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} 1202void __init at91_set_serial_console(unsigned portnr) {} 1203void __init at91_add_device_serial(void) {} 1204#endif 1205 1206 1207/* -------------------------------------------------------------------- */ 1208 1209/* 1210 * These devices are always present and don't need any board-specific 1211 * setup. 1212 */ 1213static int __init at91_add_standard_devices(void) 1214{ 1215 at91_add_device_hdmac(); 1216 at91_add_device_rtc(); 1217 at91_add_device_rtt(); 1218 at91_add_device_watchdog(); 1219 at91_add_device_tc(); 1220 return 0; 1221} 1222 1223arch_initcall(at91_add_standard_devices); 1224