1/* 2 * arch/arm/mach-at91/at572d940hf_devices.c 3 * 4 * Copyright (C) 2008 Atmel Antonio R. Costa <costa.antonior@gmail.com> 5 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org> 6 * Copyright (C) 2005 David Brownell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 */ 23 24#include <asm/mach/arch.h> 25#include <asm/mach/map.h> 26 27#include <linux/dma-mapping.h> 28#include <linux/platform_device.h> 29 30#include <mach/board.h> 31#include <mach/gpio.h> 32#include <mach/at572d940hf.h> 33#include <mach/at572d940hf_matrix.h> 34#include <mach/at91sam9_smc.h> 35 36#include "generic.h" 37#include "sam9_smc.h" 38 39 40/* -------------------------------------------------------------------- 41 * USB Host 42 * -------------------------------------------------------------------- */ 43 44#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 45static u64 ohci_dmamask = DMA_BIT_MASK(32); 46static struct at91_usbh_data usbh_data; 47 48static struct resource usbh_resources[] = { 49 [0] = { 50 .start = AT572D940HF_UHP_BASE, 51 .end = AT572D940HF_UHP_BASE + SZ_1M - 1, 52 .flags = IORESOURCE_MEM, 53 }, 54 [1] = { 55 .start = AT572D940HF_ID_UHP, 56 .end = AT572D940HF_ID_UHP, 57 .flags = IORESOURCE_IRQ, 58 }, 59}; 60 61static struct platform_device at572d940hf_usbh_device = { 62 .name = "at91_ohci", 63 .id = -1, 64 .dev = { 65 .dma_mask = &ohci_dmamask, 66 .coherent_dma_mask = DMA_BIT_MASK(32), 67 .platform_data = &usbh_data, 68 }, 69 .resource = usbh_resources, 70 .num_resources = ARRAY_SIZE(usbh_resources), 71}; 72 73void __init at91_add_device_usbh(struct at91_usbh_data *data) 74{ 75 if (!data) 76 return; 77 78 usbh_data = *data; 79 platform_device_register(&at572d940hf_usbh_device); 80 81} 82#else 83void __init at91_add_device_usbh(struct at91_usbh_data *data) {} 84#endif 85 86 87/* -------------------------------------------------------------------- 88 * USB Device (Gadget) 89 * -------------------------------------------------------------------- */ 90 91#ifdef CONFIG_USB_GADGET_AT91 92static struct at91_udc_data udc_data; 93 94static struct resource udc_resources[] = { 95 [0] = { 96 .start = AT572D940HF_BASE_UDP, 97 .end = AT572D940HF_BASE_UDP + SZ_16K - 1, 98 .flags = IORESOURCE_MEM, 99 }, 100 [1] = { 101 .start = AT572D940HF_ID_UDP, 102 .end = AT572D940HF_ID_UDP, 103 .flags = IORESOURCE_IRQ, 104 }, 105}; 106 107static struct platform_device at572d940hf_udc_device = { 108 .name = "at91_udc", 109 .id = -1, 110 .dev = { 111 .platform_data = &udc_data, 112 }, 113 .resource = udc_resources, 114 .num_resources = ARRAY_SIZE(udc_resources), 115}; 116 117void __init at91_add_device_udc(struct at91_udc_data *data) 118{ 119 if (!data) 120 return; 121 122 if (data->vbus_pin) { 123 at91_set_gpio_input(data->vbus_pin, 0); 124 at91_set_deglitch(data->vbus_pin, 1); 125 } 126 127 /* Pullup pin is handled internally */ 128 129 udc_data = *data; 130 platform_device_register(&at572d940hf_udc_device); 131} 132#else 133void __init at91_add_device_udc(struct at91_udc_data *data) {} 134#endif 135 136 137/* -------------------------------------------------------------------- 138 * Ethernet 139 * -------------------------------------------------------------------- */ 140 141#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE) 142static u64 eth_dmamask = DMA_BIT_MASK(32); 143static struct at91_eth_data eth_data; 144 145static struct resource eth_resources[] = { 146 [0] = { 147 .start = AT572D940HF_BASE_EMAC, 148 .end = AT572D940HF_BASE_EMAC + SZ_16K - 1, 149 .flags = IORESOURCE_MEM, 150 }, 151 [1] = { 152 .start = AT572D940HF_ID_EMAC, 153 .end = AT572D940HF_ID_EMAC, 154 .flags = IORESOURCE_IRQ, 155 }, 156}; 157 158static struct platform_device at572d940hf_eth_device = { 159 .name = "macb", 160 .id = -1, 161 .dev = { 162 .dma_mask = ð_dmamask, 163 .coherent_dma_mask = DMA_BIT_MASK(32), 164 .platform_data = ð_data, 165 }, 166 .resource = eth_resources, 167 .num_resources = ARRAY_SIZE(eth_resources), 168}; 169 170void __init at91_add_device_eth(struct at91_eth_data *data) 171{ 172 if (!data) 173 return; 174 175 if (data->phy_irq_pin) { 176 at91_set_gpio_input(data->phy_irq_pin, 0); 177 at91_set_deglitch(data->phy_irq_pin, 1); 178 } 179 180 /* Only RMII is supported */ 181 data->is_rmii = 1; 182 183 /* Pins used for RMII */ 184 at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXCK_EREFCK */ 185 at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */ 186 at91_set_A_periph(AT91_PIN_PA18, 0); /* ERX0 */ 187 at91_set_A_periph(AT91_PIN_PA19, 0); /* ERX1 */ 188 at91_set_A_periph(AT91_PIN_PA20, 0); /* ERXER */ 189 at91_set_A_periph(AT91_PIN_PA23, 0); /* ETXEN */ 190 at91_set_A_periph(AT91_PIN_PA21, 0); /* ETX0 */ 191 at91_set_A_periph(AT91_PIN_PA22, 0); /* ETX1 */ 192 at91_set_A_periph(AT91_PIN_PA13, 0); /* EMDIO */ 193 at91_set_A_periph(AT91_PIN_PA14, 0); /* EMDC */ 194 195 eth_data = *data; 196 platform_device_register(&at572d940hf_eth_device); 197} 198#else 199void __init at91_add_device_eth(struct at91_eth_data *data) {} 200#endif 201 202 203/* -------------------------------------------------------------------- 204 * MMC / SD 205 * -------------------------------------------------------------------- */ 206 207#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE) 208static u64 mmc_dmamask = DMA_BIT_MASK(32); 209static struct at91_mmc_data mmc_data; 210 211static struct resource mmc_resources[] = { 212 [0] = { 213 .start = AT572D940HF_BASE_MCI, 214 .end = AT572D940HF_BASE_MCI + SZ_16K - 1, 215 .flags = IORESOURCE_MEM, 216 }, 217 [1] = { 218 .start = AT572D940HF_ID_MCI, 219 .end = AT572D940HF_ID_MCI, 220 .flags = IORESOURCE_IRQ, 221 }, 222}; 223 224static struct platform_device at572d940hf_mmc_device = { 225 .name = "at91_mci", 226 .id = -1, 227 .dev = { 228 .dma_mask = &mmc_dmamask, 229 .coherent_dma_mask = DMA_BIT_MASK(32), 230 .platform_data = &mmc_data, 231 }, 232 .resource = mmc_resources, 233 .num_resources = ARRAY_SIZE(mmc_resources), 234}; 235 236void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) 237{ 238 if (!data) 239 return; 240 241 /* input/irq */ 242 if (data->det_pin) { 243 at91_set_gpio_input(data->det_pin, 1); 244 at91_set_deglitch(data->det_pin, 1); 245 } 246 if (data->wp_pin) 247 at91_set_gpio_input(data->wp_pin, 1); 248 if (data->vcc_pin) 249 at91_set_gpio_output(data->vcc_pin, 0); 250 251 /* CLK */ 252 at91_set_A_periph(AT91_PIN_PC22, 0); 253 254 /* CMD */ 255 at91_set_A_periph(AT91_PIN_PC23, 1); 256 257 /* DAT0, maybe DAT1..DAT3 */ 258 at91_set_A_periph(AT91_PIN_PC24, 1); 259 if (data->wire4) { 260 at91_set_A_periph(AT91_PIN_PC25, 1); 261 at91_set_A_periph(AT91_PIN_PC26, 1); 262 at91_set_A_periph(AT91_PIN_PC27, 1); 263 } 264 265 mmc_data = *data; 266 platform_device_register(&at572d940hf_mmc_device); 267} 268#else 269void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {} 270#endif 271 272 273/* -------------------------------------------------------------------- 274 * NAND / SmartMedia 275 * -------------------------------------------------------------------- */ 276 277#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE) 278static struct atmel_nand_data nand_data; 279 280#define NAND_BASE AT91_CHIPSELECT_3 281 282static struct resource nand_resources[] = { 283 { 284 .start = NAND_BASE, 285 .end = NAND_BASE + SZ_256M - 1, 286 .flags = IORESOURCE_MEM, 287 } 288}; 289 290static struct platform_device at572d940hf_nand_device = { 291 .name = "atmel_nand", 292 .id = -1, 293 .dev = { 294 .platform_data = &nand_data, 295 }, 296 .resource = nand_resources, 297 .num_resources = ARRAY_SIZE(nand_resources), 298}; 299 300void __init at91_add_device_nand(struct atmel_nand_data *data) 301{ 302 unsigned long csa; 303 304 if (!data) 305 return; 306 307 csa = at91_sys_read(AT91_MATRIX_EBICSA); 308 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 309 310 /* enable pin */ 311 if (data->enable_pin) 312 at91_set_gpio_output(data->enable_pin, 1); 313 314 /* ready/busy pin */ 315 if (data->rdy_pin) 316 at91_set_gpio_input(data->rdy_pin, 1); 317 318 /* card detect pin */ 319 if (data->det_pin) 320 at91_set_gpio_input(data->det_pin, 1); 321 322 at91_set_A_periph(AT91_PIN_PB28, 0); /* A[22] */ 323 at91_set_B_periph(AT91_PIN_PA28, 0); /* NANDOE */ 324 at91_set_B_periph(AT91_PIN_PA29, 0); /* NANDWE */ 325 326 nand_data = *data; 327 platform_device_register(&at572d940hf_nand_device); 328} 329 330#else 331void __init at91_add_device_nand(struct atmel_nand_data *data) {} 332#endif 333 334 335/* -------------------------------------------------------------------- 336 * TWI (i2c) 337 * -------------------------------------------------------------------- */ 338 339/* 340 * Prefer the GPIO code since the TWI controller isn't robust 341 * (gets overruns and underruns under load) and can only issue 342 * repeated STARTs in one scenario (the driver doesn't yet handle them). 343 */ 344 345#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) 346 347static struct i2c_gpio_platform_data pdata = { 348 .sda_pin = AT91_PIN_PC7, 349 .sda_is_open_drain = 1, 350 .scl_pin = AT91_PIN_PC8, 351 .scl_is_open_drain = 1, 352 .udelay = 2, /* ~100 kHz */ 353}; 354 355static struct platform_device at572d940hf_twi_device { 356 .name = "i2c-gpio", 357 .id = -1, 358 .dev.platform_data = &pdata, 359}; 360 361void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) 362{ 363 at91_set_GPIO_periph(AT91_PIN_PC7, 1); /* TWD (SDA) */ 364 at91_set_multi_drive(AT91_PIN_PC7, 1); 365 366 at91_set_GPIO_periph(AT91_PIN_PA8, 1); /* TWCK (SCL) */ 367 at91_set_multi_drive(AT91_PIN_PC8, 1); 368 369 i2c_register_board_info(0, devices, nr_devices); 370 platform_device_register(&at572d940hf_twi_device); 371} 372 373#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE) 374 375static struct resource twi0_resources[] = { 376 [0] = { 377 .start = AT572D940HF_BASE_TWI0, 378 .end = AT572D940HF_BASE_TWI0 + SZ_16K - 1, 379 .flags = IORESOURCE_MEM, 380 }, 381 [1] = { 382 .start = AT572D940HF_ID_TWI0, 383 .end = AT572D940HF_ID_TWI0, 384 .flags = IORESOURCE_IRQ, 385 }, 386}; 387 388static struct platform_device at572d940hf_twi0_device = { 389 .name = "at91_i2c", 390 .id = 0, 391 .resource = twi0_resources, 392 .num_resources = ARRAY_SIZE(twi0_resources), 393}; 394 395static struct resource twi1_resources[] = { 396 [0] = { 397 .start = AT572D940HF_BASE_TWI1, 398 .end = AT572D940HF_BASE_TWI1 + SZ_16K - 1, 399 .flags = IORESOURCE_MEM, 400 }, 401 [1] = { 402 .start = AT572D940HF_ID_TWI1, 403 .end = AT572D940HF_ID_TWI1, 404 .flags = IORESOURCE_IRQ, 405 }, 406}; 407 408static struct platform_device at572d940hf_twi1_device = { 409 .name = "at91_i2c", 410 .id = 1, 411 .resource = twi1_resources, 412 .num_resources = ARRAY_SIZE(twi1_resources), 413}; 414 415void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) 416{ 417 /* pins used for TWI0 interface */ 418 at91_set_A_periph(AT91_PIN_PC7, 0); /* TWD */ 419 at91_set_multi_drive(AT91_PIN_PC7, 1); 420 421 at91_set_A_periph(AT91_PIN_PC8, 0); /* TWCK */ 422 at91_set_multi_drive(AT91_PIN_PC8, 1); 423 424 /* pins used for TWI1 interface */ 425 at91_set_A_periph(AT91_PIN_PC20, 0); /* TWD */ 426 at91_set_multi_drive(AT91_PIN_PC20, 1); 427 428 at91_set_A_periph(AT91_PIN_PC21, 0); /* TWCK */ 429 at91_set_multi_drive(AT91_PIN_PC21, 1); 430 431 i2c_register_board_info(0, devices, nr_devices); 432 platform_device_register(&at572d940hf_twi0_device); 433 platform_device_register(&at572d940hf_twi1_device); 434} 435#else 436void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {} 437#endif 438 439 440/* -------------------------------------------------------------------- 441 * SPI 442 * -------------------------------------------------------------------- */ 443 444#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) 445static u64 spi_dmamask = DMA_BIT_MASK(32); 446 447static struct resource spi0_resources[] = { 448 [0] = { 449 .start = AT572D940HF_BASE_SPI0, 450 .end = AT572D940HF_BASE_SPI0 + SZ_16K - 1, 451 .flags = IORESOURCE_MEM, 452 }, 453 [1] = { 454 .start = AT572D940HF_ID_SPI0, 455 .end = AT572D940HF_ID_SPI0, 456 .flags = IORESOURCE_IRQ, 457 }, 458}; 459 460static struct platform_device at572d940hf_spi0_device = { 461 .name = "atmel_spi", 462 .id = 0, 463 .dev = { 464 .dma_mask = &spi_dmamask, 465 .coherent_dma_mask = DMA_BIT_MASK(32), 466 }, 467 .resource = spi0_resources, 468 .num_resources = ARRAY_SIZE(spi0_resources), 469}; 470 471static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 }; 472 473static struct resource spi1_resources[] = { 474 [0] = { 475 .start = AT572D940HF_BASE_SPI1, 476 .end = AT572D940HF_BASE_SPI1 + SZ_16K - 1, 477 .flags = IORESOURCE_MEM, 478 }, 479 [1] = { 480 .start = AT572D940HF_ID_SPI1, 481 .end = AT572D940HF_ID_SPI1, 482 .flags = IORESOURCE_IRQ, 483 }, 484}; 485 486static struct platform_device at572d940hf_spi1_device = { 487 .name = "atmel_spi", 488 .id = 1, 489 .dev = { 490 .dma_mask = &spi_dmamask, 491 .coherent_dma_mask = DMA_BIT_MASK(32), 492 }, 493 .resource = spi1_resources, 494 .num_resources = ARRAY_SIZE(spi1_resources), 495}; 496 497static const unsigned spi1_standard_cs[4] = { AT91_PIN_PC3, AT91_PIN_PC4, AT91_PIN_PC5, AT91_PIN_PC6 }; 498 499void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) 500{ 501 int i; 502 unsigned long cs_pin; 503 short enable_spi0 = 0; 504 short enable_spi1 = 0; 505 506 /* Choose SPI chip-selects */ 507 for (i = 0; i < nr_devices; i++) { 508 if (devices[i].controller_data) 509 cs_pin = (unsigned long) devices[i].controller_data; 510 else if (devices[i].bus_num == 0) 511 cs_pin = spi0_standard_cs[devices[i].chip_select]; 512 else 513 cs_pin = spi1_standard_cs[devices[i].chip_select]; 514 515 if (devices[i].bus_num == 0) 516 enable_spi0 = 1; 517 else 518 enable_spi1 = 1; 519 520 /* enable chip-select pin */ 521 at91_set_gpio_output(cs_pin, 1); 522 523 /* pass chip-select pin to driver */ 524 devices[i].controller_data = (void *) cs_pin; 525 } 526 527 spi_register_board_info(devices, nr_devices); 528 529 /* Configure SPI bus(es) */ 530 if (enable_spi0) { 531 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ 532 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ 533 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ 534 535 at91_clock_associate("spi0_clk", &at572d940hf_spi0_device.dev, "spi_clk"); 536 platform_device_register(&at572d940hf_spi0_device); 537 } 538 if (enable_spi1) { 539 at91_set_A_periph(AT91_PIN_PC0, 0); /* SPI1_MISO */ 540 at91_set_A_periph(AT91_PIN_PC1, 0); /* SPI1_MOSI */ 541 at91_set_A_periph(AT91_PIN_PC2, 0); /* SPI1_SPCK */ 542 543 at91_clock_associate("spi1_clk", &at572d940hf_spi1_device.dev, "spi_clk"); 544 platform_device_register(&at572d940hf_spi1_device); 545 } 546} 547#else 548void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {} 549#endif 550 551 552/* -------------------------------------------------------------------- 553 * Timer/Counter blocks 554 * -------------------------------------------------------------------- */ 555 556#ifdef CONFIG_ATMEL_TCLIB 557 558static struct resource tcb_resources[] = { 559 [0] = { 560 .start = AT572D940HF_BASE_TCB, 561 .end = AT572D940HF_BASE_TCB + SZ_16K - 1, 562 .flags = IORESOURCE_MEM, 563 }, 564 [1] = { 565 .start = AT572D940HF_ID_TC0, 566 .end = AT572D940HF_ID_TC0, 567 .flags = IORESOURCE_IRQ, 568 }, 569 [2] = { 570 .start = AT572D940HF_ID_TC1, 571 .end = AT572D940HF_ID_TC1, 572 .flags = IORESOURCE_IRQ, 573 }, 574 [3] = { 575 .start = AT572D940HF_ID_TC2, 576 .end = AT572D940HF_ID_TC2, 577 .flags = IORESOURCE_IRQ, 578 }, 579}; 580 581static struct platform_device at572d940hf_tcb_device = { 582 .name = "atmel_tcb", 583 .id = 0, 584 .resource = tcb_resources, 585 .num_resources = ARRAY_SIZE(tcb_resources), 586}; 587 588static void __init at91_add_device_tc(void) 589{ 590 /* this chip has a separate clock and irq for each TC channel */ 591 at91_clock_associate("tc0_clk", &at572d940hf_tcb_device.dev, "t0_clk"); 592 at91_clock_associate("tc1_clk", &at572d940hf_tcb_device.dev, "t1_clk"); 593 at91_clock_associate("tc2_clk", &at572d940hf_tcb_device.dev, "t2_clk"); 594 platform_device_register(&at572d940hf_tcb_device); 595} 596#else 597static void __init at91_add_device_tc(void) { } 598#endif 599 600 601/* -------------------------------------------------------------------- 602 * RTT 603 * -------------------------------------------------------------------- */ 604 605static struct resource rtt_resources[] = { 606 { 607 .start = AT91_BASE_SYS + AT91_RTT, 608 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1, 609 .flags = IORESOURCE_MEM, 610 } 611}; 612 613static struct platform_device at572d940hf_rtt_device = { 614 .name = "at91_rtt", 615 .id = 0, 616 .resource = rtt_resources, 617 .num_resources = ARRAY_SIZE(rtt_resources), 618}; 619 620static void __init at91_add_device_rtt(void) 621{ 622 platform_device_register(&at572d940hf_rtt_device); 623} 624 625 626/* -------------------------------------------------------------------- 627 * Watchdog 628 * -------------------------------------------------------------------- */ 629 630#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE) 631static struct platform_device at572d940hf_wdt_device = { 632 .name = "at91_wdt", 633 .id = -1, 634 .num_resources = 0, 635}; 636 637static void __init at91_add_device_watchdog(void) 638{ 639 platform_device_register(&at572d940hf_wdt_device); 640} 641#else 642static void __init at91_add_device_watchdog(void) {} 643#endif 644 645 646/* -------------------------------------------------------------------- 647 * UART 648 * -------------------------------------------------------------------- */ 649 650#if defined(CONFIG_SERIAL_ATMEL) 651static struct resource dbgu_resources[] = { 652 [0] = { 653 .start = AT91_VA_BASE_SYS + AT91_DBGU, 654 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1, 655 .flags = IORESOURCE_MEM, 656 }, 657 [1] = { 658 .start = AT91_ID_SYS, 659 .end = AT91_ID_SYS, 660 .flags = IORESOURCE_IRQ, 661 }, 662}; 663 664static struct atmel_uart_data dbgu_data = { 665 .use_dma_tx = 0, 666 .use_dma_rx = 0, /* DBGU not capable of receive DMA */ 667 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU), 668}; 669 670static u64 dbgu_dmamask = DMA_BIT_MASK(32); 671 672static struct platform_device at572d940hf_dbgu_device = { 673 .name = "atmel_usart", 674 .id = 0, 675 .dev = { 676 .dma_mask = &dbgu_dmamask, 677 .coherent_dma_mask = DMA_BIT_MASK(32), 678 .platform_data = &dbgu_data, 679 }, 680 .resource = dbgu_resources, 681 .num_resources = ARRAY_SIZE(dbgu_resources), 682}; 683 684static inline void configure_dbgu_pins(void) 685{ 686 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */ 687 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */ 688} 689 690static struct resource uart0_resources[] = { 691 [0] = { 692 .start = AT572D940HF_BASE_US0, 693 .end = AT572D940HF_BASE_US0 + SZ_16K - 1, 694 .flags = IORESOURCE_MEM, 695 }, 696 [1] = { 697 .start = AT572D940HF_ID_US0, 698 .end = AT572D940HF_ID_US0, 699 .flags = IORESOURCE_IRQ, 700 }, 701}; 702 703static struct atmel_uart_data uart0_data = { 704 .use_dma_tx = 1, 705 .use_dma_rx = 1, 706}; 707 708static u64 uart0_dmamask = DMA_BIT_MASK(32); 709 710static struct platform_device at572d940hf_uart0_device = { 711 .name = "atmel_usart", 712 .id = 1, 713 .dev = { 714 .dma_mask = &uart0_dmamask, 715 .coherent_dma_mask = DMA_BIT_MASK(32), 716 .platform_data = &uart0_data, 717 }, 718 .resource = uart0_resources, 719 .num_resources = ARRAY_SIZE(uart0_resources), 720}; 721 722static inline void configure_usart0_pins(unsigned pins) 723{ 724 at91_set_A_periph(AT91_PIN_PA8, 1); /* TXD0 */ 725 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */ 726 727 if (pins & ATMEL_UART_RTS) 728 at91_set_A_periph(AT91_PIN_PA10, 0); /* RTS0 */ 729 if (pins & ATMEL_UART_CTS) 730 at91_set_A_periph(AT91_PIN_PA9, 0); /* CTS0 */ 731} 732 733static struct resource uart1_resources[] = { 734 [0] = { 735 .start = AT572D940HF_BASE_US1, 736 .end = AT572D940HF_BASE_US1 + SZ_16K - 1, 737 .flags = IORESOURCE_MEM, 738 }, 739 [1] = { 740 .start = AT572D940HF_ID_US1, 741 .end = AT572D940HF_ID_US1, 742 .flags = IORESOURCE_IRQ, 743 }, 744}; 745 746static struct atmel_uart_data uart1_data = { 747 .use_dma_tx = 1, 748 .use_dma_rx = 1, 749}; 750 751static u64 uart1_dmamask = DMA_BIT_MASK(32); 752 753static struct platform_device at572d940hf_uart1_device = { 754 .name = "atmel_usart", 755 .id = 2, 756 .dev = { 757 .dma_mask = &uart1_dmamask, 758 .coherent_dma_mask = DMA_BIT_MASK(32), 759 .platform_data = &uart1_data, 760 }, 761 .resource = uart1_resources, 762 .num_resources = ARRAY_SIZE(uart1_resources), 763}; 764 765static inline void configure_usart1_pins(unsigned pins) 766{ 767 at91_set_A_periph(AT91_PIN_PC10, 1); /* TXD1 */ 768 at91_set_A_periph(AT91_PIN_PC9 , 0); /* RXD1 */ 769 770 if (pins & ATMEL_UART_RTS) 771 at91_set_A_periph(AT91_PIN_PC12, 0); /* RTS1 */ 772 if (pins & ATMEL_UART_CTS) 773 at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS1 */ 774} 775 776static struct resource uart2_resources[] = { 777 [0] = { 778 .start = AT572D940HF_BASE_US2, 779 .end = AT572D940HF_BASE_US2 + SZ_16K - 1, 780 .flags = IORESOURCE_MEM, 781 }, 782 [1] = { 783 .start = AT572D940HF_ID_US2, 784 .end = AT572D940HF_ID_US2, 785 .flags = IORESOURCE_IRQ, 786 }, 787}; 788 789static struct atmel_uart_data uart2_data = { 790 .use_dma_tx = 1, 791 .use_dma_rx = 1, 792}; 793 794static u64 uart2_dmamask = DMA_BIT_MASK(32); 795 796static struct platform_device at572d940hf_uart2_device = { 797 .name = "atmel_usart", 798 .id = 3, 799 .dev = { 800 .dma_mask = &uart2_dmamask, 801 .coherent_dma_mask = DMA_BIT_MASK(32), 802 .platform_data = &uart2_data, 803 }, 804 .resource = uart2_resources, 805 .num_resources = ARRAY_SIZE(uart2_resources), 806}; 807 808static inline void configure_usart2_pins(unsigned pins) 809{ 810 at91_set_A_periph(AT91_PIN_PC15, 1); /* TXD2 */ 811 at91_set_A_periph(AT91_PIN_PC14, 0); /* RXD2 */ 812 813 if (pins & ATMEL_UART_RTS) 814 at91_set_A_periph(AT91_PIN_PC17, 0); /* RTS2 */ 815 if (pins & ATMEL_UART_CTS) 816 at91_set_A_periph(AT91_PIN_PC16, 0); /* CTS2 */ 817} 818 819static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ 820struct platform_device *atmel_default_console_device; /* the serial console device */ 821 822void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) 823{ 824 struct platform_device *pdev; 825 826 switch (id) { 827 case 0: /* DBGU */ 828 pdev = &at572d940hf_dbgu_device; 829 configure_dbgu_pins(); 830 at91_clock_associate("mck", &pdev->dev, "usart"); 831 break; 832 case AT572D940HF_ID_US0: 833 pdev = &at572d940hf_uart0_device; 834 configure_usart0_pins(pins); 835 at91_clock_associate("usart0_clk", &pdev->dev, "usart"); 836 break; 837 case AT572D940HF_ID_US1: 838 pdev = &at572d940hf_uart1_device; 839 configure_usart1_pins(pins); 840 at91_clock_associate("usart1_clk", &pdev->dev, "usart"); 841 break; 842 case AT572D940HF_ID_US2: 843 pdev = &at572d940hf_uart2_device; 844 configure_usart2_pins(pins); 845 at91_clock_associate("usart2_clk", &pdev->dev, "usart"); 846 break; 847 default: 848 return; 849 } 850 pdev->id = portnr; /* update to mapped ID */ 851 852 if (portnr < ATMEL_MAX_UART) 853 at91_uarts[portnr] = pdev; 854} 855 856void __init at91_set_serial_console(unsigned portnr) 857{ 858 if (portnr < ATMEL_MAX_UART) 859 atmel_default_console_device = at91_uarts[portnr]; 860} 861 862void __init at91_add_device_serial(void) 863{ 864 int i; 865 866 for (i = 0; i < ATMEL_MAX_UART; i++) { 867 if (at91_uarts[i]) 868 platform_device_register(at91_uarts[i]); 869 } 870 871 if (!atmel_default_console_device) 872 printk(KERN_INFO "AT91: No default serial console defined.\n"); 873} 874 875#else 876void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} 877void __init at91_set_serial_console(unsigned portnr) {} 878void __init at91_add_device_serial(void) {} 879#endif 880 881 882/* -------------------------------------------------------------------- 883 * mAgic 884 * -------------------------------------------------------------------- */ 885 886#ifdef CONFIG_MAGICV 887static struct resource mAgic_resources[] = { 888 { 889 .start = AT91_MAGIC_PM_BASE, 890 .end = AT91_MAGIC_PM_BASE + AT91_MAGIC_PM_SIZE - 1, 891 .flags = IORESOURCE_MEM, 892 }, 893 { 894 .start = AT91_MAGIC_DM_I_BASE, 895 .end = AT91_MAGIC_DM_I_BASE + AT91_MAGIC_DM_I_SIZE - 1, 896 .flags = IORESOURCE_MEM, 897 }, 898 { 899 .start = AT91_MAGIC_DM_F_BASE, 900 .end = AT91_MAGIC_DM_F_BASE + AT91_MAGIC_DM_F_SIZE - 1, 901 .flags = IORESOURCE_MEM, 902 }, 903 { 904 .start = AT91_MAGIC_DM_DB_BASE, 905 .end = AT91_MAGIC_DM_DB_BASE + AT91_MAGIC_DM_DB_SIZE - 1, 906 .flags = IORESOURCE_MEM, 907 }, 908 { 909 .start = AT91_MAGIC_REGS_BASE, 910 .end = AT91_MAGIC_REGS_BASE + AT91_MAGIC_REGS_SIZE - 1, 911 .flags = IORESOURCE_MEM, 912 }, 913 { 914 .start = AT91_MAGIC_EXTPAGE_BASE, 915 .end = AT91_MAGIC_EXTPAGE_BASE + AT91_MAGIC_EXTPAGE_SIZE - 1, 916 .flags = IORESOURCE_MEM, 917 }, 918 { 919 .start = AT572D940HF_ID_MSIRQ0, 920 .end = AT572D940HF_ID_MSIRQ0, 921 .flags = IORESOURCE_IRQ, 922 }, 923 { 924 .start = AT572D940HF_ID_MHALT, 925 .end = AT572D940HF_ID_MHALT, 926 .flags = IORESOURCE_IRQ, 927 }, 928 { 929 .start = AT572D940HF_ID_MEXC, 930 .end = AT572D940HF_ID_MEXC, 931 .flags = IORESOURCE_IRQ, 932 }, 933 { 934 .start = AT572D940HF_ID_MEDMA, 935 .end = AT572D940HF_ID_MEDMA, 936 .flags = IORESOURCE_IRQ, 937 }, 938}; 939 940static struct platform_device mAgic_device = { 941 .name = "mAgic", 942 .id = -1, 943 .num_resources = ARRAY_SIZE(mAgic_resources), 944 .resource = mAgic_resources, 945}; 946 947void __init at91_add_device_mAgic(void) 948{ 949 platform_device_register(&mAgic_device); 950} 951#else 952void __init at91_add_device_mAgic(void) {} 953#endif 954 955 956/* -------------------------------------------------------------------- */ 957 958/* 959 * These devices are always present and don't need any board-specific 960 * setup. 961 */ 962static int __init at91_add_standard_devices(void) 963{ 964 at91_add_device_rtt(); 965 at91_add_device_watchdog(); 966 at91_add_device_tc(); 967 return 0; 968} 969 970arch_initcall(at91_add_standard_devices); 971