1#ifndef __ALPHA_LCA__H__ 2#define __ALPHA_LCA__H__ 3 4#include <asm/system.h> 5#include <asm/compiler.h> 6 7/* 8 * Low Cost Alpha (LCA) definitions (these apply to 21066 and 21068, 9 * for example). 10 * 11 * This file is based on: 12 * 13 * DECchip 21066 and DECchip 21068 Alpha AXP Microprocessors 14 * Hardware Reference Manual; Digital Equipment Corp.; May 1994; 15 * Maynard, MA; Order Number: EC-N2681-71. 16 */ 17 18/* 19 * NOTE: The LCA uses a Host Address Extension (HAE) register to access 20 * PCI addresses that are beyond the first 27 bits of address 21 * space. Updating the HAE requires an external cycle (and 22 * a memory barrier), which tends to be slow. Instead of updating 23 * it on each sparse memory access, we keep the current HAE value 24 * cached in variable cache_hae. Only if the cached HAE differs 25 * from the desired HAE value do we actually updated HAE register. 26 * The HAE register is preserved by the interrupt handler entry/exit 27 * code, so this scheme works even in the presence of interrupts. 28 * 29 * Dense memory space doesn't require the HAE, but is restricted to 30 * aligned 32 and 64 bit accesses. Special Cycle and Interrupt 31 * Acknowledge cycles may also require the use of the HAE. The LCA 32 * limits I/O address space to the bottom 24 bits of address space, 33 * but this easily covers the 16 bit ISA I/O address space. 34 */ 35 36/* 37 * NOTE 2! The memory operations do not set any memory barriers, as 38 * it's not needed for cases like a frame buffer that is essentially 39 * memory-like. You need to do them by hand if the operations depend 40 * on ordering. 41 * 42 * Similarly, the port I/O operations do a "mb" only after a write 43 * operation: if an mb is needed before (as in the case of doing 44 * memory mapped I/O first, and then a port I/O operation to the same 45 * device), it needs to be done by hand. 46 * 47 * After the above has bitten me 100 times, I'll give up and just do 48 * the mb all the time, but right now I'm hoping this will work out. 49 * Avoiding mb's may potentially be a noticeable speed improvement, 50 * but I can't honestly say I've tested it. 51 * 52 * Handling interrupts that need to do mb's to synchronize to 53 * non-interrupts is another fun race area. Don't do it (because if 54 * you do, I'll have to do *everything* with interrupts disabled, 55 * ugh). 56 */ 57 58/* 59 * Memory Controller registers: 60 */ 61#define LCA_MEM_BCR0 (IDENT_ADDR + 0x120000000UL) 62#define LCA_MEM_BCR1 (IDENT_ADDR + 0x120000008UL) 63#define LCA_MEM_BCR2 (IDENT_ADDR + 0x120000010UL) 64#define LCA_MEM_BCR3 (IDENT_ADDR + 0x120000018UL) 65#define LCA_MEM_BMR0 (IDENT_ADDR + 0x120000020UL) 66#define LCA_MEM_BMR1 (IDENT_ADDR + 0x120000028UL) 67#define LCA_MEM_BMR2 (IDENT_ADDR + 0x120000030UL) 68#define LCA_MEM_BMR3 (IDENT_ADDR + 0x120000038UL) 69#define LCA_MEM_BTR0 (IDENT_ADDR + 0x120000040UL) 70#define LCA_MEM_BTR1 (IDENT_ADDR + 0x120000048UL) 71#define LCA_MEM_BTR2 (IDENT_ADDR + 0x120000050UL) 72#define LCA_MEM_BTR3 (IDENT_ADDR + 0x120000058UL) 73#define LCA_MEM_GTR (IDENT_ADDR + 0x120000060UL) 74#define LCA_MEM_ESR (IDENT_ADDR + 0x120000068UL) 75#define LCA_MEM_EAR (IDENT_ADDR + 0x120000070UL) 76#define LCA_MEM_CAR (IDENT_ADDR + 0x120000078UL) 77#define LCA_MEM_VGR (IDENT_ADDR + 0x120000080UL) 78#define LCA_MEM_PLM (IDENT_ADDR + 0x120000088UL) 79#define LCA_MEM_FOR (IDENT_ADDR + 0x120000090UL) 80 81/* 82 * I/O Controller registers: 83 */ 84#define LCA_IOC_HAE (IDENT_ADDR + 0x180000000UL) 85#define LCA_IOC_CONF (IDENT_ADDR + 0x180000020UL) 86#define LCA_IOC_STAT0 (IDENT_ADDR + 0x180000040UL) 87#define LCA_IOC_STAT1 (IDENT_ADDR + 0x180000060UL) 88#define LCA_IOC_TBIA (IDENT_ADDR + 0x180000080UL) 89#define LCA_IOC_TB_ENA (IDENT_ADDR + 0x1800000a0UL) 90#define LCA_IOC_SFT_RST (IDENT_ADDR + 0x1800000c0UL) 91#define LCA_IOC_PAR_DIS (IDENT_ADDR + 0x1800000e0UL) 92#define LCA_IOC_W_BASE0 (IDENT_ADDR + 0x180000100UL) 93#define LCA_IOC_W_BASE1 (IDENT_ADDR + 0x180000120UL) 94#define LCA_IOC_W_MASK0 (IDENT_ADDR + 0x180000140UL) 95#define LCA_IOC_W_MASK1 (IDENT_ADDR + 0x180000160UL) 96#define LCA_IOC_T_BASE0 (IDENT_ADDR + 0x180000180UL) 97#define LCA_IOC_T_BASE1 (IDENT_ADDR + 0x1800001a0UL) 98#define LCA_IOC_TB_TAG0 (IDENT_ADDR + 0x188000000UL) 99#define LCA_IOC_TB_TAG1 (IDENT_ADDR + 0x188000020UL) 100#define LCA_IOC_TB_TAG2 (IDENT_ADDR + 0x188000040UL) 101#define LCA_IOC_TB_TAG3 (IDENT_ADDR + 0x188000060UL) 102#define LCA_IOC_TB_TAG4 (IDENT_ADDR + 0x188000070UL) 103#define LCA_IOC_TB_TAG5 (IDENT_ADDR + 0x1880000a0UL) 104#define LCA_IOC_TB_TAG6 (IDENT_ADDR + 0x1880000c0UL) 105#define LCA_IOC_TB_TAG7 (IDENT_ADDR + 0x1880000e0UL) 106 107/* 108 * Memory spaces: 109 */ 110#define LCA_IACK_SC (IDENT_ADDR + 0x1a0000000UL) 111#define LCA_CONF (IDENT_ADDR + 0x1e0000000UL) 112#define LCA_IO (IDENT_ADDR + 0x1c0000000UL) 113#define LCA_SPARSE_MEM (IDENT_ADDR + 0x200000000UL) 114#define LCA_DENSE_MEM (IDENT_ADDR + 0x300000000UL) 115 116/* 117 * Bit definitions for I/O Controller status register 0: 118 */ 119#define LCA_IOC_STAT0_CMD 0xf 120#define LCA_IOC_STAT0_ERR (1<<4) 121#define LCA_IOC_STAT0_LOST (1<<5) 122#define LCA_IOC_STAT0_THIT (1<<6) 123#define LCA_IOC_STAT0_TREF (1<<7) 124#define LCA_IOC_STAT0_CODE_SHIFT 8 125#define LCA_IOC_STAT0_CODE_MASK 0x7 126#define LCA_IOC_STAT0_P_NBR_SHIFT 13 127#define LCA_IOC_STAT0_P_NBR_MASK 0x7ffff 128 129#define LCA_HAE_ADDRESS LCA_IOC_HAE 130 131/* LCA PMR Power Management register defines */ 132#define LCA_PMR_ADDR (IDENT_ADDR + 0x120000098UL) 133#define LCA_PMR_PDIV 0x7 /* Primary clock divisor */ 134#define LCA_PMR_ODIV 0x38 /* Override clock divisor */ 135#define LCA_PMR_INTO 0x40 /* Interrupt override */ 136#define LCA_PMR_DMAO 0x80 /* DMA override */ 137#define LCA_PMR_OCCEB 0xffff0000L /* Override cycle counter - even bits */ 138#define LCA_PMR_OCCOB 0xffff000000000000L /* Override cycle counter - even bits */ 139#define LCA_PMR_PRIMARY_MASK 0xfffffffffffffff8L 140 141/* LCA PMR Macros */ 142 143#define LCA_READ_PMR (*(volatile unsigned long *)LCA_PMR_ADDR) 144#define LCA_WRITE_PMR(d) (*((volatile unsigned long *)LCA_PMR_ADDR) = (d)) 145 146#define LCA_GET_PRIMARY(r) ((r) & LCA_PMR_PDIV) 147#define LCA_GET_OVERRIDE(r) (((r) >> 3) & LCA_PMR_PDIV) 148#define LCA_SET_PRIMARY_CLOCK(r, c) ((r) = (((r) & LCA_PMR_PRIMARY_MASK)|(c))) 149 150/* LCA PMR Divisor values */ 151#define LCA_PMR_DIV_1 0x0 152#define LCA_PMR_DIV_1_5 0x1 153#define LCA_PMR_DIV_2 0x2 154#define LCA_PMR_DIV_4 0x3 155#define LCA_PMR_DIV_8 0x4 156#define LCA_PMR_DIV_16 0x5 157#define LCA_PMR_DIV_MIN DIV_1 158#define LCA_PMR_DIV_MAX DIV_16 159 160 161/* 162 * Data structure for handling LCA machine checks. Correctable errors 163 * result in a short logout frame, uncorrectable ones in a long one. 164 */ 165struct el_lca_mcheck_short { 166 struct el_common h; /* common logout header */ 167 unsigned long esr; /* error-status register */ 168 unsigned long ear; /* error-address register */ 169 unsigned long dc_stat; /* dcache status register */ 170 unsigned long ioc_stat0; /* I/O controller status register 0 */ 171 unsigned long ioc_stat1; /* I/O controller status register 1 */ 172}; 173 174struct el_lca_mcheck_long { 175 struct el_common h; /* common logout header */ 176 unsigned long pt[31]; /* PAL temps */ 177 unsigned long exc_addr; /* exception address */ 178 unsigned long pad1[3]; 179 unsigned long pal_base; /* PALcode base address */ 180 unsigned long hier; /* hw interrupt enable */ 181 unsigned long hirr; /* hw interrupt request */ 182 unsigned long mm_csr; /* MMU control & status */ 183 unsigned long dc_stat; /* data cache status */ 184 unsigned long dc_addr; /* data cache addr register */ 185 unsigned long abox_ctl; /* address box control register */ 186 unsigned long esr; /* error status register */ 187 unsigned long ear; /* error address register */ 188 unsigned long car; /* cache control register */ 189 unsigned long ioc_stat0; /* I/O controller status register 0 */ 190 unsigned long ioc_stat1; /* I/O controller status register 1 */ 191 unsigned long va; /* virtual address register */ 192}; 193 194union el_lca { 195 struct el_common * c; 196 struct el_lca_mcheck_long * l; 197 struct el_lca_mcheck_short * s; 198}; 199 200#ifdef __KERNEL__ 201 202#ifndef __EXTERN_INLINE 203#define __EXTERN_INLINE extern inline 204#define __IO_EXTERN_INLINE 205#endif 206 207/* 208 * I/O functions: 209 * 210 * Unlike Jensen, the Noname machines have no concept of local 211 * I/O---everything goes over the PCI bus. 212 * 213 * There is plenty room for optimization here. In particular, 214 * the Alpha's insb/insw/extb/extw should be useful in moving 215 * data to/from the right byte-lanes. 216 */ 217 218#define vip volatile int __force * 219#define vuip volatile unsigned int __force * 220#define vulp volatile unsigned long __force * 221 222#define LCA_SET_HAE \ 223 do { \ 224 if (addr >= (1UL << 24)) { \ 225 unsigned long msb = addr & 0xf8000000; \ 226 addr -= msb; \ 227 set_hae(msb); \ 228 } \ 229 } while (0) 230 231 232__EXTERN_INLINE unsigned int lca_ioread8(void __iomem *xaddr) 233{ 234 unsigned long addr = (unsigned long) xaddr; 235 unsigned long result, base_and_type; 236 237 if (addr >= LCA_DENSE_MEM) { 238 addr -= LCA_DENSE_MEM; 239 LCA_SET_HAE; 240 base_and_type = LCA_SPARSE_MEM + 0x00; 241 } else { 242 addr -= LCA_IO; 243 base_and_type = LCA_IO + 0x00; 244 } 245 246 result = *(vip) ((addr << 5) + base_and_type); 247 return __kernel_extbl(result, addr & 3); 248} 249 250__EXTERN_INLINE void lca_iowrite8(u8 b, void __iomem *xaddr) 251{ 252 unsigned long addr = (unsigned long) xaddr; 253 unsigned long w, base_and_type; 254 255 if (addr >= LCA_DENSE_MEM) { 256 addr -= LCA_DENSE_MEM; 257 LCA_SET_HAE; 258 base_and_type = LCA_SPARSE_MEM + 0x00; 259 } else { 260 addr -= LCA_IO; 261 base_and_type = LCA_IO + 0x00; 262 } 263 264 w = __kernel_insbl(b, addr & 3); 265 *(vuip) ((addr << 5) + base_and_type) = w; 266} 267 268__EXTERN_INLINE unsigned int lca_ioread16(void __iomem *xaddr) 269{ 270 unsigned long addr = (unsigned long) xaddr; 271 unsigned long result, base_and_type; 272 273 if (addr >= LCA_DENSE_MEM) { 274 addr -= LCA_DENSE_MEM; 275 LCA_SET_HAE; 276 base_and_type = LCA_SPARSE_MEM + 0x08; 277 } else { 278 addr -= LCA_IO; 279 base_and_type = LCA_IO + 0x08; 280 } 281 282 result = *(vip) ((addr << 5) + base_and_type); 283 return __kernel_extwl(result, addr & 3); 284} 285 286__EXTERN_INLINE void lca_iowrite16(u16 b, void __iomem *xaddr) 287{ 288 unsigned long addr = (unsigned long) xaddr; 289 unsigned long w, base_and_type; 290 291 if (addr >= LCA_DENSE_MEM) { 292 addr -= LCA_DENSE_MEM; 293 LCA_SET_HAE; 294 base_and_type = LCA_SPARSE_MEM + 0x08; 295 } else { 296 addr -= LCA_IO; 297 base_and_type = LCA_IO + 0x08; 298 } 299 300 w = __kernel_inswl(b, addr & 3); 301 *(vuip) ((addr << 5) + base_and_type) = w; 302} 303 304__EXTERN_INLINE unsigned int lca_ioread32(void __iomem *xaddr) 305{ 306 unsigned long addr = (unsigned long) xaddr; 307 if (addr < LCA_DENSE_MEM) 308 addr = ((addr - LCA_IO) << 5) + LCA_IO + 0x18; 309 return *(vuip)addr; 310} 311 312__EXTERN_INLINE void lca_iowrite32(u32 b, void __iomem *xaddr) 313{ 314 unsigned long addr = (unsigned long) xaddr; 315 if (addr < LCA_DENSE_MEM) 316 addr = ((addr - LCA_IO) << 5) + LCA_IO + 0x18; 317 *(vuip)addr = b; 318} 319 320__EXTERN_INLINE void __iomem *lca_ioportmap(unsigned long addr) 321{ 322 return (void __iomem *)(addr + LCA_IO); 323} 324 325__EXTERN_INLINE void __iomem *lca_ioremap(unsigned long addr, 326 unsigned long size) 327{ 328 return (void __iomem *)(addr + LCA_DENSE_MEM); 329} 330 331__EXTERN_INLINE int lca_is_ioaddr(unsigned long addr) 332{ 333 return addr >= IDENT_ADDR + 0x120000000UL; 334} 335 336__EXTERN_INLINE int lca_is_mmio(const volatile void __iomem *addr) 337{ 338 return (unsigned long)addr >= LCA_DENSE_MEM; 339} 340 341#undef vip 342#undef vuip 343#undef vulp 344 345#undef __IO_PREFIX 346#define __IO_PREFIX lca 347#define lca_trivial_rw_bw 2 348#define lca_trivial_rw_lq 1 349#define lca_trivial_io_bw 0 350#define lca_trivial_io_lq 0 351#define lca_trivial_iounmap 1 352#include <asm/io_trivial.h> 353 354#ifdef __IO_EXTERN_INLINE 355#undef __EXTERN_INLINE 356#undef __IO_EXTERN_INLINE 357#endif 358 359#endif /* __KERNEL__ */ 360 361#endif /* __ALPHA_LCA__H__ */ 362