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  • only in /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/sound/pci/lx6464es/
1/* -*- linux-c -*- *
2 *
3 * ALSA driver for the digigram lx6464es interface
4 * low-level interface
5 *
6 * Copyright (c) 2009 Tim Blechmann <tim@klingt.org>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING.  If not, write to
20 * the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
21 * Boston, MA 02111-1307, USA.
22 *
23 */
24
25#ifndef LX_CORE_H
26#define LX_CORE_H
27
28#include <linux/interrupt.h>
29
30#include "lx_defs.h"
31
32#define REG_CRM_NUMBER		12
33
34struct lx6464es;
35
36/* low-level register access */
37
38/* dsp register access */
39enum {
40	eReg_BASE,
41	eReg_CSM,
42	eReg_CRM1,
43	eReg_CRM2,
44	eReg_CRM3,
45	eReg_CRM4,
46	eReg_CRM5,
47	eReg_CRM6,
48	eReg_CRM7,
49	eReg_CRM8,
50	eReg_CRM9,
51	eReg_CRM10,
52	eReg_CRM11,
53	eReg_CRM12,
54
55	eReg_ICR,
56	eReg_CVR,
57	eReg_ISR,
58	eReg_RXHTXH,
59	eReg_RXMTXM,
60	eReg_RHLTXL,
61	eReg_RESETDSP,
62
63	eReg_CSUF,
64	eReg_CSES,
65	eReg_CRESMSB,
66	eReg_CRESLSB,
67	eReg_ADMACESMSB,
68	eReg_ADMACESLSB,
69	eReg_CONFES,
70
71	eMaxPortLx
72};
73
74unsigned long lx_dsp_reg_read(struct lx6464es *chip, int port);
75void lx_dsp_reg_readbuf(struct lx6464es *chip, int port, u32 *data, u32 len);
76void lx_dsp_reg_write(struct lx6464es *chip, int port, unsigned data);
77void lx_dsp_reg_writebuf(struct lx6464es *chip, int port, const u32 *data,
78			 u32 len);
79
80/* plx register access */
81enum {
82    ePLX_PCICR,
83
84    ePLX_MBOX0,
85    ePLX_MBOX1,
86    ePLX_MBOX2,
87    ePLX_MBOX3,
88    ePLX_MBOX4,
89    ePLX_MBOX5,
90    ePLX_MBOX6,
91    ePLX_MBOX7,
92
93    ePLX_L2PCIDB,
94    ePLX_IRQCS,
95    ePLX_CHIPSC,
96
97    eMaxPort
98};
99
100unsigned long lx_plx_reg_read(struct lx6464es *chip, int port);
101void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data);
102
103/* rhm */
104struct lx_rmh {
105	u16	cmd_len;	/* length of the command to send (WORDs) */
106	u16	stat_len;	/* length of the status received (WORDs) */
107	u16	dsp_stat;	/* status type, RMP_SSIZE_XXX */
108	u16	cmd_idx;	/* index of the command */
109	u32	cmd[REG_CRM_NUMBER];
110	u32	stat[REG_CRM_NUMBER];
111};
112
113
114/* low-level dsp access */
115int __devinit lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version);
116int lx_dsp_get_clock_frequency(struct lx6464es *chip, u32 *rfreq);
117int lx_dsp_set_granularity(struct lx6464es *chip, u32 gran);
118int lx_dsp_read_async_events(struct lx6464es *chip, u32 *data);
119int lx_dsp_get_mac(struct lx6464es *chip, u8 *mac_address);
120
121
122/* low-level pipe handling */
123int lx_pipe_allocate(struct lx6464es *chip, u32 pipe, int is_capture,
124		     int channels);
125int lx_pipe_release(struct lx6464es *chip, u32 pipe, int is_capture);
126int lx_pipe_sample_count(struct lx6464es *chip, u32 pipe, int is_capture,
127			 u64 *rsample_count);
128int lx_pipe_state(struct lx6464es *chip, u32 pipe, int is_capture, u16 *rstate);
129int lx_pipe_stop(struct lx6464es *chip, u32 pipe, int is_capture);
130int lx_pipe_start(struct lx6464es *chip, u32 pipe, int is_capture);
131int lx_pipe_pause(struct lx6464es *chip, u32 pipe, int is_capture);
132
133int lx_pipe_wait_for_start(struct lx6464es *chip, u32 pipe, int is_capture);
134int lx_pipe_wait_for_idle(struct lx6464es *chip, u32 pipe, int is_capture);
135
136/* low-level stream handling */
137int lx_stream_set_format(struct lx6464es *chip, struct snd_pcm_runtime *runtime,
138			 u32 pipe, int is_capture);
139int lx_stream_state(struct lx6464es *chip, u32 pipe, int is_capture,
140		    int *rstate);
141int lx_stream_sample_position(struct lx6464es *chip, u32 pipe, int is_capture,
142			      u64 *r_bytepos);
143
144int lx_stream_set_state(struct lx6464es *chip, u32 pipe,
145			int is_capture, enum stream_state_t state);
146
147static inline int lx_stream_start(struct lx6464es *chip, u32 pipe,
148				  int is_capture)
149{
150	snd_printdd("->lx_stream_start\n");
151	return lx_stream_set_state(chip, pipe, is_capture, SSTATE_RUN);
152}
153
154static inline int lx_stream_pause(struct lx6464es *chip, u32 pipe,
155				  int is_capture)
156{
157	snd_printdd("->lx_stream_pause\n");
158	return lx_stream_set_state(chip, pipe, is_capture, SSTATE_PAUSE);
159}
160
161static inline int lx_stream_stop(struct lx6464es *chip, u32 pipe,
162				 int is_capture)
163{
164	snd_printdd("->lx_stream_stop\n");
165	return lx_stream_set_state(chip, pipe, is_capture, SSTATE_STOP);
166}
167
168/* low-level buffer handling */
169int lx_buffer_ask(struct lx6464es *chip, u32 pipe, int is_capture,
170		  u32 *r_needed, u32 *r_freed, u32 *size_array);
171int lx_buffer_give(struct lx6464es *chip, u32 pipe, int is_capture,
172		   u32 buffer_size, u32 buf_address_lo, u32 buf_address_hi,
173		   u32 *r_buffer_index);
174int lx_buffer_free(struct lx6464es *chip, u32 pipe, int is_capture,
175		   u32 *r_buffer_size);
176int lx_buffer_cancel(struct lx6464es *chip, u32 pipe, int is_capture,
177		     u32 buffer_index);
178
179/* low-level gain/peak handling */
180int lx_level_unmute(struct lx6464es *chip, int is_capture, int unmute);
181int lx_level_peaks(struct lx6464es *chip, int is_capture, int channels,
182		   u32 *r_levels);
183
184
185/* interrupt handling */
186irqreturn_t lx_interrupt(int irq, void *dev_id);
187void lx_irq_enable(struct lx6464es *chip);
188void lx_irq_disable(struct lx6464es *chip);
189
190void lx_tasklet_capture(unsigned long data);
191void lx_tasklet_playback(unsigned long data);
192
193
194/* Stream Format Header Defines (for LIN and IEEE754) */
195#define HEADER_FMT_BASE		HEADER_FMT_BASE_LIN
196#define HEADER_FMT_BASE_LIN	0xFED00000
197#define HEADER_FMT_BASE_FLOAT	0xFAD00000
198#define HEADER_FMT_MONO		0x00000080 /* bit 23 in header_lo. WARNING: old
199					    * bit 22 is ignored in float
200					    * format */
201#define HEADER_FMT_INTEL	0x00008000
202#define HEADER_FMT_16BITS	0x00002000
203#define HEADER_FMT_24BITS	0x00004000
204#define HEADER_FMT_UPTO11	0x00000200 /* frequency is less or equ. to 11k.
205					    * */
206#define HEADER_FMT_UPTO32	0x00000100 /* frequency is over 11k and less
207					    * then 32k.*/
208
209
210#define BIT_FMP_HEADER          23
211#define BIT_FMP_SD              22
212#define BIT_FMP_MULTICHANNEL    19
213
214#define START_STATE             1
215#define PAUSE_STATE             0
216
217
218
219
220
221/* from PcxAll_e.h */
222/* Start/Pause condition for pipes (PCXStartPipe, PCXPausePipe) */
223#define START_PAUSE_IMMEDIATE           0
224#define START_PAUSE_ON_SYNCHRO          1
225#define START_PAUSE_ON_TIME_CODE        2
226
227
228/* Pipe / Stream state */
229#define START_STATE             1
230#define PAUSE_STATE             0
231
232static inline void unpack_pointer(dma_addr_t ptr, u32 *r_low, u32 *r_high)
233{
234	*r_low = (u32)(ptr & 0xffffffff);
235#if BITS_PER_LONG == 32
236	*r_high = 0;
237#else
238	*r_high = (u32)((u64)ptr>>32);
239#endif
240}
241
242#endif /* LX_CORE_H */
243