1/* 2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver 3 * 4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com> 5 * 6 * Copyright 1999-2000 Jeff Garzik 7 * 8 * Contributors: 9 * 10 * Ani Joshi: Lots of debugging and cleanup work, really helped 11 * get the driver going 12 * 13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization 14 * 15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr 16 * 17 * Paul Richards: Bug fixes, updates 18 * 19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven 20 * Includes riva_hw.c from nVidia, see copyright below. 21 * KGI code provided the basis for state storage, init, and mode switching. 22 * 23 * This file is subject to the terms and conditions of the GNU General Public 24 * License. See the file COPYING in the main directory of this archive 25 * for more details. 26 * 27 * Known bugs and issues: 28 * restoring text mode fails 29 * doublescan modes are broken 30 */ 31 32#include <linux/module.h> 33#include <linux/kernel.h> 34#include <linux/errno.h> 35#include <linux/string.h> 36#include <linux/mm.h> 37#include <linux/slab.h> 38#include <linux/delay.h> 39#include <linux/fb.h> 40#include <linux/init.h> 41#include <linux/pci.h> 42#include <linux/backlight.h> 43#include <linux/bitrev.h> 44#ifdef CONFIG_MTRR 45#include <asm/mtrr.h> 46#endif 47#ifdef CONFIG_PPC_OF 48#include <asm/prom.h> 49#include <asm/pci-bridge.h> 50#endif 51#ifdef CONFIG_PMAC_BACKLIGHT 52#include <asm/machdep.h> 53#include <asm/backlight.h> 54#endif 55 56#include "rivafb.h" 57#include "nvreg.h" 58 59/* version number of this driver */ 60#define RIVAFB_VERSION "0.9.5b" 61 62/* ------------------------------------------------------------------------- * 63 * 64 * various helpful macros and constants 65 * 66 * ------------------------------------------------------------------------- */ 67#ifdef CONFIG_FB_RIVA_DEBUG 68#define NVTRACE printk 69#else 70#define NVTRACE if(0) printk 71#endif 72 73#define NVTRACE_ENTER(...) NVTRACE("%s START\n", __func__) 74#define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __func__) 75 76#ifdef CONFIG_FB_RIVA_DEBUG 77#define assert(expr) \ 78 if(!(expr)) { \ 79 printk( "Assertion failed! %s,%s,%s,line=%d\n",\ 80 #expr,__FILE__,__func__,__LINE__); \ 81 BUG(); \ 82 } 83#else 84#define assert(expr) 85#endif 86 87#define PFX "rivafb: " 88 89/* macro that allows you to set overflow bits */ 90#define SetBitField(value,from,to) SetBF(to,GetBF(value,from)) 91#define SetBit(n) (1<<(n)) 92#define Set8Bits(value) ((value)&0xff) 93 94/* HW cursor parameters */ 95#define MAX_CURS 32 96 97/* ------------------------------------------------------------------------- * 98 * 99 * prototypes 100 * 101 * ------------------------------------------------------------------------- */ 102 103static int rivafb_blank(int blank, struct fb_info *info); 104 105/* ------------------------------------------------------------------------- * 106 * 107 * card identification 108 * 109 * ------------------------------------------------------------------------- */ 110 111static struct pci_device_id rivafb_pci_tbl[] = { 112 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128, 113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 114 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT, 115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 116 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2, 117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 118 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2, 119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 120 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2, 121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 122 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2, 123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 124 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2, 125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 126 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR, 127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 128 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR, 129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 130 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO, 131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 132 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX, 133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 134 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2, 135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 136 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO, 137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 138 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR, 139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 140 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS, 141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 142 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2, 143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 144 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA, 145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 146 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO, 147 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 148 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460, 149 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 150 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440, 151 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 152 // NF2/IGP version, GeForce 4 MX, NV18 153 { PCI_VENDOR_ID_NVIDIA, 0x01f0, 154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 155 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420, 156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 157 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO, 158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 159 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO, 160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 161 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32, 162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 163 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL, 164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 165 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64, 166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 167 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200, 168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 169 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL, 170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 171 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL, 172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 173 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2, 174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 175 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3, 176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 177 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1, 178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 179 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2, 180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 181 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC, 182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 183 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600, 184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 185 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400, 186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 187 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200, 188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 189 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL, 190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 191 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL, 192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 193 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL, 194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 195 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200, 196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 197 { 0, } /* terminate list */ 198}; 199MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl); 200 201/* ------------------------------------------------------------------------- * 202 * 203 * global variables 204 * 205 * ------------------------------------------------------------------------- */ 206 207/* command line data, set in rivafb_setup() */ 208static int flatpanel __devinitdata = -1; /* Autodetect later */ 209static int forceCRTC __devinitdata = -1; 210static int noaccel __devinitdata = 0; 211#ifdef CONFIG_MTRR 212static int nomtrr __devinitdata = 0; 213#endif 214#ifdef CONFIG_PMAC_BACKLIGHT 215static int backlight __devinitdata = 1; 216#else 217static int backlight __devinitdata = 0; 218#endif 219 220static char *mode_option __devinitdata = NULL; 221static int strictmode = 0; 222 223static struct fb_fix_screeninfo __devinitdata rivafb_fix = { 224 .type = FB_TYPE_PACKED_PIXELS, 225 .xpanstep = 1, 226 .ypanstep = 1, 227}; 228 229static struct fb_var_screeninfo __devinitdata rivafb_default_var = { 230 .xres = 640, 231 .yres = 480, 232 .xres_virtual = 640, 233 .yres_virtual = 480, 234 .bits_per_pixel = 8, 235 .red = {0, 8, 0}, 236 .green = {0, 8, 0}, 237 .blue = {0, 8, 0}, 238 .transp = {0, 0, 0}, 239 .activate = FB_ACTIVATE_NOW, 240 .height = -1, 241 .width = -1, 242 .pixclock = 39721, 243 .left_margin = 40, 244 .right_margin = 24, 245 .upper_margin = 32, 246 .lower_margin = 11, 247 .hsync_len = 96, 248 .vsync_len = 2, 249 .vmode = FB_VMODE_NONINTERLACED 250}; 251 252/* from GGI */ 253static const struct riva_regs reg_template = { 254 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */ 255 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 256 0x41, 0x01, 0x0F, 0x00, 0x00}, 257 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */ 258 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 259 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */ 260 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 261 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */ 262 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 263 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */ 264 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 265 0x00, /* 0x40 */ 266 }, 267 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */ 268 0xFF}, 269 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */ 270 0xEB /* MISC */ 271}; 272 273/* 274 * Backlight control 275 */ 276#ifdef CONFIG_FB_RIVA_BACKLIGHT 277/* We do not have any information about which values are allowed, thus 278 * we used safe values. 279 */ 280#define MIN_LEVEL 0x158 281#define MAX_LEVEL 0x534 282#define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX) 283 284static int riva_bl_get_level_brightness(struct riva_par *par, 285 int level) 286{ 287 struct fb_info *info = pci_get_drvdata(par->pdev); 288 int nlevel; 289 290 /* Get and convert the value */ 291 /* No locking on bl_curve since accessing a single value */ 292 nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP; 293 294 if (nlevel < 0) 295 nlevel = 0; 296 else if (nlevel < MIN_LEVEL) 297 nlevel = MIN_LEVEL; 298 else if (nlevel > MAX_LEVEL) 299 nlevel = MAX_LEVEL; 300 301 return nlevel; 302} 303 304static int riva_bl_update_status(struct backlight_device *bd) 305{ 306 struct riva_par *par = bl_get_data(bd); 307 U032 tmp_pcrt, tmp_pmc; 308 int level; 309 310 if (bd->props.power != FB_BLANK_UNBLANK || 311 bd->props.fb_blank != FB_BLANK_UNBLANK) 312 level = 0; 313 else 314 level = bd->props.brightness; 315 316 tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF; 317 tmp_pcrt = NV_RD32(par->riva.PCRTC0, 0x081C) & 0xFFFFFFFC; 318 if(level > 0) { 319 tmp_pcrt |= 0x1; 320 tmp_pmc |= (1 << 31); /* backlight bit */ 321 tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */ 322 } 323 NV_WR32(par->riva.PCRTC0, 0x081C, tmp_pcrt); 324 NV_WR32(par->riva.PMC, 0x10F0, tmp_pmc); 325 326 return 0; 327} 328 329static int riva_bl_get_brightness(struct backlight_device *bd) 330{ 331 return bd->props.brightness; 332} 333 334static struct backlight_ops riva_bl_ops = { 335 .get_brightness = riva_bl_get_brightness, 336 .update_status = riva_bl_update_status, 337}; 338 339static void riva_bl_init(struct riva_par *par) 340{ 341 struct backlight_properties props; 342 struct fb_info *info = pci_get_drvdata(par->pdev); 343 struct backlight_device *bd; 344 char name[12]; 345 346 if (!par->FlatPanel) 347 return; 348 349#ifdef CONFIG_PMAC_BACKLIGHT 350 if (!machine_is(powermac) || 351 !pmac_has_backlight_type("mnca")) 352 return; 353#endif 354 355 snprintf(name, sizeof(name), "rivabl%d", info->node); 356 357 memset(&props, 0, sizeof(struct backlight_properties)); 358 props.max_brightness = FB_BACKLIGHT_LEVELS - 1; 359 bd = backlight_device_register(name, info->dev, par, &riva_bl_ops, 360 &props); 361 if (IS_ERR(bd)) { 362 info->bl_dev = NULL; 363 printk(KERN_WARNING "riva: Backlight registration failed\n"); 364 goto error; 365 } 366 367 info->bl_dev = bd; 368 fb_bl_default_curve(info, 0, 369 MIN_LEVEL * FB_BACKLIGHT_MAX / MAX_LEVEL, 370 FB_BACKLIGHT_MAX); 371 372 bd->props.brightness = bd->props.max_brightness; 373 bd->props.power = FB_BLANK_UNBLANK; 374 backlight_update_status(bd); 375 376 printk("riva: Backlight initialized (%s)\n", name); 377 378 return; 379 380error: 381 return; 382} 383 384static void riva_bl_exit(struct fb_info *info) 385{ 386 struct backlight_device *bd = info->bl_dev; 387 388 backlight_device_unregister(bd); 389 printk("riva: Backlight unloaded\n"); 390} 391#else 392static inline void riva_bl_init(struct riva_par *par) {} 393static inline void riva_bl_exit(struct fb_info *info) {} 394#endif /* CONFIG_FB_RIVA_BACKLIGHT */ 395 396/* ------------------------------------------------------------------------- * 397 * 398 * MMIO access macros 399 * 400 * ------------------------------------------------------------------------- */ 401 402static inline void CRTCout(struct riva_par *par, unsigned char index, 403 unsigned char val) 404{ 405 VGA_WR08(par->riva.PCIO, 0x3d4, index); 406 VGA_WR08(par->riva.PCIO, 0x3d5, val); 407} 408 409static inline unsigned char CRTCin(struct riva_par *par, 410 unsigned char index) 411{ 412 VGA_WR08(par->riva.PCIO, 0x3d4, index); 413 return (VGA_RD08(par->riva.PCIO, 0x3d5)); 414} 415 416static inline void GRAout(struct riva_par *par, unsigned char index, 417 unsigned char val) 418{ 419 VGA_WR08(par->riva.PVIO, 0x3ce, index); 420 VGA_WR08(par->riva.PVIO, 0x3cf, val); 421} 422 423static inline unsigned char GRAin(struct riva_par *par, 424 unsigned char index) 425{ 426 VGA_WR08(par->riva.PVIO, 0x3ce, index); 427 return (VGA_RD08(par->riva.PVIO, 0x3cf)); 428} 429 430static inline void SEQout(struct riva_par *par, unsigned char index, 431 unsigned char val) 432{ 433 VGA_WR08(par->riva.PVIO, 0x3c4, index); 434 VGA_WR08(par->riva.PVIO, 0x3c5, val); 435} 436 437static inline unsigned char SEQin(struct riva_par *par, 438 unsigned char index) 439{ 440 VGA_WR08(par->riva.PVIO, 0x3c4, index); 441 return (VGA_RD08(par->riva.PVIO, 0x3c5)); 442} 443 444static inline void ATTRout(struct riva_par *par, unsigned char index, 445 unsigned char val) 446{ 447 VGA_WR08(par->riva.PCIO, 0x3c0, index); 448 VGA_WR08(par->riva.PCIO, 0x3c0, val); 449} 450 451static inline unsigned char ATTRin(struct riva_par *par, 452 unsigned char index) 453{ 454 VGA_WR08(par->riva.PCIO, 0x3c0, index); 455 return (VGA_RD08(par->riva.PCIO, 0x3c1)); 456} 457 458static inline void MISCout(struct riva_par *par, unsigned char val) 459{ 460 VGA_WR08(par->riva.PVIO, 0x3c2, val); 461} 462 463static inline unsigned char MISCin(struct riva_par *par) 464{ 465 return (VGA_RD08(par->riva.PVIO, 0x3cc)); 466} 467 468static inline void reverse_order(u32 *l) 469{ 470 u8 *a = (u8 *)l; 471 a[0] = bitrev8(a[0]); 472 a[1] = bitrev8(a[1]); 473 a[2] = bitrev8(a[2]); 474 a[3] = bitrev8(a[3]); 475} 476 477/* ------------------------------------------------------------------------- * 478 * 479 * cursor stuff 480 * 481 * ------------------------------------------------------------------------- */ 482 483/** 484 * rivafb_load_cursor_image - load cursor image to hardware 485 * @data: address to monochrome bitmap (1 = foreground color, 0 = background) 486 * @par: pointer to private data 487 * @w: width of cursor image in pixels 488 * @h: height of cursor image in scanlines 489 * @bg: background color (ARGB1555) - alpha bit determines opacity 490 * @fg: foreground color (ARGB1555) 491 * 492 * DESCRIPTiON: 493 * Loads cursor image based on a monochrome source and mask bitmap. The 494 * image bits determines the color of the pixel, 0 for background, 1 for 495 * foreground. Only the affected region (as determined by @w and @h 496 * parameters) will be updated. 497 * 498 * CALLED FROM: 499 * rivafb_cursor() 500 */ 501static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8, 502 u16 bg, u16 fg, u32 w, u32 h) 503{ 504 int i, j, k = 0; 505 u32 b, tmp; 506 u32 *data = (u32 *)data8; 507 bg = le16_to_cpu(bg); 508 fg = le16_to_cpu(fg); 509 510 w = (w + 1) & ~1; 511 512 for (i = 0; i < h; i++) { 513 b = *data++; 514 reverse_order(&b); 515 516 for (j = 0; j < w/2; j++) { 517 tmp = 0; 518#if defined(__BIG_ENDIAN) 519 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16; 520 b <<= 1; 521 tmp |= (b & (1 << 31)) ? fg : bg; 522 b <<= 1; 523#else 524 tmp = (b & 1) ? fg : bg; 525 b >>= 1; 526 tmp |= (b & 1) ? fg << 16 : bg << 16; 527 b >>= 1; 528#endif 529 writel(tmp, &par->riva.CURSOR[k++]); 530 } 531 k += (MAX_CURS - w)/2; 532 } 533} 534 535/* ------------------------------------------------------------------------- * 536 * 537 * general utility functions 538 * 539 * ------------------------------------------------------------------------- */ 540 541/** 542 * riva_wclut - set CLUT entry 543 * @chip: pointer to RIVA_HW_INST object 544 * @regnum: register number 545 * @red: red component 546 * @green: green component 547 * @blue: blue component 548 * 549 * DESCRIPTION: 550 * Sets color register @regnum. 551 * 552 * CALLED FROM: 553 * rivafb_setcolreg() 554 */ 555static void riva_wclut(RIVA_HW_INST *chip, 556 unsigned char regnum, unsigned char red, 557 unsigned char green, unsigned char blue) 558{ 559 VGA_WR08(chip->PDIO, 0x3c8, regnum); 560 VGA_WR08(chip->PDIO, 0x3c9, red); 561 VGA_WR08(chip->PDIO, 0x3c9, green); 562 VGA_WR08(chip->PDIO, 0x3c9, blue); 563} 564 565/** 566 * riva_rclut - read fromCLUT register 567 * @chip: pointer to RIVA_HW_INST object 568 * @regnum: register number 569 * @red: red component 570 * @green: green component 571 * @blue: blue component 572 * 573 * DESCRIPTION: 574 * Reads red, green, and blue from color register @regnum. 575 * 576 * CALLED FROM: 577 * rivafb_setcolreg() 578 */ 579static void riva_rclut(RIVA_HW_INST *chip, 580 unsigned char regnum, unsigned char *red, 581 unsigned char *green, unsigned char *blue) 582{ 583 584 VGA_WR08(chip->PDIO, 0x3c7, regnum); 585 *red = VGA_RD08(chip->PDIO, 0x3c9); 586 *green = VGA_RD08(chip->PDIO, 0x3c9); 587 *blue = VGA_RD08(chip->PDIO, 0x3c9); 588} 589 590/** 591 * riva_save_state - saves current chip state 592 * @par: pointer to riva_par object containing info for current riva board 593 * @regs: pointer to riva_regs object 594 * 595 * DESCRIPTION: 596 * Saves current chip state to @regs. 597 * 598 * CALLED FROM: 599 * rivafb_probe() 600 */ 601/* from GGI */ 602static void riva_save_state(struct riva_par *par, struct riva_regs *regs) 603{ 604 int i; 605 606 NVTRACE_ENTER(); 607 par->riva.LockUnlock(&par->riva, 0); 608 609 par->riva.UnloadStateExt(&par->riva, ®s->ext); 610 611 regs->misc_output = MISCin(par); 612 613 for (i = 0; i < NUM_CRT_REGS; i++) 614 regs->crtc[i] = CRTCin(par, i); 615 616 for (i = 0; i < NUM_ATC_REGS; i++) 617 regs->attr[i] = ATTRin(par, i); 618 619 for (i = 0; i < NUM_GRC_REGS; i++) 620 regs->gra[i] = GRAin(par, i); 621 622 for (i = 0; i < NUM_SEQ_REGS; i++) 623 regs->seq[i] = SEQin(par, i); 624 NVTRACE_LEAVE(); 625} 626 627/** 628 * riva_load_state - loads current chip state 629 * @par: pointer to riva_par object containing info for current riva board 630 * @regs: pointer to riva_regs object 631 * 632 * DESCRIPTION: 633 * Loads chip state from @regs. 634 * 635 * CALLED FROM: 636 * riva_load_video_mode() 637 * rivafb_probe() 638 * rivafb_remove() 639 */ 640/* from GGI */ 641static void riva_load_state(struct riva_par *par, struct riva_regs *regs) 642{ 643 RIVA_HW_STATE *state = ®s->ext; 644 int i; 645 646 NVTRACE_ENTER(); 647 CRTCout(par, 0x11, 0x00); 648 649 par->riva.LockUnlock(&par->riva, 0); 650 651 par->riva.LoadStateExt(&par->riva, state); 652 653 MISCout(par, regs->misc_output); 654 655 for (i = 0; i < NUM_CRT_REGS; i++) { 656 switch (i) { 657 case 0x19: 658 case 0x20 ... 0x40: 659 break; 660 default: 661 CRTCout(par, i, regs->crtc[i]); 662 } 663 } 664 665 for (i = 0; i < NUM_ATC_REGS; i++) 666 ATTRout(par, i, regs->attr[i]); 667 668 for (i = 0; i < NUM_GRC_REGS; i++) 669 GRAout(par, i, regs->gra[i]); 670 671 for (i = 0; i < NUM_SEQ_REGS; i++) 672 SEQout(par, i, regs->seq[i]); 673 NVTRACE_LEAVE(); 674} 675 676/** 677 * riva_load_video_mode - calculate timings 678 * @info: pointer to fb_info object containing info for current riva board 679 * 680 * DESCRIPTION: 681 * Calculate some timings and then send em off to riva_load_state(). 682 * 683 * CALLED FROM: 684 * rivafb_set_par() 685 */ 686static int riva_load_video_mode(struct fb_info *info) 687{ 688 int bpp, width, hDisplaySize, hDisplay, hStart, 689 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock; 690 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd; 691 int rc; 692 struct riva_par *par = info->par; 693 struct riva_regs newmode; 694 695 NVTRACE_ENTER(); 696 /* time to calculate */ 697 rivafb_blank(FB_BLANK_NORMAL, info); 698 699 bpp = info->var.bits_per_pixel; 700 if (bpp == 16 && info->var.green.length == 5) 701 bpp = 15; 702 width = info->var.xres_virtual; 703 hDisplaySize = info->var.xres; 704 hDisplay = (hDisplaySize / 8) - 1; 705 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1; 706 hEnd = (hDisplaySize + info->var.right_margin + 707 info->var.hsync_len) / 8 - 1; 708 hTotal = (hDisplaySize + info->var.right_margin + 709 info->var.hsync_len + info->var.left_margin) / 8 - 5; 710 hBlankStart = hDisplay; 711 hBlankEnd = hTotal + 4; 712 713 height = info->var.yres_virtual; 714 vDisplay = info->var.yres - 1; 715 vStart = info->var.yres + info->var.lower_margin - 1; 716 vEnd = info->var.yres + info->var.lower_margin + 717 info->var.vsync_len - 1; 718 vTotal = info->var.yres + info->var.lower_margin + 719 info->var.vsync_len + info->var.upper_margin + 2; 720 vBlankStart = vDisplay; 721 vBlankEnd = vTotal + 1; 722 dotClock = 1000000000 / info->var.pixclock; 723 724 memcpy(&newmode, ®_template, sizeof(struct riva_regs)); 725 726 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) 727 vTotal |= 1; 728 729 if (par->FlatPanel) { 730 vStart = vTotal - 3; 731 vEnd = vTotal - 2; 732 vBlankStart = vStart; 733 hStart = hTotal - 3; 734 hEnd = hTotal - 2; 735 hBlankEnd = hTotal + 4; 736 } 737 738 newmode.crtc[0x0] = Set8Bits (hTotal); 739 newmode.crtc[0x1] = Set8Bits (hDisplay); 740 newmode.crtc[0x2] = Set8Bits (hBlankStart); 741 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7); 742 newmode.crtc[0x4] = Set8Bits (hStart); 743 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7) 744 | SetBitField (hEnd, 4: 0, 4:0); 745 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0); 746 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0) 747 | SetBitField (vDisplay, 8: 8, 1:1) 748 | SetBitField (vStart, 8: 8, 2:2) 749 | SetBitField (vBlankStart, 8: 8, 3:3) 750 | SetBit (4) 751 | SetBitField (vTotal, 9: 9, 5:5) 752 | SetBitField (vDisplay, 9: 9, 6:6) 753 | SetBitField (vStart, 9: 9, 7:7); 754 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5) 755 | SetBit (6); 756 newmode.crtc[0x10] = Set8Bits (vStart); 757 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0) 758 | SetBit (5); 759 newmode.crtc[0x12] = Set8Bits (vDisplay); 760 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8); 761 newmode.crtc[0x15] = Set8Bits (vBlankStart); 762 newmode.crtc[0x16] = Set8Bits (vBlankEnd); 763 764 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4) 765 | SetBitField(vBlankStart,10:10,3:3) 766 | SetBitField(vStart,10:10,2:2) 767 | SetBitField(vDisplay,10:10,1:1) 768 | SetBitField(vTotal,10:10,0:0); 769 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0) 770 | SetBitField(hDisplay,8:8,1:1) 771 | SetBitField(hBlankStart,8:8,2:2) 772 | SetBitField(hStart,8:8,3:3); 773 newmode.ext.extra = SetBitField(vTotal,11:11,0:0) 774 | SetBitField(vDisplay,11:11,2:2) 775 | SetBitField(vStart,11:11,4:4) 776 | SetBitField(vBlankStart,11:11,6:6); 777 778 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) { 779 int tmp = (hTotal >> 1) & ~1; 780 newmode.ext.interlace = Set8Bits(tmp); 781 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4); 782 } else 783 newmode.ext.interlace = 0xff; /* interlace off */ 784 785 if (par->riva.Architecture >= NV_ARCH_10) 786 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart); 787 788 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) 789 newmode.misc_output &= ~0x40; 790 else 791 newmode.misc_output |= 0x40; 792 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) 793 newmode.misc_output &= ~0x80; 794 else 795 newmode.misc_output |= 0x80; 796 797 rc = CalcStateExt(&par->riva, &newmode.ext, bpp, width, 798 hDisplaySize, height, dotClock); 799 if (rc) 800 goto out; 801 802 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) & 803 0xfff000ff; 804 if (par->FlatPanel == 1) { 805 newmode.ext.pixel |= (1 << 7); 806 newmode.ext.scale |= (1 << 8); 807 } 808 if (par->SecondCRTC) { 809 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) & 810 ~0x00001000; 811 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) | 812 0x00001000; 813 newmode.ext.crtcOwner = 3; 814 newmode.ext.pllsel |= 0x20000800; 815 newmode.ext.vpll2 = newmode.ext.vpll; 816 } else if (par->riva.twoHeads) { 817 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) | 818 0x00001000; 819 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) & 820 ~0x00001000; 821 newmode.ext.crtcOwner = 0; 822 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520); 823 } 824 if (par->FlatPanel == 1) { 825 newmode.ext.pixel |= (1 << 7); 826 newmode.ext.scale |= (1 << 8); 827 } 828 newmode.ext.cursorConfig = 0x02000100; 829 par->current_state = newmode; 830 riva_load_state(par, &par->current_state); 831 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */ 832 833out: 834 rivafb_blank(FB_BLANK_UNBLANK, info); 835 NVTRACE_LEAVE(); 836 837 return rc; 838} 839 840static void riva_update_var(struct fb_var_screeninfo *var, 841 const struct fb_videomode *modedb) 842{ 843 NVTRACE_ENTER(); 844 var->xres = var->xres_virtual = modedb->xres; 845 var->yres = modedb->yres; 846 if (var->yres_virtual < var->yres) 847 var->yres_virtual = var->yres; 848 var->xoffset = var->yoffset = 0; 849 var->pixclock = modedb->pixclock; 850 var->left_margin = modedb->left_margin; 851 var->right_margin = modedb->right_margin; 852 var->upper_margin = modedb->upper_margin; 853 var->lower_margin = modedb->lower_margin; 854 var->hsync_len = modedb->hsync_len; 855 var->vsync_len = modedb->vsync_len; 856 var->sync = modedb->sync; 857 var->vmode = modedb->vmode; 858 NVTRACE_LEAVE(); 859} 860 861/** 862 * rivafb_do_maximize - 863 * @info: pointer to fb_info object containing info for current riva board 864 * @var: 865 * @nom: 866 * @den: 867 * 868 * DESCRIPTION: 869 * . 870 * 871 * RETURNS: 872 * -EINVAL on failure, 0 on success 873 * 874 * 875 * CALLED FROM: 876 * rivafb_check_var() 877 */ 878static int rivafb_do_maximize(struct fb_info *info, 879 struct fb_var_screeninfo *var, 880 int nom, int den) 881{ 882 static struct { 883 int xres, yres; 884 } modes[] = { 885 {1600, 1280}, 886 {1280, 1024}, 887 {1024, 768}, 888 {800, 600}, 889 {640, 480}, 890 {-1, -1} 891 }; 892 int i; 893 894 NVTRACE_ENTER(); 895 /* use highest possible virtual resolution */ 896 if (var->xres_virtual == -1 && var->yres_virtual == -1) { 897 printk(KERN_WARNING PFX 898 "using maximum available virtual resolution\n"); 899 for (i = 0; modes[i].xres != -1; i++) { 900 if (modes[i].xres * nom / den * modes[i].yres < 901 info->fix.smem_len) 902 break; 903 } 904 if (modes[i].xres == -1) { 905 printk(KERN_ERR PFX 906 "could not find a virtual resolution that fits into video memory!!\n"); 907 NVTRACE("EXIT - EINVAL error\n"); 908 return -EINVAL; 909 } 910 var->xres_virtual = modes[i].xres; 911 var->yres_virtual = modes[i].yres; 912 913 printk(KERN_INFO PFX 914 "virtual resolution set to maximum of %dx%d\n", 915 var->xres_virtual, var->yres_virtual); 916 } else if (var->xres_virtual == -1) { 917 var->xres_virtual = (info->fix.smem_len * den / 918 (nom * var->yres_virtual)) & ~15; 919 printk(KERN_WARNING PFX 920 "setting virtual X resolution to %d\n", var->xres_virtual); 921 } else if (var->yres_virtual == -1) { 922 var->xres_virtual = (var->xres_virtual + 15) & ~15; 923 var->yres_virtual = info->fix.smem_len * den / 924 (nom * var->xres_virtual); 925 printk(KERN_WARNING PFX 926 "setting virtual Y resolution to %d\n", var->yres_virtual); 927 } else { 928 var->xres_virtual = (var->xres_virtual + 15) & ~15; 929 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) { 930 printk(KERN_ERR PFX 931 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n", 932 var->xres, var->yres, var->bits_per_pixel); 933 NVTRACE("EXIT - EINVAL error\n"); 934 return -EINVAL; 935 } 936 } 937 938 if (var->xres_virtual * nom / den >= 8192) { 939 printk(KERN_WARNING PFX 940 "virtual X resolution (%d) is too high, lowering to %d\n", 941 var->xres_virtual, 8192 * den / nom - 16); 942 var->xres_virtual = 8192 * den / nom - 16; 943 } 944 945 if (var->xres_virtual < var->xres) { 946 printk(KERN_ERR PFX 947 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual); 948 return -EINVAL; 949 } 950 951 if (var->yres_virtual < var->yres) { 952 printk(KERN_ERR PFX 953 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual); 954 return -EINVAL; 955 } 956 if (var->yres_virtual > 0x7fff/nom) 957 var->yres_virtual = 0x7fff/nom; 958 if (var->xres_virtual > 0x7fff/nom) 959 var->xres_virtual = 0x7fff/nom; 960 NVTRACE_LEAVE(); 961 return 0; 962} 963 964static void 965riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1) 966{ 967 RIVA_FIFO_FREE(par->riva, Patt, 4); 968 NV_WR32(&par->riva.Patt->Color0, 0, clr0); 969 NV_WR32(&par->riva.Patt->Color1, 0, clr1); 970 NV_WR32(par->riva.Patt->Monochrome, 0, pat0); 971 NV_WR32(par->riva.Patt->Monochrome, 4, pat1); 972} 973 974/* acceleration routines */ 975static inline void wait_for_idle(struct riva_par *par) 976{ 977 while (par->riva.Busy(&par->riva)); 978} 979 980/* 981 * Set ROP. Translate X rop into ROP3. Internal routine. 982 */ 983static void 984riva_set_rop_solid(struct riva_par *par, int rop) 985{ 986 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); 987 RIVA_FIFO_FREE(par->riva, Rop, 1); 988 NV_WR32(&par->riva.Rop->Rop3, 0, rop); 989 990} 991 992static void riva_setup_accel(struct fb_info *info) 993{ 994 struct riva_par *par = info->par; 995 996 RIVA_FIFO_FREE(par->riva, Clip, 2); 997 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0); 998 NV_WR32(&par->riva.Clip->WidthHeight, 0, 999 (info->var.xres_virtual & 0xffff) | 1000 (info->var.yres_virtual << 16)); 1001 riva_set_rop_solid(par, 0xcc); 1002 wait_for_idle(par); 1003} 1004 1005/** 1006 * riva_get_cmap_len - query current color map length 1007 * @var: standard kernel fb changeable data 1008 * 1009 * DESCRIPTION: 1010 * Get current color map length. 1011 * 1012 * RETURNS: 1013 * Length of color map 1014 * 1015 * CALLED FROM: 1016 * rivafb_setcolreg() 1017 */ 1018static int riva_get_cmap_len(const struct fb_var_screeninfo *var) 1019{ 1020 int rc = 256; /* reasonable default */ 1021 1022 switch (var->green.length) { 1023 case 8: 1024 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */ 1025 break; 1026 case 5: 1027 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */ 1028 break; 1029 case 6: 1030 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */ 1031 break; 1032 default: 1033 /* should not occur */ 1034 break; 1035 } 1036 return rc; 1037} 1038 1039/* ------------------------------------------------------------------------- * 1040 * 1041 * framebuffer operations 1042 * 1043 * ------------------------------------------------------------------------- */ 1044 1045static int rivafb_open(struct fb_info *info, int user) 1046{ 1047 struct riva_par *par = info->par; 1048 1049 NVTRACE_ENTER(); 1050 mutex_lock(&par->open_lock); 1051 if (!par->ref_count) { 1052#ifdef CONFIG_X86 1053 memset(&par->state, 0, sizeof(struct vgastate)); 1054 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS; 1055 /* save the DAC for Riva128 */ 1056 if (par->riva.Architecture == NV_ARCH_03) 1057 par->state.flags |= VGA_SAVE_CMAP; 1058 save_vga(&par->state); 1059#endif 1060 /* vgaHWunlock() + riva unlock (0x7F) */ 1061 CRTCout(par, 0x11, 0xFF); 1062 par->riva.LockUnlock(&par->riva, 0); 1063 1064 riva_save_state(par, &par->initial_state); 1065 } 1066 par->ref_count++; 1067 mutex_unlock(&par->open_lock); 1068 NVTRACE_LEAVE(); 1069 return 0; 1070} 1071 1072static int rivafb_release(struct fb_info *info, int user) 1073{ 1074 struct riva_par *par = info->par; 1075 1076 NVTRACE_ENTER(); 1077 mutex_lock(&par->open_lock); 1078 if (!par->ref_count) { 1079 mutex_unlock(&par->open_lock); 1080 return -EINVAL; 1081 } 1082 if (par->ref_count == 1) { 1083 par->riva.LockUnlock(&par->riva, 0); 1084 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext); 1085 riva_load_state(par, &par->initial_state); 1086#ifdef CONFIG_X86 1087 restore_vga(&par->state); 1088#endif 1089 par->riva.LockUnlock(&par->riva, 1); 1090 } 1091 par->ref_count--; 1092 mutex_unlock(&par->open_lock); 1093 NVTRACE_LEAVE(); 1094 return 0; 1095} 1096 1097static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 1098{ 1099 const struct fb_videomode *mode; 1100 struct riva_par *par = info->par; 1101 int nom, den; /* translating from pixels->bytes */ 1102 int mode_valid = 0; 1103 1104 NVTRACE_ENTER(); 1105 switch (var->bits_per_pixel) { 1106 case 1 ... 8: 1107 var->red.offset = var->green.offset = var->blue.offset = 0; 1108 var->red.length = var->green.length = var->blue.length = 8; 1109 var->bits_per_pixel = 8; 1110 nom = den = 1; 1111 break; 1112 case 9 ... 15: 1113 var->green.length = 5; 1114 /* fall through */ 1115 case 16: 1116 var->bits_per_pixel = 16; 1117 /* The Riva128 supports RGB555 only */ 1118 if (par->riva.Architecture == NV_ARCH_03) 1119 var->green.length = 5; 1120 if (var->green.length == 5) { 1121 /* 0rrrrrgg gggbbbbb */ 1122 var->red.offset = 10; 1123 var->green.offset = 5; 1124 var->blue.offset = 0; 1125 var->red.length = 5; 1126 var->green.length = 5; 1127 var->blue.length = 5; 1128 } else { 1129 /* rrrrrggg gggbbbbb */ 1130 var->red.offset = 11; 1131 var->green.offset = 5; 1132 var->blue.offset = 0; 1133 var->red.length = 5; 1134 var->green.length = 6; 1135 var->blue.length = 5; 1136 } 1137 nom = 2; 1138 den = 1; 1139 break; 1140 case 17 ... 32: 1141 var->red.length = var->green.length = var->blue.length = 8; 1142 var->bits_per_pixel = 32; 1143 var->red.offset = 16; 1144 var->green.offset = 8; 1145 var->blue.offset = 0; 1146 nom = 4; 1147 den = 1; 1148 break; 1149 default: 1150 printk(KERN_ERR PFX 1151 "mode %dx%dx%d rejected...color depth not supported.\n", 1152 var->xres, var->yres, var->bits_per_pixel); 1153 NVTRACE("EXIT, returning -EINVAL\n"); 1154 return -EINVAL; 1155 } 1156 1157 if (!strictmode) { 1158 if (!info->monspecs.vfmax || !info->monspecs.hfmax || 1159 !info->monspecs.dclkmax || !fb_validate_mode(var, info)) 1160 mode_valid = 1; 1161 } 1162 1163 /* calculate modeline if supported by monitor */ 1164 if (!mode_valid && info->monspecs.gtf) { 1165 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info)) 1166 mode_valid = 1; 1167 } 1168 1169 if (!mode_valid) { 1170 mode = fb_find_best_mode(var, &info->modelist); 1171 if (mode) { 1172 riva_update_var(var, mode); 1173 mode_valid = 1; 1174 } 1175 } 1176 1177 if (!mode_valid && info->monspecs.modedb_len) 1178 return -EINVAL; 1179 1180 if (var->xres_virtual < var->xres) 1181 var->xres_virtual = var->xres; 1182 if (var->yres_virtual <= var->yres) 1183 var->yres_virtual = -1; 1184 if (rivafb_do_maximize(info, var, nom, den) < 0) 1185 return -EINVAL; 1186 1187 if (var->xoffset < 0) 1188 var->xoffset = 0; 1189 if (var->yoffset < 0) 1190 var->yoffset = 0; 1191 1192 /* truncate xoffset and yoffset to maximum if too high */ 1193 if (var->xoffset > var->xres_virtual - var->xres) 1194 var->xoffset = var->xres_virtual - var->xres - 1; 1195 1196 if (var->yoffset > var->yres_virtual - var->yres) 1197 var->yoffset = var->yres_virtual - var->yres - 1; 1198 1199 var->red.msb_right = 1200 var->green.msb_right = 1201 var->blue.msb_right = 1202 var->transp.offset = var->transp.length = var->transp.msb_right = 0; 1203 NVTRACE_LEAVE(); 1204 return 0; 1205} 1206 1207static int rivafb_set_par(struct fb_info *info) 1208{ 1209 struct riva_par *par = info->par; 1210 int rc = 0; 1211 1212 NVTRACE_ENTER(); 1213 /* vgaHWunlock() + riva unlock (0x7F) */ 1214 CRTCout(par, 0x11, 0xFF); 1215 par->riva.LockUnlock(&par->riva, 0); 1216 rc = riva_load_video_mode(info); 1217 if (rc) 1218 goto out; 1219 if(!(info->flags & FBINFO_HWACCEL_DISABLED)) 1220 riva_setup_accel(info); 1221 1222 par->cursor_reset = 1; 1223 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3)); 1224 info->fix.visual = (info->var.bits_per_pixel == 8) ? 1225 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; 1226 1227 if (info->flags & FBINFO_HWACCEL_DISABLED) 1228 info->pixmap.scan_align = 1; 1229 else 1230 info->pixmap.scan_align = 4; 1231 1232out: 1233 NVTRACE_LEAVE(); 1234 return rc; 1235} 1236 1237/** 1238 * rivafb_pan_display 1239 * @var: standard kernel fb changeable data 1240 * @con: TODO 1241 * @info: pointer to fb_info object containing info for current riva board 1242 * 1243 * DESCRIPTION: 1244 * Pan (or wrap, depending on the `vmode' field) the display using the 1245 * `xoffset' and `yoffset' fields of the `var' structure. 1246 * If the values don't fit, return -EINVAL. 1247 * 1248 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag 1249 */ 1250static int rivafb_pan_display(struct fb_var_screeninfo *var, 1251 struct fb_info *info) 1252{ 1253 struct riva_par *par = info->par; 1254 unsigned int base; 1255 1256 NVTRACE_ENTER(); 1257 base = var->yoffset * info->fix.line_length + var->xoffset; 1258 par->riva.SetStartAddress(&par->riva, base); 1259 NVTRACE_LEAVE(); 1260 return 0; 1261} 1262 1263static int rivafb_blank(int blank, struct fb_info *info) 1264{ 1265 struct riva_par *par= info->par; 1266 unsigned char tmp, vesa; 1267 1268 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */ 1269 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */ 1270 1271 NVTRACE_ENTER(); 1272 1273 if (blank) 1274 tmp |= 0x20; 1275 1276 switch (blank) { 1277 case FB_BLANK_UNBLANK: 1278 case FB_BLANK_NORMAL: 1279 break; 1280 case FB_BLANK_VSYNC_SUSPEND: 1281 vesa |= 0x80; 1282 break; 1283 case FB_BLANK_HSYNC_SUSPEND: 1284 vesa |= 0x40; 1285 break; 1286 case FB_BLANK_POWERDOWN: 1287 vesa |= 0xc0; 1288 break; 1289 } 1290 1291 SEQout(par, 0x01, tmp); 1292 CRTCout(par, 0x1a, vesa); 1293 1294 NVTRACE_LEAVE(); 1295 1296 return 0; 1297} 1298 1299/** 1300 * rivafb_setcolreg 1301 * @regno: register index 1302 * @red: red component 1303 * @green: green component 1304 * @blue: blue component 1305 * @transp: transparency 1306 * @info: pointer to fb_info object containing info for current riva board 1307 * 1308 * DESCRIPTION: 1309 * Set a single color register. The values supplied have a 16 bit 1310 * magnitude. 1311 * 1312 * RETURNS: 1313 * Return != 0 for invalid regno. 1314 * 1315 * CALLED FROM: 1316 * fbcmap.c:fb_set_cmap() 1317 */ 1318static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green, 1319 unsigned blue, unsigned transp, 1320 struct fb_info *info) 1321{ 1322 struct riva_par *par = info->par; 1323 RIVA_HW_INST *chip = &par->riva; 1324 int i; 1325 1326 if (regno >= riva_get_cmap_len(&info->var)) 1327 return -EINVAL; 1328 1329 if (info->var.grayscale) { 1330 /* gray = 0.30*R + 0.59*G + 0.11*B */ 1331 red = green = blue = 1332 (red * 77 + green * 151 + blue * 28) >> 8; 1333 } 1334 1335 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) { 1336 ((u32 *) info->pseudo_palette)[regno] = 1337 (regno << info->var.red.offset) | 1338 (regno << info->var.green.offset) | 1339 (regno << info->var.blue.offset); 1340 /* 1341 * The Riva128 2D engine requires color information in 1342 * TrueColor format even if framebuffer is in DirectColor 1343 */ 1344 if (par->riva.Architecture == NV_ARCH_03) { 1345 switch (info->var.bits_per_pixel) { 1346 case 16: 1347 par->palette[regno] = ((red & 0xf800) >> 1) | 1348 ((green & 0xf800) >> 6) | 1349 ((blue & 0xf800) >> 11); 1350 break; 1351 case 32: 1352 par->palette[regno] = ((red & 0xff00) << 8) | 1353 ((green & 0xff00)) | 1354 ((blue & 0xff00) >> 8); 1355 break; 1356 } 1357 } 1358 } 1359 1360 switch (info->var.bits_per_pixel) { 1361 case 8: 1362 /* "transparent" stuff is completely ignored. */ 1363 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8); 1364 break; 1365 case 16: 1366 if (info->var.green.length == 5) { 1367 for (i = 0; i < 8; i++) { 1368 riva_wclut(chip, regno*8+i, red >> 8, 1369 green >> 8, blue >> 8); 1370 } 1371 } else { 1372 u8 r, g, b; 1373 1374 if (regno < 32) { 1375 for (i = 0; i < 8; i++) { 1376 riva_wclut(chip, regno*8+i, 1377 red >> 8, green >> 8, 1378 blue >> 8); 1379 } 1380 } 1381 riva_rclut(chip, regno*4, &r, &g, &b); 1382 for (i = 0; i < 4; i++) 1383 riva_wclut(chip, regno*4+i, r, 1384 green >> 8, b); 1385 } 1386 break; 1387 case 32: 1388 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8); 1389 break; 1390 default: 1391 /* do nothing */ 1392 break; 1393 } 1394 return 0; 1395} 1396 1397/** 1398 * rivafb_fillrect - hardware accelerated color fill function 1399 * @info: pointer to fb_info structure 1400 * @rect: pointer to fb_fillrect structure 1401 * 1402 * DESCRIPTION: 1403 * This function fills up a region of framebuffer memory with a solid 1404 * color with a choice of two different ROP's, copy or invert. 1405 * 1406 * CALLED FROM: 1407 * framebuffer hook 1408 */ 1409static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 1410{ 1411 struct riva_par *par = info->par; 1412 u_int color, rop = 0; 1413 1414 if ((info->flags & FBINFO_HWACCEL_DISABLED)) { 1415 cfb_fillrect(info, rect); 1416 return; 1417 } 1418 1419 if (info->var.bits_per_pixel == 8) 1420 color = rect->color; 1421 else { 1422 if (par->riva.Architecture != NV_ARCH_03) 1423 color = ((u32 *)info->pseudo_palette)[rect->color]; 1424 else 1425 color = par->palette[rect->color]; 1426 } 1427 1428 switch (rect->rop) { 1429 case ROP_XOR: 1430 rop = 0x66; 1431 break; 1432 case ROP_COPY: 1433 default: 1434 rop = 0xCC; 1435 break; 1436 } 1437 1438 riva_set_rop_solid(par, rop); 1439 1440 RIVA_FIFO_FREE(par->riva, Bitmap, 1); 1441 NV_WR32(&par->riva.Bitmap->Color1A, 0, color); 1442 1443 RIVA_FIFO_FREE(par->riva, Bitmap, 2); 1444 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0, 1445 (rect->dx << 16) | rect->dy); 1446 mb(); 1447 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0, 1448 (rect->width << 16) | rect->height); 1449 mb(); 1450 riva_set_rop_solid(par, 0xcc); 1451 1452} 1453 1454/** 1455 * rivafb_copyarea - hardware accelerated blit function 1456 * @info: pointer to fb_info structure 1457 * @region: pointer to fb_copyarea structure 1458 * 1459 * DESCRIPTION: 1460 * This copies an area of pixels from one location to another 1461 * 1462 * CALLED FROM: 1463 * framebuffer hook 1464 */ 1465static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region) 1466{ 1467 struct riva_par *par = info->par; 1468 1469 if ((info->flags & FBINFO_HWACCEL_DISABLED)) { 1470 cfb_copyarea(info, region); 1471 return; 1472 } 1473 1474 RIVA_FIFO_FREE(par->riva, Blt, 3); 1475 NV_WR32(&par->riva.Blt->TopLeftSrc, 0, 1476 (region->sy << 16) | region->sx); 1477 NV_WR32(&par->riva.Blt->TopLeftDst, 0, 1478 (region->dy << 16) | region->dx); 1479 mb(); 1480 NV_WR32(&par->riva.Blt->WidthHeight, 0, 1481 (region->height << 16) | region->width); 1482 mb(); 1483} 1484 1485static inline void convert_bgcolor_16(u32 *col) 1486{ 1487 *col = ((*col & 0x0000F800) << 8) 1488 | ((*col & 0x00007E0) << 5) 1489 | ((*col & 0x0000001F) << 3) 1490 | 0xFF000000; 1491 mb(); 1492} 1493 1494/** 1495 * rivafb_imageblit: hardware accelerated color expand function 1496 * @info: pointer to fb_info structure 1497 * @image: pointer to fb_image structure 1498 * 1499 * DESCRIPTION: 1500 * If the source is a monochrome bitmap, the function fills up a a region 1501 * of framebuffer memory with pixels whose color is determined by the bit 1502 * setting of the bitmap, 1 - foreground, 0 - background. 1503 * 1504 * If the source is not a monochrome bitmap, color expansion is not done. 1505 * In this case, it is channeled to a software function. 1506 * 1507 * CALLED FROM: 1508 * framebuffer hook 1509 */ 1510static void rivafb_imageblit(struct fb_info *info, 1511 const struct fb_image *image) 1512{ 1513 struct riva_par *par = info->par; 1514 u32 fgx = 0, bgx = 0, width, tmp; 1515 u8 *cdat = (u8 *) image->data; 1516 volatile u32 __iomem *d; 1517 int i, size; 1518 1519 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) { 1520 cfb_imageblit(info, image); 1521 return; 1522 } 1523 1524 switch (info->var.bits_per_pixel) { 1525 case 8: 1526 fgx = image->fg_color; 1527 bgx = image->bg_color; 1528 break; 1529 case 16: 1530 case 32: 1531 if (par->riva.Architecture != NV_ARCH_03) { 1532 fgx = ((u32 *)info->pseudo_palette)[image->fg_color]; 1533 bgx = ((u32 *)info->pseudo_palette)[image->bg_color]; 1534 } else { 1535 fgx = par->palette[image->fg_color]; 1536 bgx = par->palette[image->bg_color]; 1537 } 1538 if (info->var.green.length == 6) 1539 convert_bgcolor_16(&bgx); 1540 break; 1541 } 1542 1543 RIVA_FIFO_FREE(par->riva, Bitmap, 7); 1544 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0, 1545 (image->dy << 16) | (image->dx & 0xFFFF)); 1546 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0, 1547 (((image->dy + image->height) << 16) | 1548 ((image->dx + image->width) & 0xffff))); 1549 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx); 1550 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx); 1551 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0, 1552 (image->height << 16) | ((image->width + 31) & ~31)); 1553 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0, 1554 (image->height << 16) | ((image->width + 31) & ~31)); 1555 NV_WR32(&par->riva.Bitmap->PointE, 0, 1556 (image->dy << 16) | (image->dx & 0xFFFF)); 1557 1558 d = &par->riva.Bitmap->MonochromeData01E; 1559 1560 width = (image->width + 31)/32; 1561 size = width * image->height; 1562 while (size >= 16) { 1563 RIVA_FIFO_FREE(par->riva, Bitmap, 16); 1564 for (i = 0; i < 16; i++) { 1565 tmp = *((u32 *)cdat); 1566 cdat = (u8 *)((u32 *)cdat + 1); 1567 reverse_order(&tmp); 1568 NV_WR32(d, i*4, tmp); 1569 } 1570 size -= 16; 1571 } 1572 if (size) { 1573 RIVA_FIFO_FREE(par->riva, Bitmap, size); 1574 for (i = 0; i < size; i++) { 1575 tmp = *((u32 *) cdat); 1576 cdat = (u8 *)((u32 *)cdat + 1); 1577 reverse_order(&tmp); 1578 NV_WR32(d, i*4, tmp); 1579 } 1580 } 1581} 1582 1583/** 1584 * rivafb_cursor - hardware cursor function 1585 * @info: pointer to info structure 1586 * @cursor: pointer to fbcursor structure 1587 * 1588 * DESCRIPTION: 1589 * A cursor function that supports displaying a cursor image via hardware. 1590 * Within the kernel, copy and invert rops are supported. If exported 1591 * to user space, only the copy rop will be supported. 1592 * 1593 * CALLED FROM 1594 * framebuffer hook 1595 */ 1596static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor) 1597{ 1598 struct riva_par *par = info->par; 1599 u8 data[MAX_CURS * MAX_CURS/8]; 1600 int i, set = cursor->set; 1601 u16 fg, bg; 1602 1603 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS) 1604 return -ENXIO; 1605 1606 par->riva.ShowHideCursor(&par->riva, 0); 1607 1608 if (par->cursor_reset) { 1609 set = FB_CUR_SETALL; 1610 par->cursor_reset = 0; 1611 } 1612 1613 if (set & FB_CUR_SETSIZE) 1614 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2); 1615 1616 if (set & FB_CUR_SETPOS) { 1617 u32 xx, yy, temp; 1618 1619 yy = cursor->image.dy - info->var.yoffset; 1620 xx = cursor->image.dx - info->var.xoffset; 1621 temp = xx & 0xFFFF; 1622 temp |= yy << 16; 1623 1624 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp); 1625 } 1626 1627 1628 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) { 1629 u32 bg_idx = cursor->image.bg_color; 1630 u32 fg_idx = cursor->image.fg_color; 1631 u32 s_pitch = (cursor->image.width+7) >> 3; 1632 u32 d_pitch = MAX_CURS/8; 1633 u8 *dat = (u8 *) cursor->image.data; 1634 u8 *msk = (u8 *) cursor->mask; 1635 u8 *src; 1636 1637 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC); 1638 1639 if (src) { 1640 switch (cursor->rop) { 1641 case ROP_XOR: 1642 for (i = 0; i < s_pitch * cursor->image.height; i++) 1643 src[i] = dat[i] ^ msk[i]; 1644 break; 1645 case ROP_COPY: 1646 default: 1647 for (i = 0; i < s_pitch * cursor->image.height; i++) 1648 src[i] = dat[i] & msk[i]; 1649 break; 1650 } 1651 1652 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch, 1653 cursor->image.height); 1654 1655 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) | 1656 ((info->cmap.green[bg_idx] & 0xf8) << 2) | 1657 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1658 1 << 15; 1659 1660 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) | 1661 ((info->cmap.green[fg_idx] & 0xf8) << 2) | 1662 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1663 1 << 15; 1664 1665 par->riva.LockUnlock(&par->riva, 0); 1666 1667 rivafb_load_cursor_image(par, data, bg, fg, 1668 cursor->image.width, 1669 cursor->image.height); 1670 kfree(src); 1671 } 1672 } 1673 1674 if (cursor->enable) 1675 par->riva.ShowHideCursor(&par->riva, 1); 1676 1677 return 0; 1678} 1679 1680static int rivafb_sync(struct fb_info *info) 1681{ 1682 struct riva_par *par = info->par; 1683 1684 wait_for_idle(par); 1685 return 0; 1686} 1687 1688/* ------------------------------------------------------------------------- * 1689 * 1690 * initialization helper functions 1691 * 1692 * ------------------------------------------------------------------------- */ 1693 1694/* kernel interface */ 1695static struct fb_ops riva_fb_ops = { 1696 .owner = THIS_MODULE, 1697 .fb_open = rivafb_open, 1698 .fb_release = rivafb_release, 1699 .fb_check_var = rivafb_check_var, 1700 .fb_set_par = rivafb_set_par, 1701 .fb_setcolreg = rivafb_setcolreg, 1702 .fb_pan_display = rivafb_pan_display, 1703 .fb_blank = rivafb_blank, 1704 .fb_fillrect = rivafb_fillrect, 1705 .fb_copyarea = rivafb_copyarea, 1706 .fb_imageblit = rivafb_imageblit, 1707 .fb_cursor = rivafb_cursor, 1708 .fb_sync = rivafb_sync, 1709}; 1710 1711static int __devinit riva_set_fbinfo(struct fb_info *info) 1712{ 1713 unsigned int cmap_len; 1714 struct riva_par *par = info->par; 1715 1716 NVTRACE_ENTER(); 1717 info->flags = FBINFO_DEFAULT 1718 | FBINFO_HWACCEL_XPAN 1719 | FBINFO_HWACCEL_YPAN 1720 | FBINFO_HWACCEL_COPYAREA 1721 | FBINFO_HWACCEL_FILLRECT 1722 | FBINFO_HWACCEL_IMAGEBLIT; 1723 1724 /* Accel seems to not work properly on NV30 yet...*/ 1725 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) { 1726 printk(KERN_DEBUG PFX "disabling acceleration\n"); 1727 info->flags |= FBINFO_HWACCEL_DISABLED; 1728 } 1729 1730 info->var = rivafb_default_var; 1731 info->fix.visual = (info->var.bits_per_pixel == 8) ? 1732 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; 1733 1734 info->pseudo_palette = par->pseudo_palette; 1735 1736 cmap_len = riva_get_cmap_len(&info->var); 1737 fb_alloc_cmap(&info->cmap, cmap_len, 0); 1738 1739 info->pixmap.size = 8 * 1024; 1740 info->pixmap.buf_align = 4; 1741 info->pixmap.access_align = 32; 1742 info->pixmap.flags = FB_PIXMAP_SYSTEM; 1743 info->var.yres_virtual = -1; 1744 NVTRACE_LEAVE(); 1745 return (rivafb_check_var(&info->var, info)); 1746} 1747 1748#ifdef CONFIG_PPC_OF 1749static int __devinit riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd) 1750{ 1751 struct riva_par *par = info->par; 1752 struct device_node *dp; 1753 const unsigned char *pedid = NULL; 1754 const unsigned char *disptype = NULL; 1755 static char *propnames[] = { 1756 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL }; 1757 int i; 1758 1759 NVTRACE_ENTER(); 1760 dp = pci_device_to_OF_node(pd); 1761 for (; dp != NULL; dp = dp->child) { 1762 disptype = of_get_property(dp, "display-type", NULL); 1763 if (disptype == NULL) 1764 continue; 1765 if (strncmp(disptype, "LCD", 3) != 0) 1766 continue; 1767 for (i = 0; propnames[i] != NULL; ++i) { 1768 pedid = of_get_property(dp, propnames[i], NULL); 1769 if (pedid != NULL) { 1770 par->EDID = (unsigned char *)pedid; 1771 NVTRACE("LCD found.\n"); 1772 return 1; 1773 } 1774 } 1775 } 1776 NVTRACE_LEAVE(); 1777 return 0; 1778} 1779#endif /* CONFIG_PPC_OF */ 1780 1781#if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF) 1782static int __devinit riva_get_EDID_i2c(struct fb_info *info) 1783{ 1784 struct riva_par *par = info->par; 1785 struct fb_var_screeninfo var; 1786 int i; 1787 1788 NVTRACE_ENTER(); 1789 riva_create_i2c_busses(par); 1790 for (i = 0; i < 3; i++) { 1791 if (!par->chan[i].par) 1792 continue; 1793 riva_probe_i2c_connector(par, i, &par->EDID); 1794 if (par->EDID && !fb_parse_edid(par->EDID, &var)) { 1795 printk(PFX "Found EDID Block from BUS %i\n", i); 1796 break; 1797 } 1798 } 1799 1800 NVTRACE_LEAVE(); 1801 return (par->EDID) ? 1 : 0; 1802} 1803#endif /* CONFIG_FB_RIVA_I2C */ 1804 1805static void __devinit riva_update_default_var(struct fb_var_screeninfo *var, 1806 struct fb_info *info) 1807{ 1808 struct fb_monspecs *specs = &info->monspecs; 1809 struct fb_videomode modedb; 1810 1811 NVTRACE_ENTER(); 1812 /* respect mode options */ 1813 if (mode_option) { 1814 fb_find_mode(var, info, mode_option, 1815 specs->modedb, specs->modedb_len, 1816 NULL, 8); 1817 } else if (specs->modedb != NULL) { 1818 /* get preferred timing */ 1819 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) { 1820 int i; 1821 1822 for (i = 0; i < specs->modedb_len; i++) { 1823 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) { 1824 modedb = specs->modedb[i]; 1825 break; 1826 } 1827 } 1828 } else { 1829 /* otherwise, get first mode in database */ 1830 modedb = specs->modedb[0]; 1831 } 1832 var->bits_per_pixel = 8; 1833 riva_update_var(var, &modedb); 1834 } 1835 NVTRACE_LEAVE(); 1836} 1837 1838 1839static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev) 1840{ 1841 NVTRACE_ENTER(); 1842#ifdef CONFIG_PPC_OF 1843 if (!riva_get_EDID_OF(info, pdev)) 1844 printk(PFX "could not retrieve EDID from OF\n"); 1845#elif defined(CONFIG_FB_RIVA_I2C) 1846 if (!riva_get_EDID_i2c(info)) 1847 printk(PFX "could not retrieve EDID from DDC/I2C\n"); 1848#endif 1849 NVTRACE_LEAVE(); 1850} 1851 1852 1853static void __devinit riva_get_edidinfo(struct fb_info *info) 1854{ 1855 struct fb_var_screeninfo *var = &rivafb_default_var; 1856 struct riva_par *par = info->par; 1857 1858 fb_edid_to_monspecs(par->EDID, &info->monspecs); 1859 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len, 1860 &info->modelist); 1861 riva_update_default_var(var, info); 1862 1863 /* if user specified flatpanel, we respect that */ 1864 if (info->monspecs.input & FB_DISP_DDI) 1865 par->FlatPanel = 1; 1866} 1867 1868/* ------------------------------------------------------------------------- * 1869 * 1870 * PCI bus 1871 * 1872 * ------------------------------------------------------------------------- */ 1873 1874static u32 __devinit riva_get_arch(struct pci_dev *pd) 1875{ 1876 u32 arch = 0; 1877 1878 switch (pd->device & 0x0ff0) { 1879 case 0x0100: /* GeForce 256 */ 1880 case 0x0110: /* GeForce2 MX */ 1881 case 0x0150: /* GeForce2 */ 1882 case 0x0170: /* GeForce4 MX */ 1883 case 0x0180: /* GeForce4 MX (8x AGP) */ 1884 case 0x01A0: /* nForce */ 1885 case 0x01F0: /* nForce2 */ 1886 arch = NV_ARCH_10; 1887 break; 1888 case 0x0200: /* GeForce3 */ 1889 case 0x0250: /* GeForce4 Ti */ 1890 case 0x0280: /* GeForce4 Ti (8x AGP) */ 1891 arch = NV_ARCH_20; 1892 break; 1893 case 0x0300: /* GeForceFX 5800 */ 1894 case 0x0310: /* GeForceFX 5600 */ 1895 case 0x0320: /* GeForceFX 5200 */ 1896 case 0x0330: /* GeForceFX 5900 */ 1897 case 0x0340: /* GeForceFX 5700 */ 1898 arch = NV_ARCH_30; 1899 break; 1900 case 0x0020: /* TNT, TNT2 */ 1901 arch = NV_ARCH_04; 1902 break; 1903 case 0x0010: /* Riva128 */ 1904 arch = NV_ARCH_03; 1905 break; 1906 default: /* unknown architecture */ 1907 break; 1908 } 1909 return arch; 1910} 1911 1912static int __devinit rivafb_probe(struct pci_dev *pd, 1913 const struct pci_device_id *ent) 1914{ 1915 struct riva_par *default_par; 1916 struct fb_info *info; 1917 int ret; 1918 1919 NVTRACE_ENTER(); 1920 assert(pd != NULL); 1921 1922 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev); 1923 if (!info) { 1924 printk (KERN_ERR PFX "could not allocate memory\n"); 1925 ret = -ENOMEM; 1926 goto err_ret; 1927 } 1928 default_par = info->par; 1929 default_par->pdev = pd; 1930 1931 info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL); 1932 if (info->pixmap.addr == NULL) { 1933 ret = -ENOMEM; 1934 goto err_framebuffer_release; 1935 } 1936 1937 ret = pci_enable_device(pd); 1938 if (ret < 0) { 1939 printk(KERN_ERR PFX "cannot enable PCI device\n"); 1940 goto err_free_pixmap; 1941 } 1942 1943 ret = pci_request_regions(pd, "rivafb"); 1944 if (ret < 0) { 1945 printk(KERN_ERR PFX "cannot request PCI regions\n"); 1946 goto err_disable_device; 1947 } 1948 1949 mutex_init(&default_par->open_lock); 1950 default_par->riva.Architecture = riva_get_arch(pd); 1951 1952 default_par->Chipset = (pd->vendor << 16) | pd->device; 1953 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset); 1954 1955 if(default_par->riva.Architecture == 0) { 1956 printk(KERN_ERR PFX "unknown NV_ARCH\n"); 1957 ret=-ENODEV; 1958 goto err_release_region; 1959 } 1960 if(default_par->riva.Architecture == NV_ARCH_10 || 1961 default_par->riva.Architecture == NV_ARCH_20 || 1962 default_par->riva.Architecture == NV_ARCH_30) { 1963 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4); 1964 } else { 1965 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture); 1966 } 1967 1968 default_par->FlatPanel = flatpanel; 1969 if (flatpanel == 1) 1970 printk(KERN_INFO PFX "flatpanel support enabled\n"); 1971 default_par->forceCRTC = forceCRTC; 1972 1973 rivafb_fix.mmio_len = pci_resource_len(pd, 0); 1974 rivafb_fix.smem_len = pci_resource_len(pd, 1); 1975 1976 { 1977 /* enable IO and mem if not already done */ 1978 unsigned short cmd; 1979 1980 pci_read_config_word(pd, PCI_COMMAND, &cmd); 1981 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 1982 pci_write_config_word(pd, PCI_COMMAND, cmd); 1983 } 1984 1985 rivafb_fix.mmio_start = pci_resource_start(pd, 0); 1986 rivafb_fix.smem_start = pci_resource_start(pd, 1); 1987 1988 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start, 1989 rivafb_fix.mmio_len); 1990 if (!default_par->ctrl_base) { 1991 printk(KERN_ERR PFX "cannot ioremap MMIO base\n"); 1992 ret = -EIO; 1993 goto err_release_region; 1994 } 1995 1996 switch (default_par->riva.Architecture) { 1997 case NV_ARCH_03: 1998 /* Riva128's PRAMIN is in the "framebuffer" space 1999 * Since these cards were never made with more than 8 megabytes 2000 * we can safely allocate this separately. 2001 */ 2002 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000); 2003 if (!default_par->riva.PRAMIN) { 2004 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n"); 2005 ret = -EIO; 2006 goto err_iounmap_ctrl_base; 2007 } 2008 break; 2009 case NV_ARCH_04: 2010 case NV_ARCH_10: 2011 case NV_ARCH_20: 2012 case NV_ARCH_30: 2013 default_par->riva.PCRTC0 = 2014 (u32 __iomem *)(default_par->ctrl_base + 0x00600000); 2015 default_par->riva.PRAMIN = 2016 (u32 __iomem *)(default_par->ctrl_base + 0x00710000); 2017 break; 2018 } 2019 riva_common_setup(default_par); 2020 2021 if (default_par->riva.Architecture == NV_ARCH_03) { 2022 default_par->riva.PCRTC = default_par->riva.PCRTC0 2023 = default_par->riva.PGRAPH; 2024 } 2025 2026 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024; 2027 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000; 2028 info->screen_base = ioremap(rivafb_fix.smem_start, 2029 rivafb_fix.smem_len); 2030 if (!info->screen_base) { 2031 printk(KERN_ERR PFX "cannot ioremap FB base\n"); 2032 ret = -EIO; 2033 goto err_iounmap_pramin; 2034 } 2035 2036#ifdef CONFIG_MTRR 2037 if (!nomtrr) { 2038 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start, 2039 rivafb_fix.smem_len, 2040 MTRR_TYPE_WRCOMB, 1); 2041 if (default_par->mtrr.vram < 0) { 2042 printk(KERN_ERR PFX "unable to setup MTRR\n"); 2043 } else { 2044 default_par->mtrr.vram_valid = 1; 2045 /* let there be speed */ 2046 printk(KERN_INFO PFX "RIVA MTRR set to ON\n"); 2047 } 2048 } 2049#endif /* CONFIG_MTRR */ 2050 2051 info->fbops = &riva_fb_ops; 2052 info->fix = rivafb_fix; 2053 riva_get_EDID(info, pd); 2054 riva_get_edidinfo(info); 2055 2056 ret=riva_set_fbinfo(info); 2057 if (ret < 0) { 2058 printk(KERN_ERR PFX "error setting initial video mode\n"); 2059 goto err_iounmap_screen_base; 2060 } 2061 2062 fb_destroy_modedb(info->monspecs.modedb); 2063 info->monspecs.modedb = NULL; 2064 2065 pci_set_drvdata(pd, info); 2066 2067 if (backlight) 2068 riva_bl_init(info->par); 2069 2070 ret = register_framebuffer(info); 2071 if (ret < 0) { 2072 printk(KERN_ERR PFX 2073 "error registering riva framebuffer\n"); 2074 goto err_iounmap_screen_base; 2075 } 2076 2077 printk(KERN_INFO PFX 2078 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n", 2079 info->fix.id, 2080 RIVAFB_VERSION, 2081 info->fix.smem_len / (1024 * 1024), 2082 info->fix.smem_start); 2083 2084 NVTRACE_LEAVE(); 2085 return 0; 2086 2087err_iounmap_screen_base: 2088#ifdef CONFIG_FB_RIVA_I2C 2089 riva_delete_i2c_busses(info->par); 2090#endif 2091 iounmap(info->screen_base); 2092err_iounmap_pramin: 2093 if (default_par->riva.Architecture == NV_ARCH_03) 2094 iounmap(default_par->riva.PRAMIN); 2095err_iounmap_ctrl_base: 2096 iounmap(default_par->ctrl_base); 2097err_release_region: 2098 pci_release_regions(pd); 2099err_disable_device: 2100err_free_pixmap: 2101 kfree(info->pixmap.addr); 2102err_framebuffer_release: 2103 framebuffer_release(info); 2104err_ret: 2105 return ret; 2106} 2107 2108static void __devexit rivafb_remove(struct pci_dev *pd) 2109{ 2110 struct fb_info *info = pci_get_drvdata(pd); 2111 struct riva_par *par = info->par; 2112 2113 NVTRACE_ENTER(); 2114 2115#ifdef CONFIG_FB_RIVA_I2C 2116 riva_delete_i2c_busses(par); 2117 kfree(par->EDID); 2118#endif 2119 2120 unregister_framebuffer(info); 2121 2122 riva_bl_exit(info); 2123 2124#ifdef CONFIG_MTRR 2125 if (par->mtrr.vram_valid) 2126 mtrr_del(par->mtrr.vram, info->fix.smem_start, 2127 info->fix.smem_len); 2128#endif /* CONFIG_MTRR */ 2129 2130 iounmap(par->ctrl_base); 2131 iounmap(info->screen_base); 2132 if (par->riva.Architecture == NV_ARCH_03) 2133 iounmap(par->riva.PRAMIN); 2134 pci_release_regions(pd); 2135 kfree(info->pixmap.addr); 2136 framebuffer_release(info); 2137 pci_set_drvdata(pd, NULL); 2138 NVTRACE_LEAVE(); 2139} 2140 2141/* ------------------------------------------------------------------------- * 2142 * 2143 * initialization 2144 * 2145 * ------------------------------------------------------------------------- */ 2146 2147#ifndef MODULE 2148static int __devinit rivafb_setup(char *options) 2149{ 2150 char *this_opt; 2151 2152 NVTRACE_ENTER(); 2153 if (!options || !*options) 2154 return 0; 2155 2156 while ((this_opt = strsep(&options, ",")) != NULL) { 2157 if (!strncmp(this_opt, "forceCRTC", 9)) { 2158 char *p; 2159 2160 p = this_opt + 9; 2161 if (!*p || !*(++p)) continue; 2162 forceCRTC = *p - '0'; 2163 if (forceCRTC < 0 || forceCRTC > 1) 2164 forceCRTC = -1; 2165 } else if (!strncmp(this_opt, "flatpanel", 9)) { 2166 flatpanel = 1; 2167 } else if (!strncmp(this_opt, "backlight:", 10)) { 2168 backlight = simple_strtoul(this_opt+10, NULL, 0); 2169#ifdef CONFIG_MTRR 2170 } else if (!strncmp(this_opt, "nomtrr", 6)) { 2171 nomtrr = 1; 2172#endif 2173 } else if (!strncmp(this_opt, "strictmode", 10)) { 2174 strictmode = 1; 2175 } else if (!strncmp(this_opt, "noaccel", 7)) { 2176 noaccel = 1; 2177 } else 2178 mode_option = this_opt; 2179 } 2180 NVTRACE_LEAVE(); 2181 return 0; 2182} 2183#endif /* !MODULE */ 2184 2185static struct pci_driver rivafb_driver = { 2186 .name = "rivafb", 2187 .id_table = rivafb_pci_tbl, 2188 .probe = rivafb_probe, 2189 .remove = __devexit_p(rivafb_remove), 2190}; 2191 2192 2193 2194/* ------------------------------------------------------------------------- * 2195 * 2196 * modularization 2197 * 2198 * ------------------------------------------------------------------------- */ 2199 2200static int __devinit rivafb_init(void) 2201{ 2202#ifndef MODULE 2203 char *option = NULL; 2204 2205 if (fb_get_options("rivafb", &option)) 2206 return -ENODEV; 2207 rivafb_setup(option); 2208#endif 2209 return pci_register_driver(&rivafb_driver); 2210} 2211 2212 2213module_init(rivafb_init); 2214 2215static void __exit rivafb_exit(void) 2216{ 2217 pci_unregister_driver(&rivafb_driver); 2218} 2219 2220module_exit(rivafb_exit); 2221 2222module_param(noaccel, bool, 0); 2223MODULE_PARM_DESC(noaccel, "bool: disable acceleration"); 2224module_param(flatpanel, int, 0); 2225MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)"); 2226module_param(forceCRTC, int, 0); 2227MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)"); 2228#ifdef CONFIG_MTRR 2229module_param(nomtrr, bool, 0); 2230MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)"); 2231#endif 2232module_param(strictmode, bool, 0); 2233MODULE_PARM_DESC(strictmode, "Only use video modes from EDID"); 2234 2235MODULE_AUTHOR("Ani Joshi, maintainer"); 2236MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series"); 2237MODULE_LICENSE("GPL"); 2238