1/* 2 * Fujitsu MB862xx Graphics Controller Registers/Bits 3 */ 4 5#ifndef _MB862XX_REG_H 6#define _MB862XX_REG_H 7 8#ifdef MB862XX_MMIO_BOTTOM 9#define MB862XX_MMIO_BASE 0x03fc0000 10#else 11#define MB862XX_MMIO_BASE 0x01fc0000 12#endif 13#define MB862XX_I2C_BASE 0x0000c000 14#define MB862XX_DISP_BASE 0x00010000 15#define MB862XX_CAP_BASE 0x00018000 16#define MB862XX_DRAW_BASE 0x00030000 17#define MB862XX_GEO_BASE 0x00038000 18#define MB862XX_PIO_BASE 0x00038000 19#define MB862XX_MMIO_SIZE 0x40000 20 21/* Host interface/pio registers */ 22#define GC_IST 0x00000020 23#define GC_IMASK 0x00000024 24#define GC_SRST 0x0000002c 25#define GC_CCF 0x00000038 26#define GC_CID 0x000000f0 27#define GC_REVISION 0x00000084 28 29#define GC_CCF_CGE_100 0x00000000 30#define GC_CCF_CGE_133 0x00040000 31#define GC_CCF_CGE_166 0x00080000 32#define GC_CCF_COT_100 0x00000000 33#define GC_CCF_COT_133 0x00010000 34#define GC_CID_CNAME_MSK 0x0000ff00 35#define GC_CID_VERSION_MSK 0x000000ff 36 37/* define enabled interrupts hereby */ 38#define GC_INT_EN 0x00000000 39 40/* Memory interface mode register */ 41#define GC_MMR 0x0000fffc 42 43/* Display Controller registers */ 44#define GC_DCM0 0x00000000 45#define GC_HTP 0x00000004 46#define GC_HDB_HDP 0x00000008 47#define GC_VSW_HSW_HSP 0x0000000c 48#define GC_VTR 0x00000010 49#define GC_VDP_VSP 0x00000014 50#define GC_WY_WX 0x00000018 51#define GC_WH_WW 0x0000001c 52#define GC_L0M 0x00000020 53#define GC_L0OA0 0x00000024 54#define GC_L0DA0 0x00000028 55#define GC_L0DY_L0DX 0x0000002c 56#define GC_DCM1 0x00000100 57#define GC_L0EM 0x00000110 58#define GC_L0WY_L0WX 0x00000114 59#define GC_L0WH_L0WW 0x00000118 60#define GC_DCM2 0x00000104 61#define GC_DCM3 0x00000108 62#define GC_CPM_CUTC 0x000000a0 63#define GC_CUOA0 0x000000a4 64#define GC_CUY0_CUX0 0x000000a8 65#define GC_CUOA1 0x000000ac 66#define GC_CUY1_CUX1 0x000000b0 67#define GC_L0PAL0 0x00000400 68 69#define GC_CPM_CEN0 0x00100000 70#define GC_CPM_CEN1 0x00200000 71 72#define GC_DCM01_ESY 0x00000004 73#define GC_DCM01_SC 0x00003f00 74#define GC_DCM01_RESV 0x00004000 75#define GC_DCM01_CKS 0x00008000 76#define GC_DCM01_L0E 0x00010000 77#define GC_DCM01_DEN 0x80000000 78#define GC_L0M_L0C_8 0x00000000 79#define GC_L0M_L0C_16 0x80000000 80#define GC_L0EM_L0EC_24 0x40000000 81#define GC_L0M_L0W_UNIT 64 82 83#define GC_DISP_REFCLK_400 400 84 85/* Carmine specific */ 86#define MB86297_DRAW_BASE 0x00020000 87#define MB86297_DISP0_BASE 0x00100000 88#define MB86297_DISP1_BASE 0x00140000 89#define MB86297_WRBACK_BASE 0x00180000 90#define MB86297_CAP0_BASE 0x00200000 91#define MB86297_CAP1_BASE 0x00280000 92#define MB86297_DRAMCTRL_BASE 0x00300000 93#define MB86297_CTRL_BASE 0x00400000 94#define MB86297_I2C_BASE 0x00500000 95 96#define GC_CTRL_STATUS 0x00000000 97#define GC_CTRL_INT_MASK 0x00000004 98#define GC_CTRL_CLK_ENABLE 0x0000000c 99#define GC_CTRL_SOFT_RST 0x00000010 100 101#define GC_CTRL_CLK_EN_DRAM 0x00000001 102#define GC_CTRL_CLK_EN_2D3D 0x00000002 103#define GC_CTRL_CLK_EN_DISP0 0x00000020 104#define GC_CTRL_CLK_EN_DISP1 0x00000040 105 106#define GC_2D3D_REV 0x000004b4 107#define GC_RE_REVISION 0x24240200 108 109/* define enabled interrupts hereby */ 110#define GC_CARMINE_INT_EN 0x00000004 111 112/* DRAM controller */ 113#define GC_DCTL_MODE_ADD 0x00000000 114#define GC_DCTL_SETTIME1_EMODE 0x00000004 115#define GC_DCTL_REFRESH_SETTIME2 0x00000008 116#define GC_DCTL_RSV0_STATES 0x0000000C 117#define GC_DCTL_RSV2_RSV1 0x00000010 118#define GC_DCTL_DDRIF2_DDRIF1 0x00000014 119#define GC_DCTL_IOCONT1_IOCONT0 0x00000024 120 121#define GC_DCTL_STATES_MSK 0x0000000f 122#define GC_DCTL_INIT_WAIT_CNT 3000 123#define GC_DCTL_INIT_WAIT_INTERVAL 1 124 125/* DRAM ctrl values for Carmine PCI Eval. board */ 126#define GC_EVB_DCTL_MODE_ADD 0x012105c3 127#define GC_EVB_DCTL_MODE_ADD_AFT_RST 0x002105c3 128#define GC_EVB_DCTL_SETTIME1_EMODE 0x47498000 129#define GC_EVB_DCTL_REFRESH_SETTIME2 0x00422a22 130#define GC_EVB_DCTL_RSV0_STATES 0x00200003 131#define GC_EVB_DCTL_RSV0_STATES_AFT_RST 0x00200002 132#define GC_EVB_DCTL_RSV2_RSV1 0x0000000f 133#define GC_EVB_DCTL_DDRIF2_DDRIF1 0x00556646 134#define GC_EVB_DCTL_IOCONT1_IOCONT0 0x05550555 135 136#define GC_DISP_REFCLK_533 533 137 138#endif 139