1/* 2 * linux/drivers/video/cyber2000fb.c 3 * 4 * Copyright (C) 1998-2002 Russell King 5 * 6 * MIPS and 50xx clock support 7 * Copyright (C) 2001 Bradley D. LaRonde <brad@ltc.com> 8 * 9 * 32 bit support, text color and panning fixes for modes != 8 bit 10 * Copyright (C) 2002 Denis Oliver Kropp <dok@directfb.org> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 * 16 * Integraphics CyberPro 2000, 2010 and 5000 frame buffer device 17 * 18 * Based on cyberfb.c. 19 * 20 * Note that we now use the new fbcon fix, var and cmap scheme. We do 21 * still have to check which console is the currently displayed one 22 * however, especially for the colourmap stuff. 23 * 24 * We also use the new hotplug PCI subsystem. I'm not sure if there 25 * are any such cards, but I'm erring on the side of caution. We don't 26 * want to go pop just because someone does have one. 27 * 28 * Note that this doesn't work fully in the case of multiple CyberPro 29 * cards with grabbers. We currently can only attach to the first 30 * CyberPro card found. 31 * 32 * When we're in truecolour mode, we power down the LUT RAM as a power 33 * saving feature. Also, when we enter any of the powersaving modes 34 * (except soft blanking) we power down the RAMDACs. This saves about 35 * 1W, which is roughly 8% of the power consumption of a NetWinder 36 * (which, incidentally, is about the same saving as a 2.5in hard disk 37 * entering standby mode.) 38 */ 39#include <linux/module.h> 40#include <linux/kernel.h> 41#include <linux/errno.h> 42#include <linux/string.h> 43#include <linux/mm.h> 44#include <linux/slab.h> 45#include <linux/delay.h> 46#include <linux/fb.h> 47#include <linux/pci.h> 48#include <linux/init.h> 49#include <linux/io.h> 50 51#include <asm/pgtable.h> 52#include <asm/system.h> 53 54#ifdef __arm__ 55#include <asm/mach-types.h> 56#endif 57 58#include "cyber2000fb.h" 59 60struct cfb_info { 61 struct fb_info fb; 62 struct display_switch *dispsw; 63 struct display *display; 64 struct pci_dev *dev; 65 unsigned char __iomem *region; 66 unsigned char __iomem *regs; 67 u_int id; 68 int func_use_count; 69 u_long ref_ps; 70 71 /* 72 * Clock divisors 73 */ 74 u_int divisors[4]; 75 76 struct { 77 u8 red, green, blue; 78 } palette[NR_PALETTE]; 79 80 u_char mem_ctl1; 81 u_char mem_ctl2; 82 u_char mclk_mult; 83 u_char mclk_div; 84 /* 85 * RAMDAC control register is both of these or'ed together 86 */ 87 u_char ramdac_ctrl; 88 u_char ramdac_powerdown; 89 90 u32 pseudo_palette[16]; 91}; 92 93static char *default_font = "Acorn8x8"; 94module_param(default_font, charp, 0); 95MODULE_PARM_DESC(default_font, "Default font name"); 96 97/* 98 * Our access methods. 99 */ 100#define cyber2000fb_writel(val, reg, cfb) writel(val, (cfb)->regs + (reg)) 101#define cyber2000fb_writew(val, reg, cfb) writew(val, (cfb)->regs + (reg)) 102#define cyber2000fb_writeb(val, reg, cfb) writeb(val, (cfb)->regs + (reg)) 103 104#define cyber2000fb_readb(reg, cfb) readb((cfb)->regs + (reg)) 105 106static inline void 107cyber2000_crtcw(unsigned int reg, unsigned int val, struct cfb_info *cfb) 108{ 109 cyber2000fb_writew((reg & 255) | val << 8, 0x3d4, cfb); 110} 111 112static inline void 113cyber2000_grphw(unsigned int reg, unsigned int val, struct cfb_info *cfb) 114{ 115 cyber2000fb_writew((reg & 255) | val << 8, 0x3ce, cfb); 116} 117 118static inline unsigned int 119cyber2000_grphr(unsigned int reg, struct cfb_info *cfb) 120{ 121 cyber2000fb_writeb(reg, 0x3ce, cfb); 122 return cyber2000fb_readb(0x3cf, cfb); 123} 124 125static inline void 126cyber2000_attrw(unsigned int reg, unsigned int val, struct cfb_info *cfb) 127{ 128 cyber2000fb_readb(0x3da, cfb); 129 cyber2000fb_writeb(reg, 0x3c0, cfb); 130 cyber2000fb_readb(0x3c1, cfb); 131 cyber2000fb_writeb(val, 0x3c0, cfb); 132} 133 134static inline void 135cyber2000_seqw(unsigned int reg, unsigned int val, struct cfb_info *cfb) 136{ 137 cyber2000fb_writew((reg & 255) | val << 8, 0x3c4, cfb); 138} 139 140/* -------------------- Hardware specific routines ------------------------- */ 141 142/* 143 * Hardware Cyber2000 Acceleration 144 */ 145static void 146cyber2000fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 147{ 148 struct cfb_info *cfb = (struct cfb_info *)info; 149 unsigned long dst, col; 150 151 if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) { 152 cfb_fillrect(info, rect); 153 return; 154 } 155 156 cyber2000fb_writeb(0, CO_REG_CONTROL, cfb); 157 cyber2000fb_writew(rect->width - 1, CO_REG_PIXWIDTH, cfb); 158 cyber2000fb_writew(rect->height - 1, CO_REG_PIXHEIGHT, cfb); 159 160 col = rect->color; 161 if (cfb->fb.var.bits_per_pixel > 8) 162 col = ((u32 *)cfb->fb.pseudo_palette)[col]; 163 cyber2000fb_writel(col, CO_REG_FGCOLOUR, cfb); 164 165 dst = rect->dx + rect->dy * cfb->fb.var.xres_virtual; 166 if (cfb->fb.var.bits_per_pixel == 24) { 167 cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb); 168 dst *= 3; 169 } 170 171 cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb); 172 cyber2000fb_writeb(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb); 173 cyber2000fb_writew(CO_CMD_L_PATTERN_FGCOL, CO_REG_CMD_L, cfb); 174 cyber2000fb_writew(CO_CMD_H_BLITTER, CO_REG_CMD_H, cfb); 175} 176 177static void 178cyber2000fb_copyarea(struct fb_info *info, const struct fb_copyarea *region) 179{ 180 struct cfb_info *cfb = (struct cfb_info *)info; 181 unsigned int cmd = CO_CMD_L_PATTERN_FGCOL; 182 unsigned long src, dst; 183 184 if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) { 185 cfb_copyarea(info, region); 186 return; 187 } 188 189 cyber2000fb_writeb(0, CO_REG_CONTROL, cfb); 190 cyber2000fb_writew(region->width - 1, CO_REG_PIXWIDTH, cfb); 191 cyber2000fb_writew(region->height - 1, CO_REG_PIXHEIGHT, cfb); 192 193 src = region->sx + region->sy * cfb->fb.var.xres_virtual; 194 dst = region->dx + region->dy * cfb->fb.var.xres_virtual; 195 196 if (region->sx < region->dx) { 197 src += region->width - 1; 198 dst += region->width - 1; 199 cmd |= CO_CMD_L_INC_LEFT; 200 } 201 202 if (region->sy < region->dy) { 203 src += (region->height - 1) * cfb->fb.var.xres_virtual; 204 dst += (region->height - 1) * cfb->fb.var.xres_virtual; 205 cmd |= CO_CMD_L_INC_UP; 206 } 207 208 if (cfb->fb.var.bits_per_pixel == 24) { 209 cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb); 210 src *= 3; 211 dst *= 3; 212 } 213 cyber2000fb_writel(src, CO_REG_SRC1_PTR, cfb); 214 cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb); 215 cyber2000fb_writew(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb); 216 cyber2000fb_writew(cmd, CO_REG_CMD_L, cfb); 217 cyber2000fb_writew(CO_CMD_H_FGSRCMAP | CO_CMD_H_BLITTER, 218 CO_REG_CMD_H, cfb); 219} 220 221static void 222cyber2000fb_imageblit(struct fb_info *info, const struct fb_image *image) 223{ 224 cfb_imageblit(info, image); 225 return; 226} 227 228static int cyber2000fb_sync(struct fb_info *info) 229{ 230 struct cfb_info *cfb = (struct cfb_info *)info; 231 int count = 100000; 232 233 if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) 234 return 0; 235 236 while (cyber2000fb_readb(CO_REG_CONTROL, cfb) & CO_CTRL_BUSY) { 237 if (!count--) { 238 debug_printf("accel_wait timed out\n"); 239 cyber2000fb_writeb(0, CO_REG_CONTROL, cfb); 240 break; 241 } 242 udelay(1); 243 } 244 return 0; 245} 246 247/* 248 * =========================================================================== 249 */ 250 251static inline u32 convert_bitfield(u_int val, struct fb_bitfield *bf) 252{ 253 u_int mask = (1 << bf->length) - 1; 254 255 return (val >> (16 - bf->length) & mask) << bf->offset; 256} 257 258/* 259 * Set a single color register. Return != 0 for invalid regno. 260 */ 261static int 262cyber2000fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 263 u_int transp, struct fb_info *info) 264{ 265 struct cfb_info *cfb = (struct cfb_info *)info; 266 struct fb_var_screeninfo *var = &cfb->fb.var; 267 u32 pseudo_val; 268 int ret = 1; 269 270 switch (cfb->fb.fix.visual) { 271 default: 272 return 1; 273 274 /* 275 * Pseudocolour: 276 * 8 8 277 * pixel --/--+--/--> red lut --> red dac 278 * | 8 279 * +--/--> green lut --> green dac 280 * | 8 281 * +--/--> blue lut --> blue dac 282 */ 283 case FB_VISUAL_PSEUDOCOLOR: 284 if (regno >= NR_PALETTE) 285 return 1; 286 287 red >>= 8; 288 green >>= 8; 289 blue >>= 8; 290 291 cfb->palette[regno].red = red; 292 cfb->palette[regno].green = green; 293 cfb->palette[regno].blue = blue; 294 295 cyber2000fb_writeb(regno, 0x3c8, cfb); 296 cyber2000fb_writeb(red, 0x3c9, cfb); 297 cyber2000fb_writeb(green, 0x3c9, cfb); 298 cyber2000fb_writeb(blue, 0x3c9, cfb); 299 return 0; 300 301 /* 302 * Direct colour: 303 * n rl 304 * pixel --/--+--/--> red lut --> red dac 305 * | gl 306 * +--/--> green lut --> green dac 307 * | bl 308 * +--/--> blue lut --> blue dac 309 * n = bpp, rl = red length, gl = green length, bl = blue length 310 */ 311 case FB_VISUAL_DIRECTCOLOR: 312 red >>= 8; 313 green >>= 8; 314 blue >>= 8; 315 316 if (var->green.length == 6 && regno < 64) { 317 cfb->palette[regno << 2].green = green; 318 319 /* 320 * The 6 bits of the green component are applied 321 * to the high 6 bits of the LUT. 322 */ 323 cyber2000fb_writeb(regno << 2, 0x3c8, cfb); 324 cyber2000fb_writeb(cfb->palette[regno >> 1].red, 325 0x3c9, cfb); 326 cyber2000fb_writeb(green, 0x3c9, cfb); 327 cyber2000fb_writeb(cfb->palette[regno >> 1].blue, 328 0x3c9, cfb); 329 330 green = cfb->palette[regno << 3].green; 331 332 ret = 0; 333 } 334 335 if (var->green.length >= 5 && regno < 32) { 336 cfb->palette[regno << 3].red = red; 337 cfb->palette[regno << 3].green = green; 338 cfb->palette[regno << 3].blue = blue; 339 340 /* 341 * The 5 bits of each colour component are 342 * applied to the high 5 bits of the LUT. 343 */ 344 cyber2000fb_writeb(regno << 3, 0x3c8, cfb); 345 cyber2000fb_writeb(red, 0x3c9, cfb); 346 cyber2000fb_writeb(green, 0x3c9, cfb); 347 cyber2000fb_writeb(blue, 0x3c9, cfb); 348 ret = 0; 349 } 350 351 if (var->green.length == 4 && regno < 16) { 352 cfb->palette[regno << 4].red = red; 353 cfb->palette[regno << 4].green = green; 354 cfb->palette[regno << 4].blue = blue; 355 356 /* 357 * The 5 bits of each colour component are 358 * applied to the high 5 bits of the LUT. 359 */ 360 cyber2000fb_writeb(regno << 4, 0x3c8, cfb); 361 cyber2000fb_writeb(red, 0x3c9, cfb); 362 cyber2000fb_writeb(green, 0x3c9, cfb); 363 cyber2000fb_writeb(blue, 0x3c9, cfb); 364 ret = 0; 365 } 366 367 /* 368 * Since this is only used for the first 16 colours, we 369 * don't have to care about overflowing for regno >= 32 370 */ 371 pseudo_val = regno << var->red.offset | 372 regno << var->green.offset | 373 regno << var->blue.offset; 374 break; 375 376 /* 377 * True colour: 378 * n rl 379 * pixel --/--+--/--> red dac 380 * | gl 381 * +--/--> green dac 382 * | bl 383 * +--/--> blue dac 384 * n = bpp, rl = red length, gl = green length, bl = blue length 385 */ 386 case FB_VISUAL_TRUECOLOR: 387 pseudo_val = convert_bitfield(transp ^ 0xffff, &var->transp); 388 pseudo_val |= convert_bitfield(red, &var->red); 389 pseudo_val |= convert_bitfield(green, &var->green); 390 pseudo_val |= convert_bitfield(blue, &var->blue); 391 ret = 0; 392 break; 393 } 394 395 /* 396 * Now set our pseudo palette for the CFB16/24/32 drivers. 397 */ 398 if (regno < 16) 399 ((u32 *)cfb->fb.pseudo_palette)[regno] = pseudo_val; 400 401 return ret; 402} 403 404struct par_info { 405 /* 406 * Hardware 407 */ 408 u_char clock_mult; 409 u_char clock_div; 410 u_char extseqmisc; 411 u_char co_pixfmt; 412 u_char crtc_ofl; 413 u_char crtc[19]; 414 u_int width; 415 u_int pitch; 416 u_int fetch; 417 418 /* 419 * Other 420 */ 421 u_char ramdac; 422}; 423 424static const u_char crtc_idx[] = { 425 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 426 0x08, 0x09, 427 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18 428}; 429 430static void cyber2000fb_write_ramdac_ctrl(struct cfb_info *cfb) 431{ 432 unsigned int i; 433 unsigned int val = cfb->ramdac_ctrl | cfb->ramdac_powerdown; 434 435 cyber2000fb_writeb(0x56, 0x3ce, cfb); 436 i = cyber2000fb_readb(0x3cf, cfb); 437 cyber2000fb_writeb(i | 4, 0x3cf, cfb); 438 cyber2000fb_writeb(val, 0x3c6, cfb); 439 cyber2000fb_writeb(i, 0x3cf, cfb); 440 /* prevent card lock-up observed on x86 with CyberPro 2000 */ 441 cyber2000fb_readb(0x3cf, cfb); 442} 443 444static void cyber2000fb_set_timing(struct cfb_info *cfb, struct par_info *hw) 445{ 446 u_int i; 447 448 /* 449 * Blank palette 450 */ 451 for (i = 0; i < NR_PALETTE; i++) { 452 cyber2000fb_writeb(i, 0x3c8, cfb); 453 cyber2000fb_writeb(0, 0x3c9, cfb); 454 cyber2000fb_writeb(0, 0x3c9, cfb); 455 cyber2000fb_writeb(0, 0x3c9, cfb); 456 } 457 458 cyber2000fb_writeb(0xef, 0x3c2, cfb); 459 cyber2000_crtcw(0x11, 0x0b, cfb); 460 cyber2000_attrw(0x11, 0x00, cfb); 461 462 cyber2000_seqw(0x00, 0x01, cfb); 463 cyber2000_seqw(0x01, 0x01, cfb); 464 cyber2000_seqw(0x02, 0x0f, cfb); 465 cyber2000_seqw(0x03, 0x00, cfb); 466 cyber2000_seqw(0x04, 0x0e, cfb); 467 cyber2000_seqw(0x00, 0x03, cfb); 468 469 for (i = 0; i < sizeof(crtc_idx); i++) 470 cyber2000_crtcw(crtc_idx[i], hw->crtc[i], cfb); 471 472 for (i = 0x0a; i < 0x10; i++) 473 cyber2000_crtcw(i, 0, cfb); 474 475 cyber2000_grphw(EXT_CRT_VRTOFL, hw->crtc_ofl, cfb); 476 cyber2000_grphw(0x00, 0x00, cfb); 477 cyber2000_grphw(0x01, 0x00, cfb); 478 cyber2000_grphw(0x02, 0x00, cfb); 479 cyber2000_grphw(0x03, 0x00, cfb); 480 cyber2000_grphw(0x04, 0x00, cfb); 481 cyber2000_grphw(0x05, 0x60, cfb); 482 cyber2000_grphw(0x06, 0x05, cfb); 483 cyber2000_grphw(0x07, 0x0f, cfb); 484 cyber2000_grphw(0x08, 0xff, cfb); 485 486 /* Attribute controller registers */ 487 for (i = 0; i < 16; i++) 488 cyber2000_attrw(i, i, cfb); 489 490 cyber2000_attrw(0x10, 0x01, cfb); 491 cyber2000_attrw(0x11, 0x00, cfb); 492 cyber2000_attrw(0x12, 0x0f, cfb); 493 cyber2000_attrw(0x13, 0x00, cfb); 494 cyber2000_attrw(0x14, 0x00, cfb); 495 496 /* PLL registers */ 497 cyber2000_grphw(EXT_DCLK_MULT, hw->clock_mult, cfb); 498 cyber2000_grphw(EXT_DCLK_DIV, hw->clock_div, cfb); 499 cyber2000_grphw(EXT_MCLK_MULT, cfb->mclk_mult, cfb); 500 cyber2000_grphw(EXT_MCLK_DIV, cfb->mclk_div, cfb); 501 cyber2000_grphw(0x90, 0x01, cfb); 502 cyber2000_grphw(0xb9, 0x80, cfb); 503 cyber2000_grphw(0xb9, 0x00, cfb); 504 505 cfb->ramdac_ctrl = hw->ramdac; 506 cyber2000fb_write_ramdac_ctrl(cfb); 507 508 cyber2000fb_writeb(0x20, 0x3c0, cfb); 509 cyber2000fb_writeb(0xff, 0x3c6, cfb); 510 511 cyber2000_grphw(0x14, hw->fetch, cfb); 512 cyber2000_grphw(0x15, ((hw->fetch >> 8) & 0x03) | 513 ((hw->pitch >> 4) & 0x30), cfb); 514 cyber2000_grphw(EXT_SEQ_MISC, hw->extseqmisc, cfb); 515 516 /* 517 * Set up accelerator registers 518 */ 519 cyber2000fb_writew(hw->width, CO_REG_SRC_WIDTH, cfb); 520 cyber2000fb_writew(hw->width, CO_REG_DEST_WIDTH, cfb); 521 cyber2000fb_writeb(hw->co_pixfmt, CO_REG_PIXFMT, cfb); 522} 523 524static inline int 525cyber2000fb_update_start(struct cfb_info *cfb, struct fb_var_screeninfo *var) 526{ 527 u_int base = var->yoffset * var->xres_virtual + var->xoffset; 528 529 base *= var->bits_per_pixel; 530 531 /* 532 * Convert to bytes and shift two extra bits because DAC 533 * can only start on 4 byte aligned data. 534 */ 535 base >>= 5; 536 537 if (base >= 1 << 20) 538 return -EINVAL; 539 540 cyber2000_grphw(0x10, base >> 16 | 0x10, cfb); 541 cyber2000_crtcw(0x0c, base >> 8, cfb); 542 cyber2000_crtcw(0x0d, base, cfb); 543 544 return 0; 545} 546 547static int 548cyber2000fb_decode_crtc(struct par_info *hw, struct cfb_info *cfb, 549 struct fb_var_screeninfo *var) 550{ 551 u_int Htotal, Hblankend, Hsyncend; 552 u_int Vtotal, Vdispend, Vblankstart, Vblankend, Vsyncstart, Vsyncend; 553#define ENCODE_BIT(v, b1, m, b2) ((((v) >> (b1)) & (m)) << (b2)) 554 555 hw->crtc[13] = hw->pitch; 556 hw->crtc[17] = 0xe3; 557 hw->crtc[14] = 0; 558 hw->crtc[8] = 0; 559 560 Htotal = var->xres + var->right_margin + 561 var->hsync_len + var->left_margin; 562 563 if (Htotal > 2080) 564 return -EINVAL; 565 566 hw->crtc[0] = (Htotal >> 3) - 5; 567 hw->crtc[1] = (var->xres >> 3) - 1; 568 hw->crtc[2] = var->xres >> 3; 569 hw->crtc[4] = (var->xres + var->right_margin) >> 3; 570 571 Hblankend = (Htotal - 4 * 8) >> 3; 572 573 hw->crtc[3] = ENCODE_BIT(Hblankend, 0, 0x1f, 0) | 574 ENCODE_BIT(1, 0, 0x01, 7); 575 576 Hsyncend = (var->xres + var->right_margin + var->hsync_len) >> 3; 577 578 hw->crtc[5] = ENCODE_BIT(Hsyncend, 0, 0x1f, 0) | 579 ENCODE_BIT(Hblankend, 5, 0x01, 7); 580 581 Vdispend = var->yres - 1; 582 Vsyncstart = var->yres + var->lower_margin; 583 Vsyncend = var->yres + var->lower_margin + var->vsync_len; 584 Vtotal = var->yres + var->lower_margin + var->vsync_len + 585 var->upper_margin - 2; 586 587 if (Vtotal > 2047) 588 return -EINVAL; 589 590 Vblankstart = var->yres + 6; 591 Vblankend = Vtotal - 10; 592 593 hw->crtc[6] = Vtotal; 594 hw->crtc[7] = ENCODE_BIT(Vtotal, 8, 0x01, 0) | 595 ENCODE_BIT(Vdispend, 8, 0x01, 1) | 596 ENCODE_BIT(Vsyncstart, 8, 0x01, 2) | 597 ENCODE_BIT(Vblankstart, 8, 0x01, 3) | 598 ENCODE_BIT(1, 0, 0x01, 4) | 599 ENCODE_BIT(Vtotal, 9, 0x01, 5) | 600 ENCODE_BIT(Vdispend, 9, 0x01, 6) | 601 ENCODE_BIT(Vsyncstart, 9, 0x01, 7); 602 hw->crtc[9] = ENCODE_BIT(0, 0, 0x1f, 0) | 603 ENCODE_BIT(Vblankstart, 9, 0x01, 5) | 604 ENCODE_BIT(1, 0, 0x01, 6); 605 hw->crtc[10] = Vsyncstart; 606 hw->crtc[11] = ENCODE_BIT(Vsyncend, 0, 0x0f, 0) | 607 ENCODE_BIT(1, 0, 0x01, 7); 608 hw->crtc[12] = Vdispend; 609 hw->crtc[15] = Vblankstart; 610 hw->crtc[16] = Vblankend; 611 hw->crtc[18] = 0xff; 612 613 /* 614 * overflow - graphics reg 0x11 615 * 0=VTOTAL:10 1=VDEND:10 2=VRSTART:10 3=VBSTART:10 616 * 4=LINECOMP:10 5-IVIDEO 6=FIXCNT 617 */ 618 hw->crtc_ofl = 619 ENCODE_BIT(Vtotal, 10, 0x01, 0) | 620 ENCODE_BIT(Vdispend, 10, 0x01, 1) | 621 ENCODE_BIT(Vsyncstart, 10, 0x01, 2) | 622 ENCODE_BIT(Vblankstart, 10, 0x01, 3) | 623 EXT_CRT_VRTOFL_LINECOMP10; 624 625 /* woody: set the interlaced bit... */ 626 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) 627 hw->crtc_ofl |= EXT_CRT_VRTOFL_INTERLACE; 628 629 return 0; 630} 631 632/* 633 * The following was discovered by a good monitor, bit twiddling, theorising 634 * and but mostly luck. Strangely, it looks like everyone elses' PLL! 635 * 636 * Clock registers: 637 * fclock = fpll / div2 638 * fpll = fref * mult / div1 639 * where: 640 * fref = 14.318MHz (69842ps) 641 * mult = reg0xb0.7:0 642 * div1 = (reg0xb1.5:0 + 1) 643 * div2 = 2^(reg0xb1.7:6) 644 * fpll should be between 115 and 260 MHz 645 * (8696ps and 3846ps) 646 */ 647static int 648cyber2000fb_decode_clock(struct par_info *hw, struct cfb_info *cfb, 649 struct fb_var_screeninfo *var) 650{ 651 u_long pll_ps = var->pixclock; 652 const u_long ref_ps = cfb->ref_ps; 653 u_int div2, t_div1, best_div1, best_mult; 654 int best_diff; 655 int vco; 656 657 /* 658 * Step 1: 659 * find div2 such that 115MHz < fpll < 260MHz 660 * and 0 <= div2 < 4 661 */ 662 for (div2 = 0; div2 < 4; div2++) { 663 u_long new_pll; 664 665 new_pll = pll_ps / cfb->divisors[div2]; 666 if (8696 > new_pll && new_pll > 3846) { 667 pll_ps = new_pll; 668 break; 669 } 670 } 671 672 if (div2 == 4) 673 return -EINVAL; 674 675 /* 676 * Step 2: 677 * Given pll_ps and ref_ps, find: 678 * pll_ps * 0.995 < pll_ps_calc < pll_ps * 1.005 679 * where { 1 < best_div1 < 32, 1 < best_mult < 256 } 680 * pll_ps_calc = best_div1 / (ref_ps * best_mult) 681 */ 682 best_diff = 0x7fffffff; 683 best_mult = 32; 684 best_div1 = 255; 685 for (t_div1 = 32; t_div1 > 1; t_div1 -= 1) { 686 u_int rr, t_mult, t_pll_ps; 687 int diff; 688 689 /* 690 * Find the multiplier for this divisor 691 */ 692 rr = ref_ps * t_div1; 693 t_mult = (rr + pll_ps / 2) / pll_ps; 694 695 /* 696 * Is the multiplier within the correct range? 697 */ 698 if (t_mult > 256 || t_mult < 2) 699 continue; 700 701 /* 702 * Calculate the actual clock period from this multiplier 703 * and divisor, and estimate the error. 704 */ 705 t_pll_ps = (rr + t_mult / 2) / t_mult; 706 diff = pll_ps - t_pll_ps; 707 if (diff < 0) 708 diff = -diff; 709 710 if (diff < best_diff) { 711 best_diff = diff; 712 best_mult = t_mult; 713 best_div1 = t_div1; 714 } 715 716 /* 717 * If we hit an exact value, there is no point in continuing. 718 */ 719 if (diff == 0) 720 break; 721 } 722 723 /* 724 * Step 3: 725 * combine values 726 */ 727 hw->clock_mult = best_mult - 1; 728 hw->clock_div = div2 << 6 | (best_div1 - 1); 729 730 vco = ref_ps * best_div1 / best_mult; 731 if ((ref_ps == 40690) && (vco < 5556)) 732 /* Set VFSEL when VCO > 180MHz (5.556 ps). */ 733 hw->clock_div |= EXT_DCLK_DIV_VFSEL; 734 735 return 0; 736} 737 738/* 739 * Set the User Defined Part of the Display 740 */ 741static int 742cyber2000fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 743{ 744 struct cfb_info *cfb = (struct cfb_info *)info; 745 struct par_info hw; 746 unsigned int mem; 747 int err; 748 749 var->transp.msb_right = 0; 750 var->red.msb_right = 0; 751 var->green.msb_right = 0; 752 var->blue.msb_right = 0; 753 var->transp.offset = 0; 754 var->transp.length = 0; 755 756 switch (var->bits_per_pixel) { 757 case 8: /* PSEUDOCOLOUR, 256 */ 758 var->red.offset = 0; 759 var->red.length = 8; 760 var->green.offset = 0; 761 var->green.length = 8; 762 var->blue.offset = 0; 763 var->blue.length = 8; 764 break; 765 766 case 16:/* DIRECTCOLOUR, 64k or 32k */ 767 switch (var->green.length) { 768 case 6: /* RGB565, 64k */ 769 var->red.offset = 11; 770 var->red.length = 5; 771 var->green.offset = 5; 772 var->green.length = 6; 773 var->blue.offset = 0; 774 var->blue.length = 5; 775 break; 776 777 default: 778 case 5: /* RGB555, 32k */ 779 var->red.offset = 10; 780 var->red.length = 5; 781 var->green.offset = 5; 782 var->green.length = 5; 783 var->blue.offset = 0; 784 var->blue.length = 5; 785 break; 786 787 case 4: /* RGB444, 4k + transparency? */ 788 var->transp.offset = 12; 789 var->transp.length = 4; 790 var->red.offset = 8; 791 var->red.length = 4; 792 var->green.offset = 4; 793 var->green.length = 4; 794 var->blue.offset = 0; 795 var->blue.length = 4; 796 break; 797 } 798 break; 799 800 case 24:/* TRUECOLOUR, 16m */ 801 var->red.offset = 16; 802 var->red.length = 8; 803 var->green.offset = 8; 804 var->green.length = 8; 805 var->blue.offset = 0; 806 var->blue.length = 8; 807 break; 808 809 case 32:/* TRUECOLOUR, 16m */ 810 var->transp.offset = 24; 811 var->transp.length = 8; 812 var->red.offset = 16; 813 var->red.length = 8; 814 var->green.offset = 8; 815 var->green.length = 8; 816 var->blue.offset = 0; 817 var->blue.length = 8; 818 break; 819 820 default: 821 return -EINVAL; 822 } 823 824 mem = var->xres_virtual * var->yres_virtual * (var->bits_per_pixel / 8); 825 if (mem > cfb->fb.fix.smem_len) 826 var->yres_virtual = cfb->fb.fix.smem_len * 8 / 827 (var->bits_per_pixel * var->xres_virtual); 828 829 if (var->yres > var->yres_virtual) 830 var->yres = var->yres_virtual; 831 if (var->xres > var->xres_virtual) 832 var->xres = var->xres_virtual; 833 834 err = cyber2000fb_decode_clock(&hw, cfb, var); 835 if (err) 836 return err; 837 838 err = cyber2000fb_decode_crtc(&hw, cfb, var); 839 if (err) 840 return err; 841 842 return 0; 843} 844 845static int cyber2000fb_set_par(struct fb_info *info) 846{ 847 struct cfb_info *cfb = (struct cfb_info *)info; 848 struct fb_var_screeninfo *var = &cfb->fb.var; 849 struct par_info hw; 850 unsigned int mem; 851 852 hw.width = var->xres_virtual; 853 hw.ramdac = RAMDAC_VREFEN | RAMDAC_DAC8BIT; 854 855 switch (var->bits_per_pixel) { 856 case 8: 857 hw.co_pixfmt = CO_PIXFMT_8BPP; 858 hw.pitch = hw.width >> 3; 859 hw.extseqmisc = EXT_SEQ_MISC_8; 860 break; 861 862 case 16: 863 hw.co_pixfmt = CO_PIXFMT_16BPP; 864 hw.pitch = hw.width >> 2; 865 866 switch (var->green.length) { 867 case 6: /* RGB565, 64k */ 868 hw.extseqmisc = EXT_SEQ_MISC_16_RGB565; 869 break; 870 case 5: /* RGB555, 32k */ 871 hw.extseqmisc = EXT_SEQ_MISC_16_RGB555; 872 break; 873 case 4: /* RGB444, 4k + transparency? */ 874 hw.extseqmisc = EXT_SEQ_MISC_16_RGB444; 875 break; 876 default: 877 BUG(); 878 } 879 break; 880 881 case 24:/* TRUECOLOUR, 16m */ 882 hw.co_pixfmt = CO_PIXFMT_24BPP; 883 hw.width *= 3; 884 hw.pitch = hw.width >> 3; 885 hw.ramdac |= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN); 886 hw.extseqmisc = EXT_SEQ_MISC_24_RGB888; 887 break; 888 889 case 32:/* TRUECOLOUR, 16m */ 890 hw.co_pixfmt = CO_PIXFMT_32BPP; 891 hw.pitch = hw.width >> 1; 892 hw.ramdac |= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN); 893 hw.extseqmisc = EXT_SEQ_MISC_32; 894 break; 895 896 default: 897 BUG(); 898 } 899 900 /* 901 * Sigh, this is absolutely disgusting, but caused by 902 * the way the fbcon developers want to separate out 903 * the "checking" and the "setting" of the video mode. 904 * 905 * If the mode is not suitable for the hardware here, 906 * we can't prevent it being set by returning an error. 907 * 908 * In theory, since NetWinders contain just one VGA card, 909 * we should never end up hitting this problem. 910 */ 911 BUG_ON(cyber2000fb_decode_clock(&hw, cfb, var) != 0); 912 BUG_ON(cyber2000fb_decode_crtc(&hw, cfb, var) != 0); 913 914 hw.width -= 1; 915 hw.fetch = hw.pitch; 916 if (!(cfb->mem_ctl2 & MEM_CTL2_64BIT)) 917 hw.fetch <<= 1; 918 hw.fetch += 1; 919 920 cfb->fb.fix.line_length = var->xres_virtual * var->bits_per_pixel / 8; 921 922 /* 923 * Same here - if the size of the video mode exceeds the 924 * available RAM, we can't prevent this mode being set. 925 * 926 * In theory, since NetWinders contain just one VGA card, 927 * we should never end up hitting this problem. 928 */ 929 mem = cfb->fb.fix.line_length * var->yres_virtual; 930 BUG_ON(mem > cfb->fb.fix.smem_len); 931 932 /* 933 * 8bpp displays are always pseudo colour. 16bpp and above 934 * are direct colour or true colour, depending on whether 935 * the RAMDAC palettes are bypassed. (Direct colour has 936 * palettes, true colour does not.) 937 */ 938 if (var->bits_per_pixel == 8) 939 cfb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; 940 else if (hw.ramdac & RAMDAC_BYPASS) 941 cfb->fb.fix.visual = FB_VISUAL_TRUECOLOR; 942 else 943 cfb->fb.fix.visual = FB_VISUAL_DIRECTCOLOR; 944 945 cyber2000fb_set_timing(cfb, &hw); 946 cyber2000fb_update_start(cfb, var); 947 948 return 0; 949} 950 951/* 952 * Pan or Wrap the Display 953 */ 954static int 955cyber2000fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) 956{ 957 struct cfb_info *cfb = (struct cfb_info *)info; 958 959 if (cyber2000fb_update_start(cfb, var)) 960 return -EINVAL; 961 962 cfb->fb.var.xoffset = var->xoffset; 963 cfb->fb.var.yoffset = var->yoffset; 964 965 if (var->vmode & FB_VMODE_YWRAP) { 966 cfb->fb.var.vmode |= FB_VMODE_YWRAP; 967 } else { 968 cfb->fb.var.vmode &= ~FB_VMODE_YWRAP; 969 } 970 971 return 0; 972} 973 974/* 975 * (Un)Blank the display. 976 * 977 * Blank the screen if blank_mode != 0, else unblank. If 978 * blank == NULL then the caller blanks by setting the CLUT 979 * (Color Look Up Table) to all black. Return 0 if blanking 980 * succeeded, != 0 if un-/blanking failed due to e.g. a 981 * video mode which doesn't support it. Implements VESA 982 * suspend and powerdown modes on hardware that supports 983 * disabling hsync/vsync: 984 * blank_mode == 2: suspend vsync 985 * blank_mode == 3: suspend hsync 986 * blank_mode == 4: powerdown 987 * 988 * wms...Enable VESA DMPS compatible powerdown mode 989 * run "setterm -powersave powerdown" to take advantage 990 */ 991static int cyber2000fb_blank(int blank, struct fb_info *info) 992{ 993 struct cfb_info *cfb = (struct cfb_info *)info; 994 unsigned int sync = 0; 995 int i; 996 997 switch (blank) { 998 case FB_BLANK_POWERDOWN: /* powerdown - both sync lines down */ 999 sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_0; 1000 break; 1001 case FB_BLANK_HSYNC_SUSPEND: /* hsync off */ 1002 sync = EXT_SYNC_CTL_VS_NORMAL | EXT_SYNC_CTL_HS_0; 1003 break; 1004 case FB_BLANK_VSYNC_SUSPEND: /* vsync off */ 1005 sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_NORMAL; 1006 break; 1007 case FB_BLANK_NORMAL: /* soft blank */ 1008 default: /* unblank */ 1009 break; 1010 } 1011 1012 cyber2000_grphw(EXT_SYNC_CTL, sync, cfb); 1013 1014 if (blank <= 1) { 1015 /* turn on ramdacs */ 1016 cfb->ramdac_powerdown &= ~(RAMDAC_DACPWRDN | RAMDAC_BYPASS | 1017 RAMDAC_RAMPWRDN); 1018 cyber2000fb_write_ramdac_ctrl(cfb); 1019 } 1020 1021 /* 1022 * Soft blank/unblank the display. 1023 */ 1024 if (blank) { /* soft blank */ 1025 for (i = 0; i < NR_PALETTE; i++) { 1026 cyber2000fb_writeb(i, 0x3c8, cfb); 1027 cyber2000fb_writeb(0, 0x3c9, cfb); 1028 cyber2000fb_writeb(0, 0x3c9, cfb); 1029 cyber2000fb_writeb(0, 0x3c9, cfb); 1030 } 1031 } else { /* unblank */ 1032 for (i = 0; i < NR_PALETTE; i++) { 1033 cyber2000fb_writeb(i, 0x3c8, cfb); 1034 cyber2000fb_writeb(cfb->palette[i].red, 0x3c9, cfb); 1035 cyber2000fb_writeb(cfb->palette[i].green, 0x3c9, cfb); 1036 cyber2000fb_writeb(cfb->palette[i].blue, 0x3c9, cfb); 1037 } 1038 } 1039 1040 if (blank >= 2) { 1041 /* turn off ramdacs */ 1042 cfb->ramdac_powerdown |= RAMDAC_DACPWRDN | RAMDAC_BYPASS | 1043 RAMDAC_RAMPWRDN; 1044 cyber2000fb_write_ramdac_ctrl(cfb); 1045 } 1046 1047 return 0; 1048} 1049 1050static struct fb_ops cyber2000fb_ops = { 1051 .owner = THIS_MODULE, 1052 .fb_check_var = cyber2000fb_check_var, 1053 .fb_set_par = cyber2000fb_set_par, 1054 .fb_setcolreg = cyber2000fb_setcolreg, 1055 .fb_blank = cyber2000fb_blank, 1056 .fb_pan_display = cyber2000fb_pan_display, 1057 .fb_fillrect = cyber2000fb_fillrect, 1058 .fb_copyarea = cyber2000fb_copyarea, 1059 .fb_imageblit = cyber2000fb_imageblit, 1060 .fb_sync = cyber2000fb_sync, 1061}; 1062 1063/* 1064 * This is the only "static" reference to the internal data structures 1065 * of this driver. It is here solely at the moment to support the other 1066 * CyberPro modules external to this driver. 1067 */ 1068static struct cfb_info *int_cfb_info; 1069 1070/* 1071 * Enable access to the extended registers 1072 */ 1073void cyber2000fb_enable_extregs(struct cfb_info *cfb) 1074{ 1075 cfb->func_use_count += 1; 1076 1077 if (cfb->func_use_count == 1) { 1078 int old; 1079 1080 old = cyber2000_grphr(EXT_FUNC_CTL, cfb); 1081 old |= EXT_FUNC_CTL_EXTREGENBL; 1082 cyber2000_grphw(EXT_FUNC_CTL, old, cfb); 1083 } 1084} 1085EXPORT_SYMBOL(cyber2000fb_enable_extregs); 1086 1087/* 1088 * Disable access to the extended registers 1089 */ 1090void cyber2000fb_disable_extregs(struct cfb_info *cfb) 1091{ 1092 if (cfb->func_use_count == 1) { 1093 int old; 1094 1095 old = cyber2000_grphr(EXT_FUNC_CTL, cfb); 1096 old &= ~EXT_FUNC_CTL_EXTREGENBL; 1097 cyber2000_grphw(EXT_FUNC_CTL, old, cfb); 1098 } 1099 1100 if (cfb->func_use_count == 0) 1101 printk(KERN_ERR "disable_extregs: count = 0\n"); 1102 else 1103 cfb->func_use_count -= 1; 1104} 1105EXPORT_SYMBOL(cyber2000fb_disable_extregs); 1106 1107void cyber2000fb_get_fb_var(struct cfb_info *cfb, struct fb_var_screeninfo *var) 1108{ 1109 memcpy(var, &cfb->fb.var, sizeof(struct fb_var_screeninfo)); 1110} 1111EXPORT_SYMBOL(cyber2000fb_get_fb_var); 1112 1113/* 1114 * Attach a capture/tv driver to the core CyberX0X0 driver. 1115 */ 1116int cyber2000fb_attach(struct cyberpro_info *info, int idx) 1117{ 1118 if (int_cfb_info != NULL) { 1119 info->dev = int_cfb_info->dev; 1120 info->regs = int_cfb_info->regs; 1121 info->fb = int_cfb_info->fb.screen_base; 1122 info->fb_size = int_cfb_info->fb.fix.smem_len; 1123 info->enable_extregs = cyber2000fb_enable_extregs; 1124 info->disable_extregs = cyber2000fb_disable_extregs; 1125 info->info = int_cfb_info; 1126 1127 strlcpy(info->dev_name, int_cfb_info->fb.fix.id, 1128 sizeof(info->dev_name)); 1129 } 1130 1131 return int_cfb_info != NULL; 1132} 1133EXPORT_SYMBOL(cyber2000fb_attach); 1134 1135/* 1136 * Detach a capture/tv driver from the core CyberX0X0 driver. 1137 */ 1138void cyber2000fb_detach(int idx) 1139{ 1140} 1141EXPORT_SYMBOL(cyber2000fb_detach); 1142 1143/* 1144 * These parameters give 1145 * 640x480, hsync 31.5kHz, vsync 60Hz 1146 */ 1147static struct fb_videomode __devinitdata cyber2000fb_default_mode = { 1148 .refresh = 60, 1149 .xres = 640, 1150 .yres = 480, 1151 .pixclock = 39722, 1152 .left_margin = 56, 1153 .right_margin = 16, 1154 .upper_margin = 34, 1155 .lower_margin = 9, 1156 .hsync_len = 88, 1157 .vsync_len = 2, 1158 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 1159 .vmode = FB_VMODE_NONINTERLACED 1160}; 1161 1162static char igs_regs[] = { 1163 EXT_CRT_IRQ, 0, 1164 EXT_CRT_TEST, 0, 1165 EXT_SYNC_CTL, 0, 1166 EXT_SEG_WRITE_PTR, 0, 1167 EXT_SEG_READ_PTR, 0, 1168 EXT_BIU_MISC, EXT_BIU_MISC_LIN_ENABLE | 1169 EXT_BIU_MISC_COP_ENABLE | 1170 EXT_BIU_MISC_COP_BFC, 1171 EXT_FUNC_CTL, 0, 1172 CURS_H_START, 0, 1173 CURS_H_START + 1, 0, 1174 CURS_H_PRESET, 0, 1175 CURS_V_START, 0, 1176 CURS_V_START + 1, 0, 1177 CURS_V_PRESET, 0, 1178 CURS_CTL, 0, 1179 EXT_ATTRIB_CTL, EXT_ATTRIB_CTL_EXT, 1180 EXT_OVERSCAN_RED, 0, 1181 EXT_OVERSCAN_GREEN, 0, 1182 EXT_OVERSCAN_BLUE, 0, 1183 1184 /* some of these are questionable when we have a BIOS */ 1185 EXT_MEM_CTL0, EXT_MEM_CTL0_7CLK | 1186 EXT_MEM_CTL0_RAS_1 | 1187 EXT_MEM_CTL0_MULTCAS, 1188 EXT_HIDDEN_CTL1, 0x30, 1189 EXT_FIFO_CTL, 0x0b, 1190 EXT_FIFO_CTL + 1, 0x17, 1191 0x76, 0x00, 1192 EXT_HIDDEN_CTL4, 0xc8 1193}; 1194 1195/* 1196 * Initialise the CyberPro hardware. On the CyberPro5XXXX, 1197 * ensure that we're using the correct PLL (5XXX's may be 1198 * programmed to use an additional set of PLLs.) 1199 */ 1200static void cyberpro_init_hw(struct cfb_info *cfb) 1201{ 1202 int i; 1203 1204 for (i = 0; i < sizeof(igs_regs); i += 2) 1205 cyber2000_grphw(igs_regs[i], igs_regs[i + 1], cfb); 1206 1207 if (cfb->id == ID_CYBERPRO_5000) { 1208 unsigned char val; 1209 cyber2000fb_writeb(0xba, 0x3ce, cfb); 1210 val = cyber2000fb_readb(0x3cf, cfb) & 0x80; 1211 cyber2000fb_writeb(val, 0x3cf, cfb); 1212 } 1213} 1214 1215static struct cfb_info __devinit *cyberpro_alloc_fb_info(unsigned int id, 1216 char *name) 1217{ 1218 struct cfb_info *cfb; 1219 1220 cfb = kzalloc(sizeof(struct cfb_info), GFP_KERNEL); 1221 if (!cfb) 1222 return NULL; 1223 1224 1225 cfb->id = id; 1226 1227 if (id == ID_CYBERPRO_5000) 1228 cfb->ref_ps = 40690; /* 24.576 MHz */ 1229 else 1230 cfb->ref_ps = 69842; /* 14.31818 MHz (69841?) */ 1231 1232 cfb->divisors[0] = 1; 1233 cfb->divisors[1] = 2; 1234 cfb->divisors[2] = 4; 1235 1236 if (id == ID_CYBERPRO_2000) 1237 cfb->divisors[3] = 8; 1238 else 1239 cfb->divisors[3] = 6; 1240 1241 strcpy(cfb->fb.fix.id, name); 1242 1243 cfb->fb.fix.type = FB_TYPE_PACKED_PIXELS; 1244 cfb->fb.fix.type_aux = 0; 1245 cfb->fb.fix.xpanstep = 0; 1246 cfb->fb.fix.ypanstep = 1; 1247 cfb->fb.fix.ywrapstep = 0; 1248 1249 switch (id) { 1250 case ID_IGA_1682: 1251 cfb->fb.fix.accel = 0; 1252 break; 1253 1254 case ID_CYBERPRO_2000: 1255 cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2000; 1256 break; 1257 1258 case ID_CYBERPRO_2010: 1259 cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2010; 1260 break; 1261 1262 case ID_CYBERPRO_5000: 1263 cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER5000; 1264 break; 1265 } 1266 1267 cfb->fb.var.nonstd = 0; 1268 cfb->fb.var.activate = FB_ACTIVATE_NOW; 1269 cfb->fb.var.height = -1; 1270 cfb->fb.var.width = -1; 1271 cfb->fb.var.accel_flags = FB_ACCELF_TEXT; 1272 1273 cfb->fb.fbops = &cyber2000fb_ops; 1274 cfb->fb.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; 1275 cfb->fb.pseudo_palette = cfb->pseudo_palette; 1276 1277 fb_alloc_cmap(&cfb->fb.cmap, NR_PALETTE, 0); 1278 1279 return cfb; 1280} 1281 1282static void cyberpro_free_fb_info(struct cfb_info *cfb) 1283{ 1284 if (cfb) { 1285 /* 1286 * Free the colourmap 1287 */ 1288 fb_alloc_cmap(&cfb->fb.cmap, 0, 0); 1289 1290 kfree(cfb); 1291 } 1292} 1293 1294/* 1295 * Parse Cyber2000fb options. Usage: 1296 * video=cyber2000:font:fontname 1297 */ 1298#ifndef MODULE 1299static int cyber2000fb_setup(char *options) 1300{ 1301 char *opt; 1302 1303 if (!options || !*options) 1304 return 0; 1305 1306 while ((opt = strsep(&options, ",")) != NULL) { 1307 if (!*opt) 1308 continue; 1309 1310 if (strncmp(opt, "font:", 5) == 0) { 1311 static char default_font_storage[40]; 1312 1313 strlcpy(default_font_storage, opt + 5, 1314 sizeof(default_font_storage)); 1315 default_font = default_font_storage; 1316 continue; 1317 } 1318 1319 printk(KERN_ERR "CyberPro20x0: unknown parameter: %s\n", opt); 1320 } 1321 return 0; 1322} 1323#endif /* MODULE */ 1324 1325/* 1326 * The CyberPro chips can be placed on many different bus types. 1327 * This probe function is common to all bus types. The bus-specific 1328 * probe function is expected to have: 1329 * - enabled access to the linear memory region 1330 * - memory mapped access to the registers 1331 * - initialised mem_ctl1 and mem_ctl2 appropriately. 1332 */ 1333static int __devinit cyberpro_common_probe(struct cfb_info *cfb) 1334{ 1335 u_long smem_size; 1336 u_int h_sync, v_sync; 1337 int err; 1338 1339 cyberpro_init_hw(cfb); 1340 1341 /* 1342 * Get the video RAM size and width from the VGA register. 1343 * This should have been already initialised by the BIOS, 1344 * but if it's garbage, claim default 1MB VRAM (woody) 1345 */ 1346 cfb->mem_ctl1 = cyber2000_grphr(EXT_MEM_CTL1, cfb); 1347 cfb->mem_ctl2 = cyber2000_grphr(EXT_MEM_CTL2, cfb); 1348 1349 /* 1350 * Determine the size of the memory. 1351 */ 1352 switch (cfb->mem_ctl2 & MEM_CTL2_SIZE_MASK) { 1353 case MEM_CTL2_SIZE_4MB: 1354 smem_size = 0x00400000; 1355 break; 1356 case MEM_CTL2_SIZE_2MB: 1357 smem_size = 0x00200000; 1358 break; 1359 case MEM_CTL2_SIZE_1MB: 1360 smem_size = 0x00100000; 1361 break; 1362 default: 1363 smem_size = 0x00100000; 1364 break; 1365 } 1366 1367 cfb->fb.fix.smem_len = smem_size; 1368 cfb->fb.fix.mmio_len = MMIO_SIZE; 1369 cfb->fb.screen_base = cfb->region; 1370 1371 err = -EINVAL; 1372 if (!fb_find_mode(&cfb->fb.var, &cfb->fb, NULL, NULL, 0, 1373 &cyber2000fb_default_mode, 8)) { 1374 printk(KERN_ERR "%s: no valid mode found\n", cfb->fb.fix.id); 1375 goto failed; 1376 } 1377 1378 cfb->fb.var.yres_virtual = cfb->fb.fix.smem_len * 8 / 1379 (cfb->fb.var.bits_per_pixel * cfb->fb.var.xres_virtual); 1380 1381 if (cfb->fb.var.yres_virtual < cfb->fb.var.yres) 1382 cfb->fb.var.yres_virtual = cfb->fb.var.yres; 1383 1384/* fb_set_var(&cfb->fb.var, -1, &cfb->fb); */ 1385 1386 /* 1387 * Calculate the hsync and vsync frequencies. Note that 1388 * we split the 1e12 constant up so that we can preserve 1389 * the precision and fit the results into 32-bit registers. 1390 * (1953125000 * 512 = 1e12) 1391 */ 1392 h_sync = 1953125000 / cfb->fb.var.pixclock; 1393 h_sync = h_sync * 512 / (cfb->fb.var.xres + cfb->fb.var.left_margin + 1394 cfb->fb.var.right_margin + cfb->fb.var.hsync_len); 1395 v_sync = h_sync / (cfb->fb.var.yres + cfb->fb.var.upper_margin + 1396 cfb->fb.var.lower_margin + cfb->fb.var.vsync_len); 1397 1398 printk(KERN_INFO "%s: %dKiB VRAM, using %dx%d, %d.%03dkHz, %dHz\n", 1399 cfb->fb.fix.id, cfb->fb.fix.smem_len >> 10, 1400 cfb->fb.var.xres, cfb->fb.var.yres, 1401 h_sync / 1000, h_sync % 1000, v_sync); 1402 1403 if (cfb->dev) 1404 cfb->fb.device = &cfb->dev->dev; 1405 err = register_framebuffer(&cfb->fb); 1406 1407failed: 1408 return err; 1409} 1410 1411static void cyberpro_common_resume(struct cfb_info *cfb) 1412{ 1413 cyberpro_init_hw(cfb); 1414 1415 /* 1416 * Reprogram the MEM_CTL1 and MEM_CTL2 registers 1417 */ 1418 cyber2000_grphw(EXT_MEM_CTL1, cfb->mem_ctl1, cfb); 1419 cyber2000_grphw(EXT_MEM_CTL2, cfb->mem_ctl2, cfb); 1420 1421 /* 1422 * Restore the old video mode and the palette. 1423 * We also need to tell fbcon to redraw the console. 1424 */ 1425 cyber2000fb_set_par(&cfb->fb); 1426} 1427 1428#ifdef CONFIG_ARCH_SHARK 1429 1430#include <mach/framebuffer.h> 1431 1432static int __devinit cyberpro_vl_probe(void) 1433{ 1434 struct cfb_info *cfb; 1435 int err = -ENOMEM; 1436 1437 if (!request_mem_region(FB_START, FB_SIZE, "CyberPro2010")) 1438 return err; 1439 1440 cfb = cyberpro_alloc_fb_info(ID_CYBERPRO_2010, "CyberPro2010"); 1441 if (!cfb) 1442 goto failed_release; 1443 1444 cfb->dev = NULL; 1445 cfb->region = ioremap(FB_START, FB_SIZE); 1446 if (!cfb->region) 1447 goto failed_ioremap; 1448 1449 cfb->regs = cfb->region + MMIO_OFFSET; 1450 cfb->fb.fix.mmio_start = FB_START + MMIO_OFFSET; 1451 cfb->fb.fix.smem_start = FB_START; 1452 1453 /* 1454 * Bring up the hardware. This is expected to enable access 1455 * to the linear memory region, and allow access to the memory 1456 * mapped registers. Also, mem_ctl1 and mem_ctl2 must be 1457 * initialised. 1458 */ 1459 cyber2000fb_writeb(0x18, 0x46e8, cfb); 1460 cyber2000fb_writeb(0x01, 0x102, cfb); 1461 cyber2000fb_writeb(0x08, 0x46e8, cfb); 1462 cyber2000fb_writeb(EXT_BIU_MISC, 0x3ce, cfb); 1463 cyber2000fb_writeb(EXT_BIU_MISC_LIN_ENABLE, 0x3cf, cfb); 1464 1465 cfb->mclk_mult = 0xdb; 1466 cfb->mclk_div = 0x54; 1467 1468 err = cyberpro_common_probe(cfb); 1469 if (err) 1470 goto failed; 1471 1472 if (int_cfb_info == NULL) 1473 int_cfb_info = cfb; 1474 1475 return 0; 1476 1477failed: 1478 iounmap(cfb->region); 1479failed_ioremap: 1480 cyberpro_free_fb_info(cfb); 1481failed_release: 1482 release_mem_region(FB_START, FB_SIZE); 1483 1484 return err; 1485} 1486#endif /* CONFIG_ARCH_SHARK */ 1487 1488/* 1489 * PCI specific support. 1490 */ 1491#ifdef CONFIG_PCI 1492/* 1493 * We need to wake up the CyberPro, and make sure its in linear memory 1494 * mode. Unfortunately, this is specific to the platform and card that 1495 * we are running on. 1496 * 1497 * On x86 and ARM, should we be initialising the CyberPro first via the 1498 * IO registers, and then the MMIO registers to catch all cases? Can we 1499 * end up in the situation where the chip is in MMIO mode, but not awake 1500 * on an x86 system? 1501 */ 1502static int cyberpro_pci_enable_mmio(struct cfb_info *cfb) 1503{ 1504 unsigned char val; 1505 1506#if defined(__sparc_v9__) 1507#error "You lose, consult DaveM." 1508#elif defined(__sparc__) 1509 /* 1510 * SPARC does not have an "outb" instruction, so we generate 1511 * I/O cycles storing into a reserved memory space at 1512 * physical address 0x3000000 1513 */ 1514 unsigned char __iomem *iop; 1515 1516 iop = ioremap(0x3000000, 0x5000); 1517 if (iop == NULL) { 1518 printk(KERN_ERR "iga5000: cannot map I/O\n"); 1519 return -ENOMEM; 1520 } 1521 1522 writeb(0x18, iop + 0x46e8); 1523 writeb(0x01, iop + 0x102); 1524 writeb(0x08, iop + 0x46e8); 1525 writeb(EXT_BIU_MISC, iop + 0x3ce); 1526 writeb(EXT_BIU_MISC_LIN_ENABLE, iop + 0x3cf); 1527 1528 iounmap(iop); 1529#else 1530 /* 1531 * Most other machine types are "normal", so 1532 * we use the standard IO-based wakeup. 1533 */ 1534 outb(0x18, 0x46e8); 1535 outb(0x01, 0x102); 1536 outb(0x08, 0x46e8); 1537 outb(EXT_BIU_MISC, 0x3ce); 1538 outb(EXT_BIU_MISC_LIN_ENABLE, 0x3cf); 1539#endif 1540 1541 /* 1542 * Allow the CyberPro to accept PCI burst accesses 1543 */ 1544 if (cfb->id == ID_CYBERPRO_2010) { 1545 printk(KERN_INFO "%s: NOT enabling PCI bursts\n", 1546 cfb->fb.fix.id); 1547 } else { 1548 val = cyber2000_grphr(EXT_BUS_CTL, cfb); 1549 if (!(val & EXT_BUS_CTL_PCIBURST_WRITE)) { 1550 printk(KERN_INFO "%s: enabling PCI bursts\n", 1551 cfb->fb.fix.id); 1552 1553 val |= EXT_BUS_CTL_PCIBURST_WRITE; 1554 1555 if (cfb->id == ID_CYBERPRO_5000) 1556 val |= EXT_BUS_CTL_PCIBURST_READ; 1557 1558 cyber2000_grphw(EXT_BUS_CTL, val, cfb); 1559 } 1560 } 1561 1562 return 0; 1563} 1564 1565static int __devinit 1566cyberpro_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 1567{ 1568 struct cfb_info *cfb; 1569 char name[16]; 1570 int err; 1571 1572 sprintf(name, "CyberPro%4X", id->device); 1573 1574 err = pci_enable_device(dev); 1575 if (err) 1576 return err; 1577 1578 err = -ENOMEM; 1579 cfb = cyberpro_alloc_fb_info(id->driver_data, name); 1580 if (!cfb) 1581 goto failed_release; 1582 1583 err = pci_request_regions(dev, cfb->fb.fix.id); 1584 if (err) 1585 goto failed_regions; 1586 1587 cfb->dev = dev; 1588 cfb->region = pci_ioremap_bar(dev, 0); 1589 if (!cfb->region) 1590 goto failed_ioremap; 1591 1592 cfb->regs = cfb->region + MMIO_OFFSET; 1593 cfb->fb.fix.mmio_start = pci_resource_start(dev, 0) + MMIO_OFFSET; 1594 cfb->fb.fix.smem_start = pci_resource_start(dev, 0); 1595 1596 /* 1597 * Bring up the hardware. This is expected to enable access 1598 * to the linear memory region, and allow access to the memory 1599 * mapped registers. Also, mem_ctl1 and mem_ctl2 must be 1600 * initialised. 1601 */ 1602 err = cyberpro_pci_enable_mmio(cfb); 1603 if (err) 1604 goto failed; 1605 1606 cfb->mclk_mult = cyber2000_grphr(EXT_MCLK_MULT, cfb); 1607 cfb->mclk_div = cyber2000_grphr(EXT_MCLK_DIV, cfb); 1608 1609#ifdef __arm__ 1610 /* 1611 * MCLK on the NetWinder and the Shark is fixed at 75MHz 1612 */ 1613 if (machine_is_netwinder()) { 1614 cfb->mclk_mult = 0xdb; 1615 cfb->mclk_div = 0x54; 1616 } 1617#endif 1618 1619 err = cyberpro_common_probe(cfb); 1620 if (err) 1621 goto failed; 1622 1623 /* 1624 * Our driver data 1625 */ 1626 pci_set_drvdata(dev, cfb); 1627 if (int_cfb_info == NULL) 1628 int_cfb_info = cfb; 1629 1630 return 0; 1631 1632failed: 1633 iounmap(cfb->region); 1634failed_ioremap: 1635 pci_release_regions(dev); 1636failed_regions: 1637 cyberpro_free_fb_info(cfb); 1638failed_release: 1639 return err; 1640} 1641 1642static void __devexit cyberpro_pci_remove(struct pci_dev *dev) 1643{ 1644 struct cfb_info *cfb = pci_get_drvdata(dev); 1645 1646 if (cfb) { 1647 /* 1648 * If unregister_framebuffer fails, then 1649 * we will be leaving hooks that could cause 1650 * oopsen laying around. 1651 */ 1652 if (unregister_framebuffer(&cfb->fb)) 1653 printk(KERN_WARNING "%s: danger Will Robinson, " 1654 "danger danger! Oopsen imminent!\n", 1655 cfb->fb.fix.id); 1656 iounmap(cfb->region); 1657 cyberpro_free_fb_info(cfb); 1658 1659 /* 1660 * Ensure that the driver data is no longer 1661 * valid. 1662 */ 1663 pci_set_drvdata(dev, NULL); 1664 if (cfb == int_cfb_info) 1665 int_cfb_info = NULL; 1666 1667 pci_release_regions(dev); 1668 } 1669} 1670 1671static int cyberpro_pci_suspend(struct pci_dev *dev, pm_message_t state) 1672{ 1673 return 0; 1674} 1675 1676/* 1677 * Re-initialise the CyberPro hardware 1678 */ 1679static int cyberpro_pci_resume(struct pci_dev *dev) 1680{ 1681 struct cfb_info *cfb = pci_get_drvdata(dev); 1682 1683 if (cfb) { 1684 cyberpro_pci_enable_mmio(cfb); 1685 cyberpro_common_resume(cfb); 1686 } 1687 1688 return 0; 1689} 1690 1691static struct pci_device_id cyberpro_pci_table[] = { 1692/* Not yet 1693 * { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_1682, 1694 * PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_IGA_1682 }, 1695 */ 1696 { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2000, 1697 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2000 }, 1698 { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2010, 1699 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2010 }, 1700 { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_5000, 1701 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_5000 }, 1702 { 0, } 1703}; 1704 1705MODULE_DEVICE_TABLE(pci, cyberpro_pci_table); 1706 1707static struct pci_driver cyberpro_driver = { 1708 .name = "CyberPro", 1709 .probe = cyberpro_pci_probe, 1710 .remove = __devexit_p(cyberpro_pci_remove), 1711 .suspend = cyberpro_pci_suspend, 1712 .resume = cyberpro_pci_resume, 1713 .id_table = cyberpro_pci_table 1714}; 1715#endif 1716 1717/* 1718 * I don't think we can use the "module_init" stuff here because 1719 * the fbcon stuff may not be initialised yet. Hence the #ifdef 1720 * around module_init. 1721 * 1722 * Tony: "module_init" is now required 1723 */ 1724static int __init cyber2000fb_init(void) 1725{ 1726 int ret = -1, err; 1727 1728#ifndef MODULE 1729 char *option = NULL; 1730 1731 if (fb_get_options("cyber2000fb", &option)) 1732 return -ENODEV; 1733 cyber2000fb_setup(option); 1734#endif 1735 1736#ifdef CONFIG_ARCH_SHARK 1737 err = cyberpro_vl_probe(); 1738 if (!err) 1739 ret = 0; 1740#endif 1741#ifdef CONFIG_PCI 1742 err = pci_register_driver(&cyberpro_driver); 1743 if (!err) 1744 ret = 0; 1745#endif 1746 1747 return ret ? err : 0; 1748} 1749module_init(cyber2000fb_init); 1750 1751#ifndef CONFIG_ARCH_SHARK 1752static void __exit cyberpro_exit(void) 1753{ 1754 pci_unregister_driver(&cyberpro_driver); 1755} 1756module_exit(cyberpro_exit); 1757#endif 1758 1759MODULE_AUTHOR("Russell King"); 1760MODULE_DESCRIPTION("CyberPro 2000, 2010 and 5000 framebuffer driver"); 1761MODULE_LICENSE("GPL"); 1762