1/* 2 * Copyright (C) 2005-2006 by Texas Instruments 3 * 4 * This file is part of the Inventra Controller Driver for Linux. 5 * 6 * The Inventra Controller Driver for Linux is free software; you 7 * can redistribute it and/or modify it under the terms of the GNU 8 * General Public License version 2 as published by the Free Software 9 * Foundation. 10 * 11 * The Inventra Controller Driver for Linux is distributed in 12 * the hope that it will be useful, but WITHOUT ANY WARRANTY; 13 * without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 * License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with The Inventra Controller Driver for Linux ; if not, 19 * write to the Free Software Foundation, Inc., 59 Temple Place, 20 * Suite 330, Boston, MA 02111-1307 USA 21 * 22 */ 23 24#include <linux/module.h> 25#include <linux/kernel.h> 26#include <linux/sched.h> 27#include <linux/init.h> 28#include <linux/list.h> 29#include <linux/delay.h> 30#include <linux/clk.h> 31#include <linux/io.h> 32#include <linux/gpio.h> 33 34#include <mach/hardware.h> 35#include <mach/memory.h> 36#include <mach/gpio.h> 37#include <mach/cputype.h> 38 39#include <asm/mach-types.h> 40 41#include "musb_core.h" 42 43#ifdef CONFIG_MACH_DAVINCI_EVM 44#define GPIO_nVBUS_DRV 160 45#endif 46 47#include "davinci.h" 48#include "cppi_dma.h" 49 50 51#define USB_PHY_CTRL IO_ADDRESS(USBPHY_CTL_PADDR) 52#define DM355_DEEPSLEEP IO_ADDRESS(DM355_DEEPSLEEP_PADDR) 53 54/* REVISIT (PM) we should be able to keep the PHY in low power mode most 55 * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0 56 * and, when in host mode, autosuspending idle root ports... PHYPLLON 57 * (overriding SUSPENDM?) then likely needs to stay off. 58 */ 59 60static inline void phy_on(void) 61{ 62 u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); 63 64 /* power everything up; start the on-chip PHY and its PLL */ 65 phy_ctrl &= ~(USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN); 66 phy_ctrl |= USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON; 67 __raw_writel(phy_ctrl, USB_PHY_CTRL); 68 69 /* wait for PLL to lock before proceeding */ 70 while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0) 71 cpu_relax(); 72} 73 74static inline void phy_off(void) 75{ 76 u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); 77 78 /* powerdown the on-chip PHY, its PLL, and the OTG block */ 79 phy_ctrl &= ~(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON); 80 phy_ctrl |= USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN; 81 __raw_writel(phy_ctrl, USB_PHY_CTRL); 82} 83 84static int dma_off = 1; 85 86void musb_platform_enable(struct musb *musb) 87{ 88 u32 tmp, old, val; 89 90 tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK) 91 << DAVINCI_USB_TXINT_SHIFT; 92 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); 93 old = tmp; 94 tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK)) 95 << DAVINCI_USB_RXINT_SHIFT; 96 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); 97 tmp |= old; 98 99 val = ~MUSB_INTR_SOF; 100 tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT); 101 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); 102 103 if (is_dma_capable() && !dma_off) 104 printk(KERN_WARNING "%s %s: dma not reactivated\n", 105 __FILE__, __func__); 106 else 107 dma_off = 0; 108 109 /* force a DRVVBUS irq so we can start polling for ID change */ 110 if (is_otg_enabled(musb)) 111 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG, 112 DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT); 113} 114 115/* 116 * Disable the HDRC and flush interrupts 117 */ 118void musb_platform_disable(struct musb *musb) 119{ 120 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG, 121 DAVINCI_USB_USBINT_MASK 122 | DAVINCI_USB_TXINT_MASK 123 | DAVINCI_USB_RXINT_MASK); 124 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 125 musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0); 126 127 if (is_dma_capable() && !dma_off) 128 WARNING("dma still active\n"); 129} 130 131 132#ifdef CONFIG_USB_MUSB_HDRC_HCD 133#define portstate(stmt) stmt 134#else 135#define portstate(stmt) 136#endif 137 138 139/* 140 * VBUS SWITCHING IS BOARD-SPECIFIC ... at least for the DM6446 EVM, 141 * which doesn't wire DRVVBUS to the FET that switches it. Unclear 142 * if that's a problem with the DM6446 chip or just with that board. 143 * 144 * In either case, the DM355 EVM automates DRVVBUS the normal way, 145 * when J10 is out, and TI documents it as handling OTG. 146 */ 147 148#ifdef CONFIG_MACH_DAVINCI_EVM 149 150static int vbus_state = -1; 151 152/* I2C operations are always synchronous, and require a task context. 153 * With unloaded systems, using the shared workqueue seems to suffice 154 * to satisfy the 100msec A_WAIT_VRISE timeout... 155 */ 156static void evm_deferred_drvvbus(struct work_struct *ignored) 157{ 158 gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state); 159 vbus_state = !vbus_state; 160} 161 162#endif /* EVM */ 163 164static void davinci_source_power(struct musb *musb, int is_on, int immediate) 165{ 166#ifdef CONFIG_MACH_DAVINCI_EVM 167 if (is_on) 168 is_on = 1; 169 170 if (vbus_state == is_on) 171 return; 172 vbus_state = !is_on; /* 0/1 vs "-1 == unknown/init" */ 173 174 if (machine_is_davinci_evm()) { 175 static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus); 176 177 if (immediate) 178 gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state); 179 else 180 schedule_work(&evm_vbus_work); 181 } 182 if (immediate) 183 vbus_state = is_on; 184#endif 185} 186 187static void davinci_set_vbus(struct musb *musb, int is_on) 188{ 189 WARN_ON(is_on && is_peripheral_active(musb)); 190 davinci_source_power(musb, is_on, 0); 191} 192 193 194#define POLL_SECONDS 2 195 196static struct timer_list otg_workaround; 197 198static void otg_timer(unsigned long _musb) 199{ 200 struct musb *musb = (void *)_musb; 201 void __iomem *mregs = musb->mregs; 202 u8 devctl; 203 unsigned long flags; 204 205 /* We poll because DaVinci's won't expose several OTG-critical 206 * status change events (from the transceiver) otherwise. 207 */ 208 devctl = musb_readb(mregs, MUSB_DEVCTL); 209 DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb)); 210 211 spin_lock_irqsave(&musb->lock, flags); 212 switch (musb->xceiv->state) { 213 case OTG_STATE_A_WAIT_VFALL: 214 /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL 215 * seems to mis-handle session "start" otherwise (or in our 216 * case "recover"), in routine "VBUS was valid by the time 217 * VBUSERR got reported during enumeration" cases. 218 */ 219 if (devctl & MUSB_DEVCTL_VBUS) { 220 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 221 break; 222 } 223 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; 224 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG, 225 MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT); 226 break; 227 case OTG_STATE_B_IDLE: 228 if (!is_peripheral_enabled(musb)) 229 break; 230 231 musb_writeb(mregs, MUSB_DEVCTL, 232 devctl | MUSB_DEVCTL_SESSION); 233 devctl = musb_readb(mregs, MUSB_DEVCTL); 234 if (devctl & MUSB_DEVCTL_BDEVICE) 235 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 236 else 237 musb->xceiv->state = OTG_STATE_A_IDLE; 238 break; 239 default: 240 break; 241 } 242 spin_unlock_irqrestore(&musb->lock, flags); 243} 244 245static irqreturn_t davinci_interrupt(int irq, void *__hci) 246{ 247 unsigned long flags; 248 irqreturn_t retval = IRQ_NONE; 249 struct musb *musb = __hci; 250 void __iomem *tibase = musb->ctrl_base; 251 struct cppi *cppi; 252 u32 tmp; 253 254 spin_lock_irqsave(&musb->lock, flags); 255 256 /* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through 257 * the Mentor registers (except for setup), use the TI ones and EOI. 258 * 259 * Docs describe irq "vector" registers associated with the CPPI and 260 * USB EOI registers. These hold a bitmask corresponding to the 261 * current IRQ, not an irq handler address. Would using those bits 262 * resolve some of the races observed in this dispatch code?? 263 */ 264 265 /* CPPI interrupts share the same IRQ line, but have their own 266 * mask, state, "vector", and EOI registers. 267 */ 268 cppi = container_of(musb->dma_controller, struct cppi, controller); 269 if (is_cppi_enabled() && musb->dma_controller && !cppi->irq) 270 retval = cppi_interrupt(irq, __hci); 271 272 /* ack and handle non-CPPI interrupts */ 273 tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG); 274 musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp); 275 DBG(4, "IRQ %08x\n", tmp); 276 277 musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK) 278 >> DAVINCI_USB_RXINT_SHIFT; 279 musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK) 280 >> DAVINCI_USB_TXINT_SHIFT; 281 musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK) 282 >> DAVINCI_USB_USBINT_SHIFT; 283 284 /* DRVVBUS irqs are the only proxy we have (a very poor one!) for 285 * DaVinci's missing ID change IRQ. We need an ID change IRQ to 286 * switch appropriately between halves of the OTG state machine. 287 * Managing DEVCTL.SESSION per Mentor docs requires we know its 288 * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set. 289 * Also, DRVVBUS pulses for SRP (but not at 5V) ... 290 */ 291 if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) { 292 int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG); 293 void __iomem *mregs = musb->mregs; 294 u8 devctl = musb_readb(mregs, MUSB_DEVCTL); 295 int err = musb->int_usb & MUSB_INTR_VBUSERROR; 296 297 err = is_host_enabled(musb) 298 && (musb->int_usb & MUSB_INTR_VBUSERROR); 299 if (err) { 300 musb->int_usb &= ~MUSB_INTR_VBUSERROR; 301 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 302 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 303 WARNING("VBUS error workaround (delay coming)\n"); 304 } else if (is_host_enabled(musb) && drvvbus) { 305 MUSB_HST_MODE(musb); 306 musb->xceiv->default_a = 1; 307 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; 308 portstate(musb->port1_status |= USB_PORT_STAT_POWER); 309 del_timer(&otg_workaround); 310 } else { 311 musb->is_active = 0; 312 MUSB_DEV_MODE(musb); 313 musb->xceiv->default_a = 0; 314 musb->xceiv->state = OTG_STATE_B_IDLE; 315 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); 316 } 317 318 /* NOTE: this must complete poweron within 100 msec 319 * (OTG_TIME_A_WAIT_VRISE) but we don't check for that. 320 */ 321 davinci_source_power(musb, drvvbus, 0); 322 DBG(2, "VBUS %s (%s)%s, devctl %02x\n", 323 drvvbus ? "on" : "off", 324 otg_state_string(musb), 325 err ? " ERROR" : "", 326 devctl); 327 retval = IRQ_HANDLED; 328 } 329 330 if (musb->int_tx || musb->int_rx || musb->int_usb) 331 retval |= musb_interrupt(musb); 332 333 /* irq stays asserted until EOI is written */ 334 musb_writel(tibase, DAVINCI_USB_EOI_REG, 0); 335 336 /* poll for ID change */ 337 if (is_otg_enabled(musb) 338 && musb->xceiv->state == OTG_STATE_B_IDLE) 339 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 340 341 spin_unlock_irqrestore(&musb->lock, flags); 342 343 return retval; 344} 345 346int musb_platform_set_mode(struct musb *musb, u8 mode) 347{ 348 /* EVM can't do this (right?) */ 349 return -EIO; 350} 351 352int __init musb_platform_init(struct musb *musb, void *board_data) 353{ 354 void __iomem *tibase = musb->ctrl_base; 355 u32 revision; 356 357 usb_nop_xceiv_register(); 358 musb->xceiv = otg_get_transceiver(); 359 if (!musb->xceiv) 360 return -ENODEV; 361 362 musb->mregs += DAVINCI_BASE_OFFSET; 363 364 clk_enable(musb->clock); 365 366 /* returns zero if e.g. not clocked */ 367 revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG); 368 if (revision == 0) 369 goto fail; 370 371 if (is_host_enabled(musb)) 372 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb); 373 374 musb->board_set_vbus = davinci_set_vbus; 375 davinci_source_power(musb, 0, 1); 376 377 /* dm355 EVM swaps D+/D- for signal integrity, and 378 * is clocked from the main 24 MHz crystal. 379 */ 380 if (machine_is_davinci_dm355_evm()) { 381 u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); 382 383 phy_ctrl &= ~(3 << 9); 384 phy_ctrl |= USBPHY_DATAPOL; 385 __raw_writel(phy_ctrl, USB_PHY_CTRL); 386 } 387 388 /* On dm355, the default-A state machine needs DRVVBUS control. 389 * If we won't be a host, there's no need to turn it on. 390 */ 391 if (cpu_is_davinci_dm355()) { 392 u32 deepsleep = __raw_readl(DM355_DEEPSLEEP); 393 394 if (is_host_enabled(musb)) { 395 deepsleep &= ~DRVVBUS_OVERRIDE; 396 } else { 397 deepsleep &= ~DRVVBUS_FORCE; 398 deepsleep |= DRVVBUS_OVERRIDE; 399 } 400 __raw_writel(deepsleep, DM355_DEEPSLEEP); 401 } 402 403 /* reset the controller */ 404 musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1); 405 406 /* start the on-chip PHY and its PLL */ 407 phy_on(); 408 409 msleep(5); 410 411 /* NOTE: irqs are in mixed mode, not bypass to pure-musb */ 412 pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n", 413 revision, __raw_readl(USB_PHY_CTRL), 414 musb_readb(tibase, DAVINCI_USB_CTRL_REG)); 415 416 musb->isr = davinci_interrupt; 417 return 0; 418 419fail: 420 clk_disable(musb->clock); 421 422 otg_put_transceiver(musb->xceiv); 423 usb_nop_xceiv_unregister(); 424 return -ENODEV; 425} 426 427int musb_platform_exit(struct musb *musb) 428{ 429 if (is_host_enabled(musb)) 430 del_timer_sync(&otg_workaround); 431 432 /* force VBUS off */ 433 if (cpu_is_davinci_dm355()) { 434 u32 deepsleep = __raw_readl(DM355_DEEPSLEEP); 435 436 deepsleep &= ~DRVVBUS_FORCE; 437 deepsleep |= DRVVBUS_OVERRIDE; 438 __raw_writel(deepsleep, DM355_DEEPSLEEP); 439 } 440 441 davinci_source_power(musb, 0 /*off*/, 1); 442 443 /* delay, to avoid problems with module reload */ 444 if (is_host_enabled(musb) && musb->xceiv->default_a) { 445 int maxdelay = 30; 446 u8 devctl, warn = 0; 447 448 /* if there's no peripheral connected, this can take a 449 * long time to fall, especially on EVM with huge C133. 450 */ 451 do { 452 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 453 if (!(devctl & MUSB_DEVCTL_VBUS)) 454 break; 455 if ((devctl & MUSB_DEVCTL_VBUS) != warn) { 456 warn = devctl & MUSB_DEVCTL_VBUS; 457 DBG(1, "VBUS %d\n", 458 warn >> MUSB_DEVCTL_VBUS_SHIFT); 459 } 460 msleep(1000); 461 maxdelay--; 462 } while (maxdelay > 0); 463 464 /* in OTG mode, another host might be connected */ 465 if (devctl & MUSB_DEVCTL_VBUS) 466 DBG(1, "VBUS off timeout (devctl %02x)\n", devctl); 467 } 468 469 phy_off(); 470 471 clk_disable(musb->clock); 472 473 otg_put_transceiver(musb->xceiv); 474 usb_nop_xceiv_unregister(); 475 476 return 0; 477} 478