1/* Modified by Broadcom Corp. Portions Copyright (c) Broadcom Corp, 2012. */ 2/* 3 * xHCI host controller driver 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software Foundation, 21 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24#ifndef __LINUX_XHCI_HCD_H 25#define __LINUX_XHCI_HCD_H 26 27#include <linux/usb.h> 28#include <linux/timer.h> 29#include <linux/kernel.h> 30#include <linux/usb/hcd.h> 31 32/* Code sharing between pci-quirks and xhci hcd */ 33#include "xhci-ext-caps.h" 34 35/* xHCI PCI Configuration Registers */ 36#define XHCI_SBRN_OFFSET (0x60) 37 38/* Max number of USB devices for any host controller - limit in section 6.1 */ 39#define MAX_HC_SLOTS 256 40/* Section 5.3.3 - MaxPorts */ 41#define MAX_HC_PORTS 127 42 43/* 44 * xHCI register interface. 45 * This corresponds to the eXtensible Host Controller Interface (xHCI) 46 * Revision 0.95 specification 47 */ 48 49/** 50 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 51 * @hc_capbase: length of the capabilities register and HC version number 52 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 53 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 54 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 55 * @hcc_params: HCCPARAMS - Capability Parameters 56 * @db_off: DBOFF - Doorbell array offset 57 * @run_regs_off: RTSOFF - Runtime register space offset 58 */ 59struct xhci_cap_regs { 60 u32 hc_capbase; 61 u32 hcs_params1; 62 u32 hcs_params2; 63 u32 hcs_params3; 64 u32 hcc_params; 65 u32 db_off; 66 u32 run_regs_off; 67 /* Reserved up to (CAPLENGTH - 0x1C) */ 68}; 69 70/* hc_capbase bitmasks */ 71/* bits 7:0 - how long is the Capabilities register */ 72#define HC_LENGTH(p) XHCI_HC_LENGTH(p) 73/* bits 31:16 */ 74#define HC_VERSION(p) (((p) >> 16) & 0xffff) 75 76/* HCSPARAMS1 - hcs_params1 - bitmasks */ 77/* bits 0:7, Max Device Slots */ 78#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 79#define HCS_SLOTS_MASK 0xff 80/* bits 8:18, Max Interrupters */ 81#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 82/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 83#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 84 85/* HCSPARAMS2 - hcs_params2 - bitmasks */ 86/* bits 0:3, frames or uframes that SW needs to queue transactions 87 * ahead of the HW to meet periodic deadlines */ 88#define HCS_IST(p) (((p) >> 0) & 0xf) 89/* bits 4:7, max number of Event Ring segments */ 90#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 91/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 92/* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */ 93#define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f) 94 95/* HCSPARAMS3 - hcs_params3 - bitmasks */ 96/* bits 0:7, Max U1 to U0 latency for the roothub ports */ 97#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 98/* bits 16:31, Max U2 to U0 latency for the roothub ports */ 99#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 100 101/* HCCPARAMS - hcc_params - bitmasks */ 102/* true: HC can use 64-bit address pointers */ 103#define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 104/* true: HC can do bandwidth negotiation */ 105#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 106#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 107/* true: HC has port power switches */ 108#define HCC_PPC(p) ((p) & (1 << 3)) 109/* true: HC has port indicators */ 110#define HCS_INDICATOR(p) ((p) & (1 << 4)) 111/* true: HC has Light HC Reset Capability */ 112#define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 113/* true: HC supports latency tolerance messaging */ 114#define HCC_LTC(p) ((p) & (1 << 6)) 115/* true: no secondary Stream ID Support */ 116#define HCC_NSS(p) ((p) & (1 << 7)) 117/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 118#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 119/* Extended Capabilities pointer from PCI base - section 5.3.6 */ 120#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 121 122/* db_off bitmask - bits 0:1 reserved */ 123#define DBOFF_MASK (~0x3) 124 125/* run_regs_off bitmask - bits 0:4 reserved */ 126#define RTSOFF_MASK (~0x1f) 127 128 129/* Number of registers per port */ 130#define NUM_PORT_REGS 4 131 132/** 133 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 134 * @command: USBCMD - xHC command register 135 * @status: USBSTS - xHC status register 136 * @page_size: This indicates the page size that the host controller 137 * supports. If bit n is set, the HC supports a page size 138 * of 2^(n+12), up to a 128MB page size. 139 * 4K is the minimum page size. 140 * @cmd_ring: CRP - 64-bit Command Ring Pointer 141 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 142 * @config_reg: CONFIG - Configure Register 143 * @port_status_base: PORTSCn - base address for Port Status and Control 144 * Each port has a Port Status and Control register, 145 * followed by a Port Power Management Status and Control 146 * register, a Port Link Info register, and a reserved 147 * register. 148 * @port_power_base: PORTPMSCn - base address for 149 * Port Power Management Status and Control 150 * @port_link_base: PORTLIn - base address for Port Link Info (current 151 * Link PM state and control) for USB 2.1 and USB 3.0 152 * devices. 153 */ 154struct xhci_op_regs { 155 u32 command; 156 u32 status; 157 u32 page_size; 158 u32 reserved1; 159 u32 reserved2; 160 u32 dev_notification; 161 u64 cmd_ring; 162 /* rsvd: offset 0x20-2F */ 163 u32 reserved3[4]; 164 u64 dcbaa_ptr; 165 u32 config_reg; 166 /* rsvd: offset 0x3C-3FF */ 167 u32 reserved4[241]; 168 /* port 1 registers, which serve as a base address for other ports */ 169 u32 port_status_base; 170 u32 port_power_base; 171 u32 port_link_base; 172 u32 reserved5; 173 /* registers for ports 2-255 */ 174 u32 reserved6[NUM_PORT_REGS*254]; 175}; 176 177/* USBCMD - USB command - command bitmasks */ 178/* start/stop HC execution - do not write unless HC is halted*/ 179#define CMD_RUN XHCI_CMD_RUN 180/* Reset HC - resets internal HC state machine and all registers (except 181 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 182 * The xHCI driver must reinitialize the xHC after setting this bit. 183 */ 184#define CMD_RESET (1 << 1) 185/* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 186#define CMD_EIE XHCI_CMD_EIE 187/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 188#define CMD_HSEIE XHCI_CMD_HSEIE 189/* bits 4:6 are reserved (and should be preserved on writes). */ 190/* light reset (port status stays unchanged) - reset completed when this is 0 */ 191#define CMD_LRESET (1 << 7) 192#define CMD_CSS (1 << 8) 193#define CMD_CRS (1 << 9) 194/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 195#define CMD_EWE XHCI_CMD_EWE 196/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 197 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 198 * '0' means the xHC can power it off if all ports are in the disconnect, 199 * disabled, or powered-off state. 200 */ 201#define CMD_PM_INDEX (1 << 11) 202/* bits 12:31 are reserved (and should be preserved on writes). */ 203 204/* USBSTS - USB status - status bitmasks */ 205/* HC not running - set to 1 when run/stop bit is cleared. */ 206#define STS_HALT XHCI_STS_HALT 207/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 208#define STS_FATAL (1 << 2) 209/* event interrupt - clear this prior to clearing any IP flags in IR set*/ 210#define STS_EINT (1 << 3) 211/* port change detect */ 212#define STS_PORT (1 << 4) 213/* bits 5:7 reserved and zeroed */ 214/* save state status - '1' means xHC is saving state */ 215#define STS_SAVE (1 << 8) 216/* restore state status - '1' means xHC is restoring state */ 217#define STS_RESTORE (1 << 9) 218/* true: save or restore error */ 219#define STS_SRE (1 << 10) 220/* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 221#define STS_CNR XHCI_STS_CNR 222/* true: internal Host Controller Error - SW needs to reset and reinitialize */ 223#define STS_HCE (1 << 12) 224/* bits 13:31 reserved and should be preserved */ 225 226/* 227 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 228 * Generate a device notification event when the HC sees a transaction with a 229 * notification type that matches a bit set in this bit field. 230 */ 231#define DEV_NOTE_MASK (0xffff) 232#define ENABLE_DEV_NOTE(x) (1 << x) 233/* Most of the device notification types should only be used for debug. 234 * SW does need to pay attention to function wake notifications. 235 */ 236#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 237 238/* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 239/* bit 0 is the command ring cycle state */ 240/* stop ring operation after completion of the currently executing command */ 241#define CMD_RING_PAUSE (1 << 1) 242/* stop ring immediately - abort the currently executing command */ 243#define CMD_RING_ABORT (1 << 2) 244/* true: command ring is running */ 245#define CMD_RING_RUNNING (1 << 3) 246/* bits 4:5 reserved and should be preserved */ 247/* Command Ring pointer - bit mask for the lower 32 bits. */ 248#define CMD_RING_RSVD_BITS (0x3f) 249 250/* CONFIG - Configure Register - config_reg bitmasks */ 251/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 252#define MAX_DEVS(p) ((p) & 0xff) 253/* bits 8:31 - reserved and should be preserved */ 254 255/* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 256/* true: device connected */ 257#define PORT_CONNECT (1 << 0) 258/* true: port enabled */ 259#define PORT_PE (1 << 1) 260/* bit 2 reserved and zeroed */ 261/* true: port has an over-current condition */ 262#define PORT_OC (1 << 3) 263/* true: port reset signaling asserted */ 264#define PORT_RESET (1 << 4) 265/* Port Link State - bits 5:8 266 * A read gives the current link PM state of the port, 267 * a write with Link State Write Strobe set sets the link state. 268 */ 269/* Port Link State - bits 5:8 270 * A read gives the current link PM state of the port, 271 * a write with Link State Write Strobe set sets the link state. 272 */ 273#define PORT_PLS_MASK (0xf << 5) 274#define XDEV_U0 (0x0 << 5) 275#define XDEV_U3 (0x3 << 5) 276#define XDEV_RESUME (0xf << 5) 277 278/* true: port has power (see HCC_PPC) */ 279#define PORT_POWER (1 << 9) 280/* bits 10:13 indicate device speed: 281 * 0 - undefined speed - port hasn't be initialized by a reset yet 282 * 1 - full speed 283 * 2 - low speed 284 * 3 - high speed 285 * 4 - super speed 286 * 5-15 reserved 287 */ 288#define DEV_SPEED_MASK (0xf << 10) 289#define XDEV_FS (0x1 << 10) 290#define XDEV_LS (0x2 << 10) 291#define XDEV_HS (0x3 << 10) 292#define XDEV_SS (0x4 << 10) 293#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 294#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 295#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 296#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 297#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 298/* Bits 20:23 in the Slot Context are the speed for the device */ 299#define SLOT_SPEED_FS (XDEV_FS << 10) 300#define SLOT_SPEED_LS (XDEV_LS << 10) 301#define SLOT_SPEED_HS (XDEV_HS << 10) 302#define SLOT_SPEED_SS (XDEV_SS << 10) 303/* Port Indicator Control */ 304#define PORT_LED_OFF (0 << 14) 305#define PORT_LED_AMBER (1 << 14) 306#define PORT_LED_GREEN (2 << 14) 307#define PORT_LED_MASK (3 << 14) 308/* Port Link State Write Strobe - set this when changing link state */ 309#define PORT_LINK_STROBE (1 << 16) 310/* true: connect status change */ 311#define PORT_CSC (1 << 17) 312/* true: port enable change */ 313#define PORT_PEC (1 << 18) 314/* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 315 * into an enabled state, and the device into the default state. A "warm" reset 316 * also resets the link, forcing the device through the link training sequence. 317 * SW can also look at the Port Reset register to see when warm reset is done. 318 */ 319#define PORT_WRC (1 << 19) 320/* true: over-current change */ 321#define PORT_OCC (1 << 20) 322/* true: reset change - 1 to 0 transition of PORT_RESET */ 323#define PORT_RC (1 << 21) 324/* port link status change - set on some port link state transitions: 325 * Transition Reason 326 * ------------------------------------------------------------------------------ 327 * - U3 to Resume Wakeup signaling from a device 328 * - Resume to Recovery to U0 USB 3.0 device resume 329 * - Resume to U0 USB 2.0 device resume 330 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 331 * - U3 to U0 Software resume of USB 2.0 device complete 332 * - U2 to U0 L1 resume of USB 2.1 device complete 333 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 334 * - U0 to disabled L1 entry error with USB 2.1 device 335 * - Any state to inactive Error on USB 3.0 port 336 */ 337#define PORT_PLC (1 << 22) 338/* port configure error change - port failed to configure its link partner */ 339#define PORT_CEC (1 << 23) 340/* bit 24 reserved */ 341/* wake on connect (enable) */ 342#define PORT_WKCONN_E (1 << 25) 343/* wake on disconnect (enable) */ 344#define PORT_WKDISC_E (1 << 26) 345/* wake on over-current (enable) */ 346#define PORT_WKOC_E (1 << 27) 347/* bits 28:29 reserved */ 348/* true: device is removable - for USB 3.0 roothub emulation */ 349#define PORT_DEV_REMOVE (1 << 30) 350/* Initiate a warm port reset - complete when PORT_WRC is '1' */ 351#define PORT_WR (1 << 31) 352 353/* Port Power Management Status and Control - port_power_base bitmasks */ 354/* Inactivity timer value for transitions into U1, in microseconds. 355 * Timeout can be up to 127us. 0xFF means an infinite timeout. 356 */ 357#define PORT_U1_TIMEOUT(p) ((p) & 0xff) 358/* Inactivity timer value for transitions into U2 */ 359#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 360/* Bits 24:31 for port testing */ 361 362 363/** 364 * struct xhci_intr_reg - Interrupt Register Set 365 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 366 * interrupts and check for pending interrupts. 367 * @irq_control: IMOD - Interrupt Moderation Register. 368 * Used to throttle interrupts. 369 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 370 * @erst_base: ERST base address. 371 * @erst_dequeue: Event ring dequeue pointer. 372 * 373 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 374 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 375 * multiple segments of the same size. The HC places events on the ring and 376 * "updates the Cycle bit in the TRBs to indicate to software the current 377 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 378 * updates the dequeue pointer. 379 */ 380struct xhci_intr_reg { 381 u32 irq_pending; 382 u32 irq_control; 383 u32 erst_size; 384 u32 rsvd; 385 u64 erst_base; 386 u64 erst_dequeue; 387}; 388 389/* irq_pending bitmasks */ 390#define ER_IRQ_PENDING(p) ((p) & 0x1) 391/* bits 2:31 need to be preserved */ 392#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 393#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 394#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 395 396/* irq_control bitmasks */ 397/* Minimum interval between interrupts (in 250ns intervals). The interval 398 * between interrupts will be longer if there are no events on the event ring. 399 * Default is 4000 (1 ms). 400 */ 401#define ER_IRQ_INTERVAL_MASK (0xffff) 402/* Counter used to count down the time to the next interrupt - HW use only */ 403#define ER_IRQ_COUNTER_MASK (0xffff << 16) 404 405/* erst_size bitmasks */ 406/* Preserve bits 16:31 of erst_size */ 407#define ERST_SIZE_MASK (0xffff << 16) 408 409/* erst_dequeue bitmasks */ 410/* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 411 * where the current dequeue pointer lies. This is an optional HW hint. 412 */ 413#define ERST_DESI_MASK (0x7) 414/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 415 * a work queue (or delayed service routine)? 416 */ 417#define ERST_EHB (1 << 3) 418#define ERST_PTR_MASK (0xf) 419 420/** 421 * struct xhci_run_regs 422 * @microframe_index: 423 * MFINDEX - current microframe number 424 * 425 * Section 5.5 Host Controller Runtime Registers: 426 * "Software should read and write these registers using only Dword (32 bit) 427 * or larger accesses" 428 */ 429struct xhci_run_regs { 430 u32 microframe_index; 431 u32 rsvd[7]; 432 struct xhci_intr_reg ir_set[128]; 433}; 434 435/** 436 * struct doorbell_array 437 * 438 * Section 5.6 439 */ 440struct xhci_doorbell_array { 441 u32 doorbell[256]; 442}; 443 444#define DB_TARGET_MASK 0xFFFFFF00 445#define DB_STREAM_ID_MASK 0x0000FFFF 446#define DB_TARGET_HOST 0x0 447#define DB_STREAM_ID_HOST 0x0 448#define DB_MASK (0xff << 8) 449 450/* Endpoint Target - bits 0:7 */ 451#define EPI_TO_DB(p) (((p) + 1) & 0xff) 452#define STREAM_ID_TO_DB(p) (((p) & 0xffff) << 16) 453 454 455/** 456 * struct xhci_protocol_caps 457 * @revision: major revision, minor revision, capability ID, 458 * and next capability pointer. 459 * @name_string: Four ASCII characters to say which spec this xHC 460 * follows, typically "USB ". 461 * @port_info: Port offset, count, and protocol-defined information. 462 */ 463struct xhci_protocol_caps { 464 u32 revision; 465 u32 name_string; 466 u32 port_info; 467}; 468 469#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 470#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 471#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 472 473/** 474 * struct xhci_container_ctx 475 * @type: Type of context. Used to calculated offsets to contained contexts. 476 * @size: Size of the context data 477 * @bytes: The raw context data given to HW 478 * @dma: dma address of the bytes 479 * 480 * Represents either a Device or Input context. Holds a pointer to the raw 481 * memory used for the context (bytes) and dma address of it (dma). 482 */ 483struct xhci_container_ctx { 484 unsigned type; 485#define XHCI_CTX_TYPE_DEVICE 0x1 486#define XHCI_CTX_TYPE_INPUT 0x2 487 488 int size; 489 490 u8 *bytes; 491 dma_addr_t dma; 492}; 493 494/** 495 * struct xhci_slot_ctx 496 * @dev_info: Route string, device speed, hub info, and last valid endpoint 497 * @dev_info2: Max exit latency for device number, root hub port number 498 * @tt_info: tt_info is used to construct split transaction tokens 499 * @dev_state: slot state and device address 500 * 501 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 502 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 503 * reserved at the end of the slot context for HC internal use. 504 */ 505struct xhci_slot_ctx { 506 u32 dev_info; 507 u32 dev_info2; 508 u32 tt_info; 509 u32 dev_state; 510 /* offset 0x10 to 0x1f reserved for HC internal use */ 511 u32 reserved[4]; 512}; 513 514/* dev_info bitmasks */ 515/* Route String - 0:19 */ 516#define ROUTE_STRING_MASK (0xfffff) 517/* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 518#define DEV_SPEED (0xf << 20) 519/* bit 24 reserved */ 520/* Is this LS/FS device connected through a HS hub? - bit 25 */ 521#define DEV_MTT (0x1 << 25) 522/* Set if the device is a hub - bit 26 */ 523#define DEV_HUB (0x1 << 26) 524/* Index of the last valid endpoint context in this device context - 27:31 */ 525#define LAST_CTX_MASK (0x1f << 27) 526#define LAST_CTX(p) ((p) << 27) 527#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 528#define SLOT_FLAG (1 << 0) 529#define EP0_FLAG (1 << 1) 530 531/* dev_info2 bitmasks */ 532/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 533#define MAX_EXIT (0xffff) 534/* Root hub port number that is needed to access the USB device */ 535#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 536/* Maximum number of ports under a hub device */ 537#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 538 539/* tt_info bitmasks */ 540/* 541 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 542 * The Slot ID of the hub that isolates the high speed signaling from 543 * this low or full-speed device. '0' if attached to root hub port. 544 */ 545#define TT_SLOT (0xff) 546/* 547 * The number of the downstream facing port of the high-speed hub 548 * '0' if the device is not low or full speed. 549 */ 550#define TT_PORT (0xff << 8) 551#define TT_THINK_TIME(p) (((p) & 0x3) << 16) 552 553/* dev_state bitmasks */ 554/* USB device address - assigned by the HC */ 555#define DEV_ADDR_MASK (0xff) 556/* bits 8:26 reserved */ 557/* Slot state */ 558#define SLOT_STATE (0x1f << 27) 559#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 560 561 562/** 563 * struct xhci_ep_ctx 564 * @ep_info: endpoint state, streams, mult, and interval information. 565 * @ep_info2: information on endpoint type, max packet size, max burst size, 566 * error count, and whether the HC will force an event for all 567 * transactions. 568 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 569 * defines one stream, this points to the endpoint transfer ring. 570 * Otherwise, it points to a stream context array, which has a 571 * ring pointer for each flow. 572 * @tx_info: 573 * Average TRB lengths for the endpoint ring and 574 * max payload within an Endpoint Service Interval Time (ESIT). 575 * 576 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 577 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 578 * reserved at the end of the endpoint context for HC internal use. 579 */ 580struct xhci_ep_ctx { 581 u32 ep_info; 582 u32 ep_info2; 583 u64 deq; 584 u32 tx_info; 585 /* offset 0x14 - 0x1f reserved for HC internal use */ 586 u32 reserved[3]; 587}; 588 589/* ep_info bitmasks */ 590/* 591 * Endpoint State - bits 0:2 592 * 0 - disabled 593 * 1 - running 594 * 2 - halted due to halt condition - ok to manipulate endpoint ring 595 * 3 - stopped 596 * 4 - TRB error 597 * 5-7 - reserved 598 */ 599#define EP_STATE_MASK (0xf) 600#define EP_STATE_DISABLED 0 601#define EP_STATE_RUNNING 1 602#define EP_STATE_HALTED 2 603#define EP_STATE_STOPPED 3 604#define EP_STATE_ERROR 4 605/* Mult - Max number of burtst within an interval, in EP companion desc. */ 606#define EP_MULT(p) ((p & 0x3) << 8) 607/* bits 10:14 are Max Primary Streams */ 608/* bit 15 is Linear Stream Array */ 609/* Interval - period between requests to an endpoint - 125u increments. */ 610#define EP_INTERVAL(p) ((p & 0xff) << 16) 611#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 612#define EP_MAXPSTREAMS_MASK (0x1f << 10) 613#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 614/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 615#define EP_HAS_LSA (1 << 15) 616 617/* ep_info2 bitmasks */ 618/* 619 * Force Event - generate transfer events for all TRBs for this endpoint 620 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 621 */ 622#define FORCE_EVENT (0x1) 623#define ERROR_COUNT(p) (((p) & 0x3) << 1) 624#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 625#define EP_TYPE(p) ((p) << 3) 626#define ISOC_OUT_EP 1 627#define BULK_OUT_EP 2 628#define INT_OUT_EP 3 629#define CTRL_EP 4 630#define ISOC_IN_EP 5 631#define BULK_IN_EP 6 632#define INT_IN_EP 7 633/* bit 6 reserved */ 634/* bit 7 is Host Initiate Disable - for disabling stream selection */ 635#define MAX_BURST(p) (((p)&0xff) << 8) 636#define MAX_PACKET(p) (((p)&0xffff) << 16) 637#define MAX_PACKET_MASK (0xffff << 16) 638#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 639 640/* Get max packet size from ep desc. Bit 10..0 specify the max packet size. 641 * USB2.0 spec 9.6.6. 642 */ 643#define GET_MAX_PACKET(p) ((p) & 0x7ff) 644 645/* tx_info bitmasks */ 646#define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff) 647#define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16) 648 649 650/** 651 * struct xhci_input_control_context 652 * Input control context; see section 6.2.5. 653 * 654 * @drop_context: set the bit of the endpoint context you want to disable 655 * @add_context: set the bit of the endpoint context you want to enable 656 */ 657struct xhci_input_control_ctx { 658 u32 drop_flags; 659 u32 add_flags; 660 u32 rsvd2[6]; 661}; 662 663/* Represents everything that is needed to issue a command on the command ring. 664 * It's useful to pre-allocate these for commands that cannot fail due to 665 * out-of-memory errors, like freeing streams. 666 */ 667struct xhci_command { 668 /* Input context for changing device state */ 669 struct xhci_container_ctx *in_ctx; 670 u32 status; 671 /* If completion is null, no one is waiting on this command 672 * and the structure can be freed after the command completes. 673 */ 674 struct completion *completion; 675 union xhci_trb *command_trb; 676 struct list_head cmd_list; 677}; 678 679/* drop context bitmasks */ 680#define DROP_EP(x) (0x1 << x) 681/* add context bitmasks */ 682#define ADD_EP(x) (0x1 << x) 683 684struct xhci_stream_ctx { 685 /* 64-bit stream ring address, cycle state, and stream type */ 686 u64 stream_ring; 687 /* offset 0x14 - 0x1f reserved for HC internal use */ 688 u32 reserved[2]; 689}; 690 691/* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 692#define SCT_FOR_CTX(p) (((p) << 1) & 0x7) 693/* Secondary stream array type, dequeue pointer is to a transfer ring */ 694#define SCT_SEC_TR 0 695/* Primary stream array type, dequeue pointer is to a transfer ring */ 696#define SCT_PRI_TR 1 697/* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 698#define SCT_SSA_8 2 699#define SCT_SSA_16 3 700#define SCT_SSA_32 4 701#define SCT_SSA_64 5 702#define SCT_SSA_128 6 703#define SCT_SSA_256 7 704 705/* Assume no secondary streams for now */ 706struct xhci_stream_info { 707 struct xhci_ring **stream_rings; 708 /* Number of streams, including stream 0 (which drivers can't use) */ 709 unsigned int num_streams; 710 /* The stream context array may be bigger than 711 * the number of streams the driver asked for 712 */ 713 struct xhci_stream_ctx *stream_ctx_array; 714 unsigned int num_stream_ctxs; 715 dma_addr_t ctx_array_dma; 716 /* For mapping physical TRB addresses to segments in stream rings */ 717 struct radix_tree_root trb_address_map; 718 struct xhci_command *free_streams_command; 719}; 720 721#define SMALL_STREAM_ARRAY_SIZE 256 722#define MEDIUM_STREAM_ARRAY_SIZE 1024 723 724struct xhci_virt_ep { 725 struct xhci_ring *ring; 726 /* Related to endpoints that are configured to use stream IDs only */ 727 struct xhci_stream_info *stream_info; 728 /* Temporary storage in case the configure endpoint command fails and we 729 * have to restore the device state to the previous state 730 */ 731 struct xhci_ring *new_ring; 732 unsigned int ep_state; 733#define SET_DEQ_PENDING (1 << 0) 734#define EP_HALTED (1 << 1) /* For stall handling */ 735#define EP_HALT_PENDING (1 << 2) /* For URB cancellation */ 736/* Transitioning the endpoint to using streams, don't enqueue URBs */ 737#define EP_GETTING_STREAMS (1 << 3) 738#define EP_HAS_STREAMS (1 << 4) 739/* Transitioning the endpoint to not using streams, don't enqueue URBs */ 740#define EP_GETTING_NO_STREAMS (1 << 5) 741 /* ---- Related to URB cancellation ---- */ 742 struct list_head cancelled_td_list; 743 /* The TRB that was last reported in a stopped endpoint ring */ 744 union xhci_trb *stopped_trb; 745 struct xhci_td *stopped_td; 746 unsigned int stopped_stream; 747 /* Watchdog timer for stop endpoint command to cancel URBs */ 748 struct timer_list stop_cmd_timer; 749 int stop_cmds_pending; 750 struct xhci_hcd *xhci; 751 /* 752 * Sometimes the xHC can not process isochronous endpoint ring quickly 753 * enough, and it will miss some isoc tds on the ring and generate 754 * a Missed Service Error Event. 755 * Set skip flag when receive a Missed Service Error Event and 756 * process the missed tds on the endpoint ring. 757 */ 758 bool skip; 759}; 760 761struct xhci_virt_device { 762 /* 763 * Commands to the hardware are passed an "input context" that 764 * tells the hardware what to change in its data structures. 765 * The hardware will return changes in an "output context" that 766 * software must allocate for the hardware. We need to keep 767 * track of input and output contexts separately because 768 * these commands might fail and we don't trust the hardware. 769 */ 770 struct xhci_container_ctx *out_ctx; 771 /* Used for addressing devices and configuration changes */ 772 struct xhci_container_ctx *in_ctx; 773 /* Rings saved to ensure old alt settings can be re-instated */ 774 struct xhci_ring **ring_cache; 775 int num_rings_cached; 776#define XHCI_MAX_RINGS_CACHED 31 777 struct xhci_virt_ep eps[31]; 778 struct completion cmd_completion; 779 /* Status of the last command issued for this device */ 780 u32 cmd_status; 781 struct list_head cmd_list; 782}; 783 784 785/** 786 * struct xhci_device_context_array 787 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 788 */ 789struct xhci_device_context_array { 790 /* 64-bit device addresses; we only write 32-bit addresses */ 791 u64 dev_context_ptrs[MAX_HC_SLOTS]; 792 /* private xHCD pointers */ 793 dma_addr_t dma; 794}; 795/* TODO: write function to set the 64-bit device DMA address */ 796/* 797 * TODO: change this to be dynamically sized at HC mem init time since the HC 798 * might not be able to handle the maximum number of devices possible. 799 */ 800 801 802struct xhci_transfer_event { 803 /* 64-bit buffer address, or immediate data */ 804 u64 buffer; 805 u32 transfer_len; 806 /* This field is interpreted differently based on the type of TRB */ 807 u32 flags; 808}; 809 810/** Transfer Event bit fields **/ 811#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 812 813/* Completion Code - only applicable for some types of TRBs */ 814#define COMP_CODE_MASK (0xff << 24) 815#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 816#define COMP_SUCCESS 1 817/* Data Buffer Error */ 818#define COMP_DB_ERR 2 819/* Babble Detected Error */ 820#define COMP_BABBLE 3 821/* USB Transaction Error */ 822#define COMP_TX_ERR 4 823/* TRB Error - some TRB field is invalid */ 824#define COMP_TRB_ERR 5 825/* Stall Error - USB device is stalled */ 826#define COMP_STALL 6 827/* Resource Error - HC doesn't have memory for that device configuration */ 828#define COMP_ENOMEM 7 829/* Bandwidth Error - not enough room in schedule for this dev config */ 830#define COMP_BW_ERR 8 831/* No Slots Available Error - HC ran out of device slots */ 832#define COMP_ENOSLOTS 9 833/* Invalid Stream Type Error */ 834#define COMP_STREAM_ERR 10 835/* Slot Not Enabled Error - doorbell rung for disabled device slot */ 836#define COMP_EBADSLT 11 837/* Endpoint Not Enabled Error */ 838#define COMP_EBADEP 12 839/* Short Packet */ 840#define COMP_SHORT_TX 13 841/* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ 842#define COMP_UNDERRUN 14 843/* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ 844#define COMP_OVERRUN 15 845/* Virtual Function Event Ring Full Error */ 846#define COMP_VF_FULL 16 847/* Parameter Error - Context parameter is invalid */ 848#define COMP_EINVAL 17 849/* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ 850#define COMP_BW_OVER 18 851/* Context State Error - illegal context state transition requested */ 852#define COMP_CTX_STATE 19 853/* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ 854#define COMP_PING_ERR 20 855/* Event Ring is full */ 856#define COMP_ER_FULL 21 857/* Missed Service Error - HC couldn't service an isoc ep within interval */ 858#define COMP_MISSED_INT 23 859/* Successfully stopped command ring */ 860#define COMP_CMD_STOP 24 861/* Successfully aborted current command and stopped command ring */ 862#define COMP_CMD_ABORT 25 863/* Stopped - transfer was terminated by a stop endpoint command */ 864#define COMP_STOP 26 865/* Same as COMP_EP_STOPPED, but the transfered length in the event is invalid */ 866#define COMP_STOP_INVAL 27 867/* Control Abort Error - Debug Capability - control pipe aborted */ 868#define COMP_DBG_ABORT 28 869/* TRB type 29 and 30 reserved */ 870/* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ 871#define COMP_BUFF_OVER 31 872/* Event Lost Error - xHC has an "internal event overrun condition" */ 873#define COMP_ISSUES 32 874/* Undefined Error - reported when other error codes don't apply */ 875#define COMP_UNKNOWN 33 876/* Invalid Stream ID Error */ 877#define COMP_STRID_ERR 34 878/* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ 879#define COMP_2ND_BW_ERR 35 880/* Split Transaction Error */ 881#define COMP_SPLIT_ERR 36 882 883struct xhci_link_trb { 884 /* 64-bit segment pointer*/ 885 u64 segment_ptr; 886 u32 intr_target; 887 u32 control; 888}; 889 890/* control bitfields */ 891#define LINK_TOGGLE (0x1<<1) 892 893/* Command completion event TRB */ 894struct xhci_event_cmd { 895 /* Pointer to command TRB, or the value passed by the event data trb */ 896 u64 cmd_trb; 897 u32 status; 898 u32 flags; 899}; 900 901/* flags bitmasks */ 902/* bits 16:23 are the virtual function ID */ 903/* bits 24:31 are the slot ID */ 904#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) 905#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 906 907/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 908#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 909#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 910 911/* Set TR Dequeue Pointer command TRB fields */ 912#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 913#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 914 915 916/* Port Status Change Event TRB fields */ 917/* Port ID - bits 31:24 */ 918#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 919 920/* Normal TRB fields */ 921/* transfer_len bitmasks - bits 0:16 */ 922#define TRB_LEN(p) ((p) & 0x1ffff) 923/* Interrupter Target - which MSI-X vector to target the completion event at */ 924#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 925#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 926 927/* Cycle bit - indicates TRB ownership by HC or HCD */ 928#define TRB_CYCLE (1<<0) 929/* 930 * Force next event data TRB to be evaluated before task switch. 931 * Used to pass OS data back after a TD completes. 932 */ 933#define TRB_ENT (1<<1) 934/* Interrupt on short packet */ 935#define TRB_ISP (1<<2) 936/* Set PCIe no snoop attribute */ 937#define TRB_NO_SNOOP (1<<3) 938/* Chain multiple TRBs into a TD */ 939#define TRB_CHAIN (1<<4) 940/* Interrupt on completion */ 941#define TRB_IOC (1<<5) 942/* The buffer pointer contains immediate data */ 943#define TRB_IDT (1<<6) 944 945 946/* Control transfer TRB specific fields */ 947#define TRB_DIR_IN (1<<16) 948 949#define TRB_TX_TYPE(p) ((p)<<16) 950#define TRB_DATA_OUT 2 951#define TRB_DATA_IN 3 952 953/* Isochronous TRB specific fields */ 954#define TRB_SIA (1<<31) 955 956struct xhci_generic_trb { 957 u32 field[4]; 958}; 959 960union xhci_trb { 961 struct xhci_link_trb link; 962 struct xhci_transfer_event trans_event; 963 struct xhci_event_cmd event_cmd; 964 struct xhci_generic_trb generic; 965}; 966 967/* TRB bit mask */ 968#define TRB_TYPE_BITMASK (0xfc00) 969#define TRB_TYPE(p) ((p) << 10) 970#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 971/* TRB type IDs */ 972/* bulk, interrupt, isoc scatter/gather, and control data stage */ 973#define TRB_NORMAL 1 974/* setup stage for control transfers */ 975#define TRB_SETUP 2 976/* data stage for control transfers */ 977#define TRB_DATA 3 978/* status stage for control transfers */ 979#define TRB_STATUS 4 980/* isoc transfers */ 981#define TRB_ISOC 5 982/* TRB for linking ring segments */ 983#define TRB_LINK 6 984#define TRB_EVENT_DATA 7 985/* Transfer Ring No-op (not for the command ring) */ 986#define TRB_TR_NOOP 8 987/* Command TRBs */ 988/* Enable Slot Command */ 989#define TRB_ENABLE_SLOT 9 990/* Disable Slot Command */ 991#define TRB_DISABLE_SLOT 10 992/* Address Device Command */ 993#define TRB_ADDR_DEV 11 994/* Configure Endpoint Command */ 995#define TRB_CONFIG_EP 12 996/* Evaluate Context Command */ 997#define TRB_EVAL_CONTEXT 13 998/* Reset Endpoint Command */ 999#define TRB_RESET_EP 14 1000/* Stop Transfer Ring Command */ 1001#define TRB_STOP_RING 15 1002/* Set Transfer Ring Dequeue Pointer Command */ 1003#define TRB_SET_DEQ 16 1004/* Reset Device Command */ 1005#define TRB_RESET_DEV 17 1006/* Force Event Command (opt) */ 1007#define TRB_FORCE_EVENT 18 1008/* Negotiate Bandwidth Command (opt) */ 1009#define TRB_NEG_BANDWIDTH 19 1010/* Set Latency Tolerance Value Command (opt) */ 1011#define TRB_SET_LT 20 1012/* Get port bandwidth Command */ 1013#define TRB_GET_BW 21 1014/* Force Header Command - generate a transaction or link management packet */ 1015#define TRB_FORCE_HEADER 22 1016/* No-op Command - not for transfer rings */ 1017#define TRB_CMD_NOOP 23 1018/* TRB IDs 24-31 reserved */ 1019/* Event TRBS */ 1020/* Transfer Event */ 1021#define TRB_TRANSFER 32 1022/* Command Completion Event */ 1023#define TRB_COMPLETION 33 1024/* Port Status Change Event */ 1025#define TRB_PORT_STATUS 34 1026/* Bandwidth Request Event (opt) */ 1027#define TRB_BANDWIDTH_EVENT 35 1028/* Doorbell Event (opt) */ 1029#define TRB_DOORBELL 36 1030/* Host Controller Event */ 1031#define TRB_HC_EVENT 37 1032/* Device Notification Event - device sent function wake notification */ 1033#define TRB_DEV_NOTE 38 1034/* MFINDEX Wrap Event - microframe counter wrapped */ 1035#define TRB_MFINDEX_WRAP 39 1036/* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1037 1038/* Nec vendor-specific command completion event. */ 1039#define TRB_NEC_CMD_COMP 48 1040/* Get NEC firmware revision. */ 1041#define TRB_NEC_GET_FW 49 1042 1043#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1044#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1045 1046/* 1047 * TRBS_PER_SEGMENT must be a multiple of 4, 1048 * since the command ring is 64-byte aligned. 1049 * It must also be greater than 16. 1050 */ 1051#ifdef CONFIG_BCM47XX 1052#define TRBS_PER_SEGMENT 256 1053#else 1054#define TRBS_PER_SEGMENT 64 1055#endif 1056 1057/* Allow two commands + a link TRB, along with any reserved command TRBs */ 1058#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1059#define SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1060/* SEGMENT_SHIFT should be log2(SEGMENT_SIZE). 1061 * Change this if you change TRBS_PER_SEGMENT! 1062 */ 1063#ifdef CONFIG_BCM47XX 1064#define SEGMENT_SHIFT 12 1065#else 1066#define SEGMENT_SHIFT 10 1067#endif 1068 1069/* TRB buffer pointers can't cross 64KB boundaries */ 1070#define TRB_MAX_BUFF_SHIFT 16 1071#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1072 1073struct xhci_segment { 1074 union xhci_trb *trbs; 1075 /* private to HCD */ 1076 struct xhci_segment *next; 1077 dma_addr_t dma; 1078}; 1079 1080struct xhci_td { 1081 struct list_head td_list; 1082 struct list_head cancelled_td_list; 1083 struct urb *urb; 1084 struct xhci_segment *start_seg; 1085 union xhci_trb *first_trb; 1086 union xhci_trb *last_trb; 1087}; 1088 1089struct xhci_dequeue_state { 1090 struct xhci_segment *new_deq_seg; 1091 union xhci_trb *new_deq_ptr; 1092 int new_cycle_state; 1093}; 1094 1095struct xhci_ring { 1096 struct xhci_segment *first_seg; 1097 union xhci_trb *enqueue; 1098 struct xhci_segment *enq_seg; 1099 unsigned int enq_updates; 1100 union xhci_trb *dequeue; 1101 struct xhci_segment *deq_seg; 1102 unsigned int deq_updates; 1103 struct list_head td_list; 1104 /* 1105 * Write the cycle state into the TRB cycle field to give ownership of 1106 * the TRB to the host controller (if we are the producer), or to check 1107 * if we own the TRB (if we are the consumer). See section 4.9.1. 1108 */ 1109 u32 cycle_state; 1110 unsigned int stream_id; 1111}; 1112 1113struct xhci_erst_entry { 1114 /* 64-bit event ring segment address */ 1115 u64 seg_addr; 1116 u32 seg_size; 1117 /* Set to zero */ 1118 u32 rsvd; 1119}; 1120 1121struct xhci_erst { 1122 struct xhci_erst_entry *entries; 1123 unsigned int num_entries; 1124 /* xhci->event_ring keeps track of segment dma addresses */ 1125 dma_addr_t erst_dma_addr; 1126 /* Num entries the ERST can contain */ 1127 unsigned int erst_size; 1128}; 1129 1130struct xhci_scratchpad { 1131 u64 *sp_array; 1132 dma_addr_t sp_dma; 1133 void **sp_buffers; 1134 dma_addr_t *sp_dma_buffers; 1135}; 1136 1137struct urb_priv { 1138 int length; 1139 int td_cnt; 1140 struct xhci_td *td[0]; 1141}; 1142 1143/* 1144 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1145 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1146 * meaning 64 ring segments. 1147 * Initial allocated size of the ERST, in number of entries */ 1148#define ERST_NUM_SEGS 1 1149/* Initial allocated size of the ERST, in number of entries */ 1150#define ERST_SIZE 64 1151/* Initial number of event segment rings allocated */ 1152#define ERST_ENTRIES 1 1153/* Poll every 60 seconds */ 1154#define POLL_TIMEOUT 60 1155/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1156#define XHCI_STOP_EP_CMD_TIMEOUT 5 1157 1158 1159/* There is one ehci_hci structure per controller */ 1160struct xhci_hcd { 1161 /* glue to PCI and HCD framework */ 1162 struct xhci_cap_regs __iomem *cap_regs; 1163 struct xhci_op_regs __iomem *op_regs; 1164 struct xhci_run_regs __iomem *run_regs; 1165 struct xhci_doorbell_array __iomem *dba; 1166 /* Our HCD's current interrupter register set */ 1167 struct xhci_intr_reg __iomem *ir_set; 1168 1169 /* Cached register copies of read-only HC data */ 1170 __u32 hcs_params1; 1171 __u32 hcs_params2; 1172 __u32 hcs_params3; 1173 __u32 hcc_params; 1174 1175 spinlock_t lock; 1176 1177 /* packed release number */ 1178 u8 sbrn; 1179 u16 hci_version; 1180 u8 max_slots; 1181 u8 max_interrupters; 1182 u8 max_ports; 1183 u8 isoc_threshold; 1184 int event_ring_max; 1185 int addr_64; 1186 /* 4KB min, 128MB max */ 1187 int page_size; 1188 /* Valid values are 12 to 20, inclusive */ 1189 int page_shift; 1190 /* msi-x vectors */ 1191 int msix_count; 1192 struct msix_entry *msix_entries; 1193 /* data structures */ 1194 struct xhci_device_context_array *dcbaa; 1195 struct xhci_ring *cmd_ring; 1196 unsigned int cmd_ring_reserved_trbs; 1197 struct xhci_ring *event_ring; 1198 struct xhci_erst erst; 1199 /* Scratchpad */ 1200 struct xhci_scratchpad *scratchpad; 1201 1202 /* slot enabling and address device helpers */ 1203 struct completion addr_dev; 1204 int slot_id; 1205 /* Internal mirror of the HW's dcbaa */ 1206 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1207 1208 /* DMA pools */ 1209 struct dma_pool *device_pool; 1210 struct dma_pool *segment_pool; 1211 struct dma_pool *small_streams_pool; 1212 struct dma_pool *medium_streams_pool; 1213 1214#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING 1215 /* Poll the rings - for debugging */ 1216 struct timer_list event_ring_timer; 1217 int zombie; 1218#endif 1219 /* Host controller watchdog timer structures */ 1220 unsigned int xhc_state; 1221/* Host controller is dying - not responding to commands. "I'm not dead yet!" 1222 * 1223 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1224 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1225 * that sees this status (other than the timer that set it) should stop touching 1226 * hardware immediately. Interrupt handlers should return immediately when 1227 * they see this status (any time they drop and re-acquire xhci->lock). 1228 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1229 * putting the TD on the canceled list, etc. 1230 * 1231 * There are no reports of xHCI host controllers that display this issue. 1232 */ 1233#define XHCI_STATE_DYING (1 << 0) 1234 /* Statistics */ 1235 int noops_submitted; 1236 int noops_handled; 1237 int error_bitmask; 1238 unsigned int quirks; 1239#define XHCI_LINK_TRB_QUIRK (1 << 0) 1240#define XHCI_RESET_EP_QUIRK (1 << 1) 1241#define XHCI_NEC_HOST (1 << 2) 1242 1243 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */ 1244 u8 *port_array; 1245 /* Array of pointers to USB 3.0 PORTSC registers */ 1246 u32 __iomem **usb3_ports; 1247 unsigned int num_usb3_ports; 1248 /* Array of pointers to USB 2.0 PORTSC registers */ 1249 u32 __iomem **usb2_ports; 1250 unsigned int num_usb2_ports; 1251}; 1252 1253/* For testing purposes */ 1254#define NUM_TEST_NOOPS 0 1255 1256/* convert between an HCD pointer and the corresponding EHCI_HCD */ 1257static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1258{ 1259 return (struct xhci_hcd *) (hcd->hcd_priv); 1260} 1261 1262static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1263{ 1264 return container_of((void *) xhci, struct usb_hcd, hcd_priv); 1265} 1266 1267#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING 1268#define XHCI_DEBUG 1 1269#else 1270#define XHCI_DEBUG 0 1271#endif 1272 1273#define xhci_dbg(xhci, fmt, args...) \ 1274 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) 1275#define xhci_info(xhci, fmt, args...) \ 1276 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) 1277#define xhci_err(xhci, fmt, args...) \ 1278 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1279#define xhci_warn(xhci, fmt, args...) \ 1280 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1281 1282/* TODO: copied from ehci.h - can be refactored? */ 1283/* xHCI spec says all registers are little endian */ 1284static inline unsigned int xhci_readl(const struct xhci_hcd *xhci, 1285 __u32 __iomem *regs) 1286{ 1287 return readl(regs); 1288} 1289static inline void xhci_writel(struct xhci_hcd *xhci, 1290 const unsigned int val, __u32 __iomem *regs) 1291{ 1292 xhci_dbg(xhci, 1293 "`MEM_WRITE_DWORD(3'b000, 32'h%p, 32'h%0x, 4'hf);\n", 1294 regs, val); 1295 writel(val, regs); 1296} 1297 1298/* 1299 * Registers should always be accessed with double word or quad word accesses. 1300 * 1301 * Some xHCI implementations may support 64-bit address pointers. Registers 1302 * with 64-bit address pointers should be written to with dword accesses by 1303 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1304 * xHCI implementations that do not support 64-bit address pointers will ignore 1305 * the high dword, and write order is irrelevant. 1306 */ 1307static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1308 __u64 __iomem *regs) 1309{ 1310 __u32 __iomem *ptr = (__u32 __iomem *) regs; 1311 u64 val_lo = readl(ptr); 1312 u64 val_hi = readl(ptr + 1); 1313 return val_lo + (val_hi << 32); 1314} 1315static inline void xhci_write_64(struct xhci_hcd *xhci, 1316 const u64 val, __u64 __iomem *regs) 1317{ 1318 __u32 __iomem *ptr = (__u32 __iomem *) regs; 1319 u32 val_lo = lower_32_bits(val); 1320 u32 val_hi = upper_32_bits(val); 1321 1322 xhci_dbg(xhci, 1323 "`MEM_WRITE_DWORD(3'b000, 64'h%p, 64'h%0lx, 4'hf);\n", 1324 regs, (long unsigned int) val); 1325 writel(val_lo, ptr); 1326 writel(val_hi, ptr + 1); 1327} 1328 1329static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) 1330{ 1331 u32 temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase); 1332 return ((HC_VERSION(temp) == 0x95) && 1333 (xhci->quirks & XHCI_LINK_TRB_QUIRK)); 1334} 1335 1336/* xHCI debugging */ 1337void xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num); 1338void xhci_print_registers(struct xhci_hcd *xhci); 1339void xhci_dbg_regs(struct xhci_hcd *xhci); 1340void xhci_print_run_regs(struct xhci_hcd *xhci); 1341void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb); 1342void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb); 1343void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg); 1344void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring); 1345void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); 1346void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); 1347void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring); 1348void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep); 1349char *xhci_get_slot_state(struct xhci_hcd *xhci, 1350 struct xhci_container_ctx *ctx); 1351void xhci_dbg_ep_rings(struct xhci_hcd *xhci, 1352 unsigned int slot_id, unsigned int ep_index, 1353 struct xhci_virt_ep *ep); 1354 1355/* xHCI memory management */ 1356void xhci_mem_cleanup(struct xhci_hcd *xhci); 1357int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1358void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 1359int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1360int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1361void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1362 struct usb_device *udev); 1363unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1364unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc); 1365unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index); 1366unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1367void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1368void xhci_endpoint_copy(struct xhci_hcd *xhci, 1369 struct xhci_container_ctx *in_ctx, 1370 struct xhci_container_ctx *out_ctx, 1371 unsigned int ep_index); 1372void xhci_slot_copy(struct xhci_hcd *xhci, 1373 struct xhci_container_ctx *in_ctx, 1374 struct xhci_container_ctx *out_ctx); 1375int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1376 struct usb_device *udev, struct usb_host_endpoint *ep, 1377 gfp_t mem_flags); 1378void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1379void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, 1380 struct xhci_virt_device *virt_dev, 1381 unsigned int ep_index); 1382struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1383 unsigned int num_stream_ctxs, 1384 unsigned int num_streams, gfp_t flags); 1385void xhci_free_stream_info(struct xhci_hcd *xhci, 1386 struct xhci_stream_info *stream_info); 1387void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 1388 struct xhci_ep_ctx *ep_ctx, 1389 struct xhci_stream_info *stream_info); 1390void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci, 1391 struct xhci_ep_ctx *ep_ctx, 1392 struct xhci_virt_ep *ep); 1393struct xhci_ring *xhci_dma_to_transfer_ring( 1394 struct xhci_virt_ep *ep, 1395 u64 address); 1396struct xhci_ring *xhci_stream_id_to_ring( 1397 struct xhci_virt_device *dev, 1398 unsigned int ep_index, 1399 unsigned int stream_id); 1400struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1401 bool allocate_in_ctx, bool allocate_completion, 1402 gfp_t mem_flags); 1403void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv); 1404void xhci_free_command(struct xhci_hcd *xhci, 1405 struct xhci_command *command); 1406 1407#ifdef CONFIG_PCI 1408/* xHCI PCI glue */ 1409int xhci_register_pci(void); 1410void xhci_unregister_pci(void); 1411#endif 1412 1413/* xHCI host controller glue */ 1414void xhci_quiesce(struct xhci_hcd *xhci); 1415int xhci_halt(struct xhci_hcd *xhci); 1416int xhci_reset(struct xhci_hcd *xhci); 1417int xhci_init(struct usb_hcd *hcd); 1418int xhci_run(struct usb_hcd *hcd); 1419void xhci_stop(struct usb_hcd *hcd); 1420void xhci_shutdown(struct usb_hcd *hcd); 1421int xhci_get_frame(struct usb_hcd *hcd); 1422irqreturn_t xhci_irq(struct usb_hcd *hcd); 1423irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd); 1424int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 1425void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev); 1426int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, 1427 struct usb_host_endpoint **eps, unsigned int num_eps, 1428 unsigned int num_streams, gfp_t mem_flags); 1429int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, 1430 struct usb_host_endpoint **eps, unsigned int num_eps, 1431 gfp_t mem_flags); 1432int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev); 1433int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 1434 struct usb_tt *tt, gfp_t mem_flags); 1435int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); 1436int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); 1437int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1438int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1439void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep); 1440int xhci_reset_device(struct usb_hcd *hcd, struct usb_device *udev); 1441int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1442void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1443 1444/* xHCI ring, segment, TRB, and TD functions */ 1445dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 1446struct xhci_segment *trb_in_td(struct xhci_segment *start_seg, 1447 union xhci_trb *start_trb, union xhci_trb *end_trb, 1448 dma_addr_t suspect_dma); 1449int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 1450void xhci_ring_cmd_db(struct xhci_hcd *xhci); 1451void *xhci_setup_one_noop(struct xhci_hcd *xhci); 1452int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id); 1453int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1454 u32 slot_id); 1455int xhci_queue_vendor_command(struct xhci_hcd *xhci, 1456 u32 field1, u32 field2, u32 field3, u32 field4); 1457int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, 1458 unsigned int ep_index); 1459int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1460 int slot_id, unsigned int ep_index); 1461int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1462 int slot_id, unsigned int ep_index); 1463int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1464 int slot_id, unsigned int ep_index); 1465int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 1466 struct urb *urb, int slot_id, unsigned int ep_index); 1467int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1468 u32 slot_id, bool command_must_succeed); 1469int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1470 u32 slot_id); 1471int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id, 1472 unsigned int ep_index); 1473int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id); 1474void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, 1475 unsigned int slot_id, unsigned int ep_index, 1476 unsigned int stream_id, struct xhci_td *cur_td, 1477 struct xhci_dequeue_state *state); 1478void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, 1479 unsigned int slot_id, unsigned int ep_index, 1480 unsigned int stream_id, 1481 struct xhci_dequeue_state *deq_state); 1482void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, 1483 struct usb_device *udev, unsigned int ep_index); 1484void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci, 1485 unsigned int slot_id, unsigned int ep_index, 1486 struct xhci_dequeue_state *deq_state); 1487void xhci_stop_endpoint_command_watchdog(unsigned long arg); 1488 1489#ifdef CONFIG_BCM47XX 1490void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 1491 unsigned int ep_index, unsigned int stream_id); 1492#endif /* CONFIG_BCM47XX */ 1493 1494/* xHCI roothub code */ 1495int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 1496 char *buf, u16 wLength); 1497int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 1498 1499/* xHCI contexts */ 1500struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1501struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1502struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 1503 1504#endif /* __LINUX_XHCI_HCD_H */ 1505