1/* 2 * OHCI HCD (Host Controller Driver) for USB. 3 * 4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 5 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net> 6 * 7 * [ Initialisation is based on Linus' ] 8 * [ uhci code and gregs ohci fragments ] 9 * [ (C) Copyright 1999 Linus Torvalds ] 10 * [ (C) Copyright 1999 Gregory P. Smith] 11 * 12 * 13 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller 14 * interfaces (though some non-x86 Intel chips use it). It supports 15 * smarter hardware than UHCI. A download link for the spec available 16 * through the http://www.usb.org website. 17 * 18 * This file is licenced under the GPL. 19 */ 20 21#include <linux/module.h> 22#include <linux/moduleparam.h> 23#include <linux/pci.h> 24#include <linux/kernel.h> 25#include <linux/delay.h> 26#include <linux/ioport.h> 27#include <linux/sched.h> 28#include <linux/slab.h> 29#include <linux/errno.h> 30#include <linux/init.h> 31#include <linux/timer.h> 32#include <linux/list.h> 33#include <linux/usb.h> 34#include <linux/usb/otg.h> 35#include <linux/usb/hcd.h> 36#include <linux/dma-mapping.h> 37#include <linux/dmapool.h> 38#include <linux/workqueue.h> 39#include <linux/debugfs.h> 40 41#include <asm/io.h> 42#include <asm/irq.h> 43#include <asm/system.h> 44#include <asm/unaligned.h> 45#include <asm/byteorder.h> 46 47 48#define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell" 49#define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver" 50 51/*-------------------------------------------------------------------------*/ 52 53#undef OHCI_VERBOSE_DEBUG /* not always helpful */ 54 55/* For initializing controller (mask in an HCFS mode too) */ 56#define OHCI_CONTROL_INIT OHCI_CTRL_CBSR 57#define OHCI_INTR_INIT \ 58 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \ 59 | OHCI_INTR_RD | OHCI_INTR_WDH) 60 61#ifdef __hppa__ 62/* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ 63#define IR_DISABLE 64#endif 65 66#ifdef CONFIG_ARCH_OMAP 67/* OMAP doesn't support IR (no SMM; not needed) */ 68#define IR_DISABLE 69#endif 70 71/*-------------------------------------------------------------------------*/ 72 73static const char hcd_name [] = "ohci_hcd"; 74 75#define STATECHANGE_DELAY msecs_to_jiffies(300) 76 77#include "ohci.h" 78 79static void ohci_dump (struct ohci_hcd *ohci, int verbose); 80static int ohci_init (struct ohci_hcd *ohci); 81static void ohci_stop (struct usb_hcd *hcd); 82 83#if defined(CONFIG_PM) || defined(CONFIG_PCI) 84static int ohci_restart (struct ohci_hcd *ohci); 85#endif 86 87#ifdef CONFIG_PCI 88static void quirk_amd_pll(int state); 89static void amd_iso_dev_put(void); 90static void sb800_prefetch(struct ohci_hcd *ohci, int on); 91#else 92static inline void quirk_amd_pll(int state) 93{ 94 return; 95} 96static inline void amd_iso_dev_put(void) 97{ 98 return; 99} 100static inline void sb800_prefetch(struct ohci_hcd *ohci, int on) 101{ 102 return; 103} 104#endif 105 106 107#include "ohci-hub.c" 108#include "ohci-dbg.c" 109#include "ohci-mem.c" 110#include "ohci-q.c" 111 112 113/* 114 * On architectures with edge-triggered interrupts we must never return 115 * IRQ_NONE. 116 */ 117#if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */ 118#define IRQ_NOTMINE IRQ_HANDLED 119#else 120#define IRQ_NOTMINE IRQ_NONE 121#endif 122 123 124/* Some boards misreport power switching/overcurrent */ 125static int distrust_firmware = 1; 126module_param (distrust_firmware, bool, 0); 127MODULE_PARM_DESC (distrust_firmware, 128 "true to distrust firmware power/overcurrent setup"); 129 130/* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */ 131static int no_handshake = 0; 132module_param (no_handshake, bool, 0); 133MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake"); 134 135/*-------------------------------------------------------------------------*/ 136 137/* 138 * queue up an urb for anything except the root hub 139 */ 140static int ohci_urb_enqueue ( 141 struct usb_hcd *hcd, 142 struct urb *urb, 143 gfp_t mem_flags 144) { 145 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 146 struct ed *ed; 147 urb_priv_t *urb_priv; 148 unsigned int pipe = urb->pipe; 149 int i, size = 0; 150 unsigned long flags; 151 int retval = 0; 152 153#ifdef OHCI_VERBOSE_DEBUG 154 urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS); 155#endif 156 157 /* every endpoint has a ed, locate and maybe (re)initialize it */ 158 if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval))) 159 return -ENOMEM; 160 161 /* for the private part of the URB we need the number of TDs (size) */ 162 switch (ed->type) { 163 case PIPE_CONTROL: 164 /* td_submit_urb() doesn't yet handle these */ 165 if (urb->transfer_buffer_length > 4096) 166 return -EMSGSIZE; 167 168 /* 1 TD for setup, 1 for ACK, plus ... */ 169 size = 2; 170 /* FALLTHROUGH */ 171 // case PIPE_INTERRUPT: 172 // case PIPE_BULK: 173 default: 174 /* one TD for every 4096 Bytes (can be upto 8K) */ 175 size += urb->transfer_buffer_length / 4096; 176 /* ... and for any remaining bytes ... */ 177 if ((urb->transfer_buffer_length % 4096) != 0) 178 size++; 179 /* ... and maybe a zero length packet to wrap it up */ 180 if (size == 0) 181 size++; 182 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0 183 && (urb->transfer_buffer_length 184 % usb_maxpacket (urb->dev, pipe, 185 usb_pipeout (pipe))) == 0) 186 size++; 187 break; 188 case PIPE_ISOCHRONOUS: /* number of packets from URB */ 189 size = urb->number_of_packets; 190 break; 191 } 192 193 /* allocate the private part of the URB */ 194 urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *), 195 mem_flags); 196 if (!urb_priv) 197 return -ENOMEM; 198 INIT_LIST_HEAD (&urb_priv->pending); 199 urb_priv->length = size; 200 urb_priv->ed = ed; 201 202 /* allocate the TDs (deferring hash chain updates) */ 203 for (i = 0; i < size; i++) { 204 urb_priv->td [i] = td_alloc (ohci, mem_flags); 205 if (!urb_priv->td [i]) { 206 urb_priv->length = i; 207 urb_free_priv (ohci, urb_priv); 208 return -ENOMEM; 209 } 210 } 211 212 spin_lock_irqsave (&ohci->lock, flags); 213 214 /* don't submit to a dead HC */ 215 if (!HCD_HW_ACCESSIBLE(hcd)) { 216 retval = -ENODEV; 217 goto fail; 218 } 219 if (!HC_IS_RUNNING(hcd->state)) { 220 retval = -ENODEV; 221 goto fail; 222 } 223 retval = usb_hcd_link_urb_to_ep(hcd, urb); 224 if (retval) 225 goto fail; 226 227 /* schedule the ed if needed */ 228 if (ed->state == ED_IDLE) { 229 retval = ed_schedule (ohci, ed); 230 if (retval < 0) { 231 usb_hcd_unlink_urb_from_ep(hcd, urb); 232 goto fail; 233 } 234 if (ed->type == PIPE_ISOCHRONOUS) { 235 u16 frame = ohci_frame_no(ohci); 236 237 /* delay a few frames before the first TD */ 238 frame += max_t (u16, 8, ed->interval); 239 frame &= ~(ed->interval - 1); 240 frame |= ed->branch; 241 urb->start_frame = frame; 242 243 /* yes, only URB_ISO_ASAP is supported, and 244 * urb->start_frame is never used as input. 245 */ 246 } 247 } else if (ed->type == PIPE_ISOCHRONOUS) 248 urb->start_frame = ed->last_iso + ed->interval; 249 250 /* fill the TDs and link them to the ed; and 251 * enable that part of the schedule, if needed 252 * and update count of queued periodic urbs 253 */ 254 urb->hcpriv = urb_priv; 255 td_submit_urb (ohci, urb); 256 257fail: 258 if (retval) 259 urb_free_priv (ohci, urb_priv); 260 spin_unlock_irqrestore (&ohci->lock, flags); 261 return retval; 262} 263 264/* 265 * decouple the URB from the HC queues (TDs, urb_priv). 266 * reporting is always done 267 * asynchronously, and we might be dealing with an urb that's 268 * partially transferred, or an ED with other urbs being unlinked. 269 */ 270static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 271{ 272 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 273 unsigned long flags; 274 int rc; 275 276#ifdef OHCI_VERBOSE_DEBUG 277 urb_print(urb, "UNLINK", 1, status); 278#endif 279 280 spin_lock_irqsave (&ohci->lock, flags); 281 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 282 if (rc) { 283 ; /* Do nothing */ 284 } else if (HC_IS_RUNNING(hcd->state)) { 285 urb_priv_t *urb_priv; 286 287 /* Unless an IRQ completed the unlink while it was being 288 * handed to us, flag it for unlink and giveback, and force 289 * some upcoming INTR_SF to call finish_unlinks() 290 */ 291 urb_priv = urb->hcpriv; 292 if (urb_priv) { 293 if (urb_priv->ed->state == ED_OPER) 294 start_ed_unlink (ohci, urb_priv->ed); 295 } 296 } else { 297 /* 298 * with HC dead, we won't respect hc queue pointers 299 * any more ... just clean up every urb's memory. 300 */ 301 if (urb->hcpriv) 302 finish_urb(ohci, urb, status); 303 } 304 spin_unlock_irqrestore (&ohci->lock, flags); 305 return rc; 306} 307 308/*-------------------------------------------------------------------------*/ 309 310/* frees config/altsetting state for endpoints, 311 * including ED memory, dummy TD, and bulk/intr data toggle 312 */ 313 314static void 315ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) 316{ 317 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 318 unsigned long flags; 319 struct ed *ed = ep->hcpriv; 320 unsigned limit = 1000; 321 322 /* ASSERT: any requests/urbs are being unlinked */ 323 /* ASSERT: nobody can be submitting urbs for this any more */ 324 325 if (!ed) 326 return; 327 328rescan: 329 spin_lock_irqsave (&ohci->lock, flags); 330 331 if (!HC_IS_RUNNING (hcd->state)) { 332sanitize: 333 ed->state = ED_IDLE; 334 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT) 335 ohci->eds_scheduled--; 336 finish_unlinks (ohci, 0); 337 } 338 339 switch (ed->state) { 340 case ED_UNLINK: /* wait for hw to finish? */ 341 /* major IRQ delivery trouble loses INTR_SF too... */ 342 if (limit-- == 0) { 343 ohci_warn(ohci, "ED unlink timeout\n"); 344 if (quirk_zfmicro(ohci)) { 345 ohci_warn(ohci, "Attempting ZF TD recovery\n"); 346 ohci->ed_to_check = ed; 347 ohci->zf_delay = 2; 348 } 349 goto sanitize; 350 } 351 spin_unlock_irqrestore (&ohci->lock, flags); 352 schedule_timeout_uninterruptible(1); 353 goto rescan; 354 case ED_IDLE: /* fully unlinked */ 355 if (list_empty (&ed->td_list)) { 356 td_free (ohci, ed->dummy); 357 ed_free (ohci, ed); 358 break; 359 } 360 /* else FALL THROUGH */ 361 default: 362 /* caller was supposed to have unlinked any requests; 363 * that's not our job. can't recover; must leak ed. 364 */ 365 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n", 366 ed, ep->desc.bEndpointAddress, ed->state, 367 list_empty (&ed->td_list) ? "" : " (has tds)"); 368 td_free (ohci, ed->dummy); 369 break; 370 } 371 ep->hcpriv = NULL; 372 spin_unlock_irqrestore (&ohci->lock, flags); 373 return; 374} 375 376static int ohci_get_frame (struct usb_hcd *hcd) 377{ 378 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 379 380 return ohci_frame_no(ohci); 381} 382 383static void ohci_usb_reset (struct ohci_hcd *ohci) 384{ 385 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control); 386 ohci->hc_control &= OHCI_CTRL_RWC; 387 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 388} 389 390/* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and 391 * other cases where the next software may expect clean state from the 392 * "firmware". this is bus-neutral, unlike shutdown() methods. 393 */ 394static void 395ohci_shutdown (struct usb_hcd *hcd) 396{ 397 struct ohci_hcd *ohci; 398 399 ohci = hcd_to_ohci (hcd); 400 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); 401 ohci_usb_reset (ohci); 402 /* flush the writes */ 403 (void) ohci_readl (ohci, &ohci->regs->control); 404} 405 406static int check_ed(struct ohci_hcd *ohci, struct ed *ed) 407{ 408 return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0 409 && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK) 410 == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK) 411 && !list_empty(&ed->td_list); 412} 413 414/* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes 415 * an interrupt TD but neglects to add it to the donelist. On systems with 416 * this chipset, we need to periodically check the state of the queues to look 417 * for such "lost" TDs. 418 */ 419static void unlink_watchdog_func(unsigned long _ohci) 420{ 421 unsigned long flags; 422 unsigned max; 423 unsigned seen_count = 0; 424 unsigned i; 425 struct ed **seen = NULL; 426 struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci; 427 428 spin_lock_irqsave(&ohci->lock, flags); 429 max = ohci->eds_scheduled; 430 if (!max) 431 goto done; 432 433 if (ohci->ed_to_check) 434 goto out; 435 436 seen = kcalloc(max, sizeof *seen, GFP_ATOMIC); 437 if (!seen) 438 goto out; 439 440 for (i = 0; i < NUM_INTS; i++) { 441 struct ed *ed = ohci->periodic[i]; 442 443 while (ed) { 444 unsigned temp; 445 446 /* scan this branch of the periodic schedule tree */ 447 for (temp = 0; temp < seen_count; temp++) { 448 if (seen[temp] == ed) { 449 /* we've checked it and what's after */ 450 ed = NULL; 451 break; 452 } 453 } 454 if (!ed) 455 break; 456 seen[seen_count++] = ed; 457 if (!check_ed(ohci, ed)) { 458 ed = ed->ed_next; 459 continue; 460 } 461 462 /* HC's TD list is empty, but HCD sees at least one 463 * TD that's not been sent through the donelist. 464 */ 465 ohci->ed_to_check = ed; 466 ohci->zf_delay = 2; 467 468 /* The HC may wait until the next frame to report the 469 * TD as done through the donelist and INTR_WDH. (We 470 * just *assume* it's not a multi-TD interrupt URB; 471 * those could defer the IRQ more than one frame, using 472 * DI...) Check again after the next INTR_SF. 473 */ 474 ohci_writel(ohci, OHCI_INTR_SF, 475 &ohci->regs->intrstatus); 476 ohci_writel(ohci, OHCI_INTR_SF, 477 &ohci->regs->intrenable); 478 479 /* flush those writes */ 480 (void) ohci_readl(ohci, &ohci->regs->control); 481 482 goto out; 483 } 484 } 485out: 486 kfree(seen); 487 if (ohci->eds_scheduled) 488 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ)); 489done: 490 spin_unlock_irqrestore(&ohci->lock, flags); 491} 492 493/*-------------------------------------------------------------------------* 494 * HC functions 495 *-------------------------------------------------------------------------*/ 496 497/* init memory, and kick BIOS/SMM off */ 498 499static int ohci_init (struct ohci_hcd *ohci) 500{ 501 int ret; 502 struct usb_hcd *hcd = ohci_to_hcd(ohci); 503 504 if (distrust_firmware) 505 ohci->flags |= OHCI_QUIRK_HUB_POWER; 506 507 disable (ohci); 508 ohci->regs = hcd->regs; 509 510 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and 511 * was never needed for most non-PCI systems ... remove the code? 512 */ 513 514#ifndef IR_DISABLE 515 /* SMM owns the HC? not for long! */ 516 if (!no_handshake && ohci_readl (ohci, 517 &ohci->regs->control) & OHCI_CTRL_IR) { 518 u32 temp; 519 520 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n"); 521 522 /* this timeout is arbitrary. we make it long, so systems 523 * depending on usb keyboards may be usable even if the 524 * BIOS/SMM code seems pretty broken. 525 */ 526 temp = 500; /* arbitrary: five seconds */ 527 528 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable); 529 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus); 530 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) { 531 msleep (10); 532 if (--temp == 0) { 533 ohci_err (ohci, "USB HC takeover failed!" 534 " (BIOS/SMM bug)\n"); 535 return -EBUSY; 536 } 537 } 538 ohci_usb_reset (ohci); 539 } 540#endif 541 542 /* Disable HC interrupts */ 543 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); 544 545 /* flush the writes, and save key bits like RWC */ 546 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC) 547 ohci->hc_control |= OHCI_CTRL_RWC; 548 549 /* Read the number of ports unless overridden */ 550 if (ohci->num_ports == 0) 551 ohci->num_ports = roothub_a(ohci) & RH_A_NDP; 552 553 if (ohci->hcca) 554 return 0; 555 556 ohci->hcca = dma_alloc_coherent (hcd->self.controller, 557 sizeof *ohci->hcca, &ohci->hcca_dma, 0); 558 if (!ohci->hcca) 559 return -ENOMEM; 560 561 if ((ret = ohci_mem_init (ohci)) < 0) 562 ohci_stop (hcd); 563 else { 564 create_debug_files (ohci); 565 } 566 567 return ret; 568} 569 570/*-------------------------------------------------------------------------*/ 571 572/* Start an OHCI controller, set the BUS operational 573 * resets USB and controller 574 * enable interrupts 575 */ 576static int ohci_run (struct ohci_hcd *ohci) 577{ 578 u32 mask, val; 579 int first = ohci->fminterval == 0; 580 struct usb_hcd *hcd = ohci_to_hcd(ohci); 581 582 disable (ohci); 583 584 /* boot firmware should have set this up (5.1.1.3.1) */ 585 if (first) { 586 587 val = ohci_readl (ohci, &ohci->regs->fminterval); 588 ohci->fminterval = val & 0x3fff; 589 if (ohci->fminterval != FI) 590 ohci_dbg (ohci, "fminterval delta %d\n", 591 ohci->fminterval - FI); 592 ohci->fminterval |= FSMP (ohci->fminterval) << 16; 593 /* also: power/overcurrent flags in roothub.a */ 594 } 595 596 /* Reset USB nearly "by the book". RemoteWakeupConnected has 597 * to be checked in case boot firmware (BIOS/SMM/...) has set up 598 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM). 599 * If the bus glue detected wakeup capability then it should 600 * already be enabled; if so we'll just enable it again. 601 */ 602 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0) 603 device_set_wakeup_capable(hcd->self.controller, 1); 604 605 switch (ohci->hc_control & OHCI_CTRL_HCFS) { 606 case OHCI_USB_OPER: 607 val = 0; 608 break; 609 case OHCI_USB_SUSPEND: 610 case OHCI_USB_RESUME: 611 ohci->hc_control &= OHCI_CTRL_RWC; 612 ohci->hc_control |= OHCI_USB_RESUME; 613 val = 10 /* msec wait */; 614 break; 615 // case OHCI_USB_RESET: 616 default: 617 ohci->hc_control &= OHCI_CTRL_RWC; 618 ohci->hc_control |= OHCI_USB_RESET; 619 val = 50 /* msec wait */; 620 break; 621 } 622 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 623 // flush the writes 624 (void) ohci_readl (ohci, &ohci->regs->control); 625 msleep(val); 626 627 memset (ohci->hcca, 0, sizeof (struct ohci_hcca)); 628 629 /* 2msec timelimit here means no irqs/preempt */ 630 spin_lock_irq (&ohci->lock); 631 632retry: 633 /* HC Reset requires max 10 us delay */ 634 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus); 635 val = 30; /* ... allow extra time */ 636 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) { 637 if (--val == 0) { 638 spin_unlock_irq (&ohci->lock); 639 ohci_err (ohci, "USB HC reset timed out!\n"); 640 return -1; 641 } 642 udelay (1); 643 } 644 645 /* now we're in the SUSPEND state ... must go OPERATIONAL 646 * within 2msec else HC enters RESUME 647 * 648 * ... but some hardware won't init fmInterval "by the book" 649 * (SiS, OPTi ...), so reset again instead. SiS doesn't need 650 * this if we write fmInterval after we're OPERATIONAL. 651 * Unclear about ALi, ServerWorks, and others ... this could 652 * easily be a longstanding bug in chip init on Linux. 653 */ 654 if (ohci->flags & OHCI_QUIRK_INITRESET) { 655 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 656 // flush those writes 657 (void) ohci_readl (ohci, &ohci->regs->control); 658 } 659 660 /* Tell the controller where the control and bulk lists are 661 * The lists are empty now. */ 662 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead); 663 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead); 664 665 /* a reset clears this */ 666 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca); 667 668 periodic_reinit (ohci); 669 670 /* some OHCI implementations are finicky about how they init. 671 * bogus values here mean not even enumeration could work. 672 */ 673 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0 674 || !ohci_readl (ohci, &ohci->regs->periodicstart)) { 675 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) { 676 ohci->flags |= OHCI_QUIRK_INITRESET; 677 ohci_dbg (ohci, "enabling initreset quirk\n"); 678 goto retry; 679 } 680 spin_unlock_irq (&ohci->lock); 681 ohci_err (ohci, "init err (%08x %04x)\n", 682 ohci_readl (ohci, &ohci->regs->fminterval), 683 ohci_readl (ohci, &ohci->regs->periodicstart)); 684 return -EOVERFLOW; 685 } 686 687 /* use rhsc irqs after khubd is fully initialized */ 688 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 689 hcd->uses_new_polling = 1; 690 691 /* start controller operations */ 692 ohci->hc_control &= OHCI_CTRL_RWC; 693 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER; 694 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 695 hcd->state = HC_STATE_RUNNING; 696 697 /* wake on ConnectStatusChange, matching external hubs */ 698 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status); 699 700 /* Choose the interrupts we care about now, others later on demand */ 701 mask = OHCI_INTR_INIT; 702 ohci_writel (ohci, ~0, &ohci->regs->intrstatus); 703 ohci_writel (ohci, mask, &ohci->regs->intrenable); 704 705 /* handle root hub init quirks ... */ 706 val = roothub_a (ohci); 707 val &= ~(RH_A_PSM | RH_A_OCPM); 708 if (ohci->flags & OHCI_QUIRK_SUPERIO) { 709 /* NSC 87560 and maybe others */ 710 val |= RH_A_NOCP; 711 val &= ~(RH_A_POTPGT | RH_A_NPS); 712 ohci_writel (ohci, val, &ohci->regs->roothub.a); 713 } else if ((ohci->flags & OHCI_QUIRK_AMD756) || 714 (ohci->flags & OHCI_QUIRK_HUB_POWER)) { 715 /* hub power always on; required for AMD-756 and some 716 * Mac platforms. ganged overcurrent reporting, if any. 717 */ 718 val |= RH_A_NPS; 719 ohci_writel (ohci, val, &ohci->regs->roothub.a); 720 } 721 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status); 722 ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM, 723 &ohci->regs->roothub.b); 724 // flush those writes 725 (void) ohci_readl (ohci, &ohci->regs->control); 726 727 ohci->next_statechange = jiffies + STATECHANGE_DELAY; 728 spin_unlock_irq (&ohci->lock); 729 730 // POTPGT delay is bits 24-31, in 2 ms units. 731 mdelay ((val >> 23) & 0x1fe); 732 hcd->state = HC_STATE_RUNNING; 733 734 if (quirk_zfmicro(ohci)) { 735 /* Create timer to watch for bad queue state on ZF Micro */ 736 setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func, 737 (unsigned long) ohci); 738 739 ohci->eds_scheduled = 0; 740 ohci->ed_to_check = NULL; 741 } 742 743 ohci_dump (ohci, 1); 744 745 return 0; 746} 747 748/*-------------------------------------------------------------------------*/ 749 750/* an interrupt happens */ 751 752static irqreturn_t ohci_irq (struct usb_hcd *hcd) 753{ 754 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 755 struct ohci_regs __iomem *regs = ohci->regs; 756 int ints; 757 758 /* Read interrupt status (and flush pending writes). We ignore the 759 * optimization of checking the LSB of hcca->done_head; it doesn't 760 * work on all systems (edge triggering for OHCI can be a factor). 761 */ 762 ints = ohci_readl(ohci, ®s->intrstatus); 763 764 /* Check for an all 1's result which is a typical consequence 765 * of dead, unclocked, or unplugged (CardBus...) devices 766 */ 767 if (ints == ~(u32)0) { 768 disable (ohci); 769 ohci_dbg (ohci, "device removed!\n"); 770 return IRQ_HANDLED; 771 } 772 773 /* We only care about interrupts that are enabled */ 774 ints &= ohci_readl(ohci, ®s->intrenable); 775 776 /* interrupt for some other device? */ 777 if (ints == 0) 778 return IRQ_NOTMINE; 779 780 if (ints & OHCI_INTR_UE) { 781 // e.g. due to PCI Master/Target Abort 782 if (quirk_nec(ohci)) { 783 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n"); 784 785 ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable); 786 787 schedule_work (&ohci->nec_work); 788 } else { 789 disable (ohci); 790 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n"); 791 } 792 793 ohci_dump (ohci, 1); 794 ohci_usb_reset (ohci); 795 } 796 797 if (ints & OHCI_INTR_RHSC) { 798 ohci_vdbg(ohci, "rhsc\n"); 799 ohci->next_statechange = jiffies + STATECHANGE_DELAY; 800 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC, 801 ®s->intrstatus); 802 803 /* NOTE: Vendors didn't always make the same implementation 804 * choices for RHSC. Many followed the spec; RHSC triggers 805 * on an edge, like setting and maybe clearing a port status 806 * change bit. With others it's level-triggered, active 807 * until khubd clears all the port status change bits. We'll 808 * always disable it here and rely on polling until khubd 809 * re-enables it. 810 */ 811 ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable); 812 usb_hcd_poll_rh_status(hcd); 813 } 814 815 /* For connect and disconnect events, we expect the controller 816 * to turn on RHSC along with RD. But for remote wakeup events 817 * this might not happen. 818 */ 819 else if (ints & OHCI_INTR_RD) { 820 ohci_vdbg(ohci, "resume detect\n"); 821 ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus); 822 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 823 if (ohci->autostop) { 824 spin_lock (&ohci->lock); 825 ohci_rh_resume (ohci); 826 spin_unlock (&ohci->lock); 827 } else 828 usb_hcd_resume_root_hub(hcd); 829 } 830 831 if (ints & OHCI_INTR_WDH) { 832 spin_lock (&ohci->lock); 833 dl_done_list (ohci); 834 spin_unlock (&ohci->lock); 835 } 836 837 if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) { 838 spin_lock(&ohci->lock); 839 if (ohci->ed_to_check) { 840 struct ed *ed = ohci->ed_to_check; 841 842 if (check_ed(ohci, ed)) { 843 /* HC thinks the TD list is empty; HCD knows 844 * at least one TD is outstanding 845 */ 846 if (--ohci->zf_delay == 0) { 847 struct td *td = list_entry( 848 ed->td_list.next, 849 struct td, td_list); 850 ohci_warn(ohci, 851 "Reclaiming orphan TD %p\n", 852 td); 853 takeback_td(ohci, td); 854 ohci->ed_to_check = NULL; 855 } 856 } else 857 ohci->ed_to_check = NULL; 858 } 859 spin_unlock(&ohci->lock); 860 } 861 862 /* could track INTR_SO to reduce available PCI/... bandwidth */ 863 864 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled 865 * when there's still unlinking to be done (next frame). 866 */ 867 spin_lock (&ohci->lock); 868 if (ohci->ed_rm_list) 869 finish_unlinks (ohci, ohci_frame_no(ohci)); 870 if ((ints & OHCI_INTR_SF) != 0 871 && !ohci->ed_rm_list 872 && !ohci->ed_to_check 873 && HC_IS_RUNNING(hcd->state)) 874 ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable); 875 spin_unlock (&ohci->lock); 876 877 if (HC_IS_RUNNING(hcd->state)) { 878 ohci_writel (ohci, ints, ®s->intrstatus); 879 ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable); 880 // flush those writes 881 (void) ohci_readl (ohci, &ohci->regs->control); 882 } 883 884 return IRQ_HANDLED; 885} 886 887/*-------------------------------------------------------------------------*/ 888 889static void ohci_stop (struct usb_hcd *hcd) 890{ 891 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 892 893 ohci_dump (ohci, 1); 894 895 flush_scheduled_work(); 896 897 ohci_usb_reset (ohci); 898 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); 899 free_irq(hcd->irq, hcd); 900 hcd->irq = -1; 901 902 if (quirk_zfmicro(ohci)) 903 del_timer(&ohci->unlink_watchdog); 904 if (quirk_amdiso(ohci)) 905 amd_iso_dev_put(); 906 907 remove_debug_files (ohci); 908 ohci_mem_cleanup (ohci); 909 if (ohci->hcca) { 910 dma_free_coherent (hcd->self.controller, 911 sizeof *ohci->hcca, 912 ohci->hcca, ohci->hcca_dma); 913 ohci->hcca = NULL; 914 ohci->hcca_dma = 0; 915 } 916} 917 918/*-------------------------------------------------------------------------*/ 919 920#if defined(CONFIG_PM) || defined(CONFIG_PCI) 921 922/* must not be called from interrupt context */ 923static int ohci_restart (struct ohci_hcd *ohci) 924{ 925 int temp; 926 int i; 927 struct urb_priv *priv; 928 929 spin_lock_irq(&ohci->lock); 930 disable (ohci); 931 932 /* Recycle any "live" eds/tds (and urbs). */ 933 if (!list_empty (&ohci->pending)) 934 ohci_dbg(ohci, "abort schedule...\n"); 935 list_for_each_entry (priv, &ohci->pending, pending) { 936 struct urb *urb = priv->td[0]->urb; 937 struct ed *ed = priv->ed; 938 939 switch (ed->state) { 940 case ED_OPER: 941 ed->state = ED_UNLINK; 942 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE); 943 ed_deschedule (ohci, ed); 944 945 ed->ed_next = ohci->ed_rm_list; 946 ed->ed_prev = NULL; 947 ohci->ed_rm_list = ed; 948 /* FALLTHROUGH */ 949 case ED_UNLINK: 950 break; 951 default: 952 ohci_dbg(ohci, "bogus ed %p state %d\n", 953 ed, ed->state); 954 } 955 956 if (!urb->unlinked) 957 urb->unlinked = -ESHUTDOWN; 958 } 959 finish_unlinks (ohci, 0); 960 spin_unlock_irq(&ohci->lock); 961 962 /* paranoia, in case that didn't work: */ 963 964 /* empty the interrupt branches */ 965 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0; 966 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0; 967 968 /* no EDs to remove */ 969 ohci->ed_rm_list = NULL; 970 971 /* empty control and bulk lists */ 972 ohci->ed_controltail = NULL; 973 ohci->ed_bulktail = NULL; 974 975 if ((temp = ohci_run (ohci)) < 0) { 976 ohci_err (ohci, "can't restart, %d\n", temp); 977 return temp; 978 } 979 ohci_dbg(ohci, "restart complete\n"); 980 return 0; 981} 982 983#endif 984 985/*-------------------------------------------------------------------------*/ 986 987MODULE_AUTHOR (DRIVER_AUTHOR); 988MODULE_DESCRIPTION(DRIVER_DESC); 989MODULE_LICENSE ("GPL"); 990 991#ifdef CONFIG_PCI 992#include "ohci-pci.c" 993#define PCI_DRIVER ohci_pci_driver 994#endif 995 996#if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111) 997#include "ohci-sa1111.c" 998#define SA1111_DRIVER ohci_hcd_sa1111_driver 999#endif 1000 1001#if defined(CONFIG_ARCH_S3C2410) || defined(CONFIG_ARCH_S3C64XX) 1002#include "ohci-s3c2410.c" 1003#define PLATFORM_DRIVER ohci_hcd_s3c2410_driver 1004#endif 1005 1006#ifdef CONFIG_USB_OHCI_HCD_OMAP1 1007#include "ohci-omap.c" 1008#define OMAP1_PLATFORM_DRIVER ohci_hcd_omap_driver 1009#endif 1010 1011#ifdef CONFIG_USB_OHCI_HCD_OMAP3 1012#include "ohci-omap3.c" 1013#define OMAP3_PLATFORM_DRIVER ohci_hcd_omap3_driver 1014#endif 1015 1016#ifdef CONFIG_ARCH_LH7A404 1017#include "ohci-lh7a404.c" 1018#define PLATFORM_DRIVER ohci_hcd_lh7a404_driver 1019#endif 1020 1021#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 1022#include "ohci-pxa27x.c" 1023#define PLATFORM_DRIVER ohci_hcd_pxa27x_driver 1024#endif 1025 1026#ifdef CONFIG_ARCH_EP93XX 1027#include "ohci-ep93xx.c" 1028#define PLATFORM_DRIVER ohci_hcd_ep93xx_driver 1029#endif 1030 1031#ifdef CONFIG_MIPS_ALCHEMY 1032#include "ohci-au1xxx.c" 1033#define PLATFORM_DRIVER ohci_hcd_au1xxx_driver 1034#endif 1035 1036#ifdef CONFIG_PNX8550 1037#include "ohci-pnx8550.c" 1038#define PLATFORM_DRIVER ohci_hcd_pnx8550_driver 1039#endif 1040 1041#ifdef CONFIG_USB_OHCI_HCD_PPC_SOC 1042#include "ohci-ppc-soc.c" 1043#define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver 1044#endif 1045 1046#ifdef CONFIG_ARCH_AT91 1047#include "ohci-at91.c" 1048#define PLATFORM_DRIVER ohci_hcd_at91_driver 1049#endif 1050 1051#ifdef CONFIG_ARCH_PNX4008 1052#include "ohci-pnx4008.c" 1053#define PLATFORM_DRIVER usb_hcd_pnx4008_driver 1054#endif 1055 1056#ifdef CONFIG_ARCH_DAVINCI_DA8XX 1057#include "ohci-da8xx.c" 1058#define PLATFORM_DRIVER ohci_hcd_da8xx_driver 1059#endif 1060 1061#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 1062 defined(CONFIG_CPU_SUBTYPE_SH7763) || defined(CONFIG_CPU_SUBTYPE_SH7786) 1063#include "ohci-sh.c" 1064#define PLATFORM_DRIVER ohci_hcd_sh_driver 1065#endif 1066 1067 1068#ifdef CONFIG_USB_OHCI_HCD_PPC_OF 1069#include "ohci-ppc-of.c" 1070#define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver 1071#endif 1072 1073#ifdef CONFIG_PPC_PS3 1074#include "ohci-ps3.c" 1075#define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver 1076#endif 1077 1078#ifdef CONFIG_USB_OHCI_HCD_SSB 1079#include "ohci-ssb.c" 1080#define SSB_OHCI_DRIVER ssb_ohci_driver 1081#endif 1082 1083#ifdef CONFIG_MFD_SM501 1084#include "ohci-sm501.c" 1085#define SM501_OHCI_DRIVER ohci_hcd_sm501_driver 1086#endif 1087 1088#ifdef CONFIG_MFD_TC6393XB 1089#include "ohci-tmio.c" 1090#define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver 1091#endif 1092 1093#ifdef CONFIG_MACH_JZ4740 1094#include "ohci-jz4740.c" 1095#define PLATFORM_DRIVER ohci_hcd_jz4740_driver 1096#endif 1097 1098#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ 1099 !defined(OMAP1_PLATFORM_DRIVER) && !defined(OMAP3_PLATFORM_DRIVER) && \ 1100 !defined(OF_PLATFORM_DRIVER) && !defined(SA1111_DRIVER) && \ 1101 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(SM501_OHCI_DRIVER) && \ 1102 !defined(TMIO_OHCI_DRIVER) && !defined(SSB_OHCI_DRIVER) 1103#error "missing bus glue for ohci-hcd" 1104#endif 1105 1106static int __init ohci_hcd_mod_init(void) 1107{ 1108 int retval = 0; 1109 1110 if (usb_disabled()) 1111 return -ENODEV; 1112 1113 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); 1114 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name, 1115 sizeof (struct ed), sizeof (struct td)); 1116 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded); 1117 1118#ifdef DEBUG 1119 ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root); 1120 if (!ohci_debug_root) { 1121 retval = -ENOENT; 1122 goto error_debug; 1123 } 1124#endif 1125 1126#ifdef PS3_SYSTEM_BUS_DRIVER 1127 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER); 1128 if (retval < 0) 1129 goto error_ps3; 1130#endif 1131 1132#ifdef PLATFORM_DRIVER 1133 retval = platform_driver_register(&PLATFORM_DRIVER); 1134 if (retval < 0) 1135 goto error_platform; 1136#endif 1137 1138#ifdef OMAP1_PLATFORM_DRIVER 1139 retval = platform_driver_register(&OMAP1_PLATFORM_DRIVER); 1140 if (retval < 0) 1141 goto error_omap1_platform; 1142#endif 1143 1144#ifdef OMAP3_PLATFORM_DRIVER 1145 retval = platform_driver_register(&OMAP3_PLATFORM_DRIVER); 1146 if (retval < 0) 1147 goto error_omap3_platform; 1148#endif 1149 1150#ifdef OF_PLATFORM_DRIVER 1151 retval = of_register_platform_driver(&OF_PLATFORM_DRIVER); 1152 if (retval < 0) 1153 goto error_of_platform; 1154#endif 1155 1156#ifdef SA1111_DRIVER 1157 retval = sa1111_driver_register(&SA1111_DRIVER); 1158 if (retval < 0) 1159 goto error_sa1111; 1160#endif 1161 1162#ifdef PCI_DRIVER 1163 retval = pci_register_driver(&PCI_DRIVER); 1164 if (retval < 0) 1165 goto error_pci; 1166#endif 1167 1168#ifdef SSB_OHCI_DRIVER 1169 retval = ssb_driver_register(&SSB_OHCI_DRIVER); 1170 if (retval) 1171 goto error_ssb; 1172#endif 1173 1174#ifdef SM501_OHCI_DRIVER 1175 retval = platform_driver_register(&SM501_OHCI_DRIVER); 1176 if (retval < 0) 1177 goto error_sm501; 1178#endif 1179 1180#ifdef TMIO_OHCI_DRIVER 1181 retval = platform_driver_register(&TMIO_OHCI_DRIVER); 1182 if (retval < 0) 1183 goto error_tmio; 1184#endif 1185 1186 return retval; 1187 1188 /* Error path */ 1189#ifdef TMIO_OHCI_DRIVER 1190 platform_driver_unregister(&TMIO_OHCI_DRIVER); 1191 error_tmio: 1192#endif 1193#ifdef SM501_OHCI_DRIVER 1194 platform_driver_unregister(&SM501_OHCI_DRIVER); 1195 error_sm501: 1196#endif 1197#ifdef SSB_OHCI_DRIVER 1198 ssb_driver_unregister(&SSB_OHCI_DRIVER); 1199 error_ssb: 1200#endif 1201#ifdef PCI_DRIVER 1202 pci_unregister_driver(&PCI_DRIVER); 1203 error_pci: 1204#endif 1205#ifdef SA1111_DRIVER 1206 sa1111_driver_unregister(&SA1111_DRIVER); 1207 error_sa1111: 1208#endif 1209#ifdef OF_PLATFORM_DRIVER 1210 of_unregister_platform_driver(&OF_PLATFORM_DRIVER); 1211 error_of_platform: 1212#endif 1213#ifdef PLATFORM_DRIVER 1214 platform_driver_unregister(&PLATFORM_DRIVER); 1215 error_platform: 1216#endif 1217#ifdef OMAP1_PLATFORM_DRIVER 1218 platform_driver_unregister(&OMAP1_PLATFORM_DRIVER); 1219 error_omap1_platform: 1220#endif 1221#ifdef OMAP3_PLATFORM_DRIVER 1222 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER); 1223 error_omap3_platform: 1224#endif 1225#ifdef PS3_SYSTEM_BUS_DRIVER 1226 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1227 error_ps3: 1228#endif 1229#ifdef DEBUG 1230 debugfs_remove(ohci_debug_root); 1231 ohci_debug_root = NULL; 1232 error_debug: 1233#endif 1234 1235 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); 1236 return retval; 1237} 1238module_init(ohci_hcd_mod_init); 1239 1240static void __exit ohci_hcd_mod_exit(void) 1241{ 1242#ifdef TMIO_OHCI_DRIVER 1243 platform_driver_unregister(&TMIO_OHCI_DRIVER); 1244#endif 1245#ifdef SM501_OHCI_DRIVER 1246 platform_driver_unregister(&SM501_OHCI_DRIVER); 1247#endif 1248#ifdef SSB_OHCI_DRIVER 1249 ssb_driver_unregister(&SSB_OHCI_DRIVER); 1250#endif 1251#ifdef PCI_DRIVER 1252 pci_unregister_driver(&PCI_DRIVER); 1253#endif 1254#ifdef SA1111_DRIVER 1255 sa1111_driver_unregister(&SA1111_DRIVER); 1256#endif 1257#ifdef OF_PLATFORM_DRIVER 1258 of_unregister_platform_driver(&OF_PLATFORM_DRIVER); 1259#endif 1260#ifdef PLATFORM_DRIVER 1261 platform_driver_unregister(&PLATFORM_DRIVER); 1262#endif 1263#ifdef PS3_SYSTEM_BUS_DRIVER 1264 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1265#endif 1266#ifdef DEBUG 1267 debugfs_remove(ohci_debug_root); 1268#endif 1269 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); 1270} 1271module_exit(ohci_hcd_mod_exit); 1272