1/* 2 * Macros and prototypes for i.MX21 3 * 4 * Copyright (C) 2006 Loping Dog Embedded Systems 5 * Copyright (C) 2009 Martin Fuzzey 6 * Originally written by Jay Monkman <jtm@lopingdog.com> 7 * Ported to 2.6.30, debugged and enhanced by Martin Fuzzey 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software Foundation, 21 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24#ifndef __LINUX_IMX21_HCD_H__ 25#define __LINUX_IMX21_HCD_H__ 26 27#include <mach/mx21-usbhost.h> 28 29#define NUM_ISO_ETDS 2 30#define USB_NUM_ETD 32 31#define DMEM_SIZE 4096 32 33/* Register definitions */ 34#define USBOTG_HWMODE 0x00 35#define USBOTG_HWMODE_ANASDBEN (1 << 14) 36#define USBOTG_HWMODE_OTGXCVR_SHIFT 6 37#define USBOTG_HWMODE_OTGXCVR_MASK (3 << 6) 38#define USBOTG_HWMODE_OTGXCVR_TD_RD (0 << 6) 39#define USBOTG_HWMODE_OTGXCVR_TS_RD (2 << 6) 40#define USBOTG_HWMODE_OTGXCVR_TD_RS (1 << 6) 41#define USBOTG_HWMODE_OTGXCVR_TS_RS (3 << 6) 42#define USBOTG_HWMODE_HOSTXCVR_SHIFT 4 43#define USBOTG_HWMODE_HOSTXCVR_MASK (3 << 4) 44#define USBOTG_HWMODE_HOSTXCVR_TD_RD (0 << 4) 45#define USBOTG_HWMODE_HOSTXCVR_TS_RD (2 << 4) 46#define USBOTG_HWMODE_HOSTXCVR_TD_RS (1 << 4) 47#define USBOTG_HWMODE_HOSTXCVR_TS_RS (3 << 4) 48#define USBOTG_HWMODE_CRECFG_MASK (3 << 0) 49#define USBOTG_HWMODE_CRECFG_HOST (1 << 0) 50#define USBOTG_HWMODE_CRECFG_FUNC (2 << 0) 51#define USBOTG_HWMODE_CRECFG_HNP (3 << 0) 52 53#define USBOTG_CINT_STAT 0x04 54#define USBOTG_CINT_STEN 0x08 55#define USBOTG_ASHNPINT (1 << 5) 56#define USBOTG_ASFCINT (1 << 4) 57#define USBOTG_ASHCINT (1 << 3) 58#define USBOTG_SHNPINT (1 << 2) 59#define USBOTG_FCINT (1 << 1) 60#define USBOTG_HCINT (1 << 0) 61 62#define USBOTG_CLK_CTRL 0x0c 63#define USBOTG_CLK_CTRL_FUNC (1 << 2) 64#define USBOTG_CLK_CTRL_HST (1 << 1) 65#define USBOTG_CLK_CTRL_MAIN (1 << 0) 66 67#define USBOTG_RST_CTRL 0x10 68#define USBOTG_RST_RSTI2C (1 << 15) 69#define USBOTG_RST_RSTCTRL (1 << 5) 70#define USBOTG_RST_RSTFC (1 << 4) 71#define USBOTG_RST_RSTFSKE (1 << 3) 72#define USBOTG_RST_RSTRH (1 << 2) 73#define USBOTG_RST_RSTHSIE (1 << 1) 74#define USBOTG_RST_RSTHC (1 << 0) 75 76#define USBOTG_FRM_INTVL 0x14 77#define USBOTG_FRM_REMAIN 0x18 78#define USBOTG_HNP_CSR 0x1c 79#define USBOTG_HNP_ISR 0x2c 80#define USBOTG_HNP_IEN 0x30 81 82#define USBOTG_I2C_TXCVR_REG(x) (0x100 + (x)) 83#define USBOTG_I2C_XCVR_DEVAD 0x118 84#define USBOTG_I2C_SEQ_OP_REG 0x119 85#define USBOTG_I2C_SEQ_RD_STARTAD 0x11a 86#define USBOTG_I2C_OP_CTRL_REG 0x11b 87#define USBOTG_I2C_SCLK_TO_SCK_HPER 0x11e 88#define USBOTG_I2C_MASTER_INT_REG 0x11f 89 90#define USBH_HOST_CTRL 0x80 91#define USBH_HOST_CTRL_HCRESET (1 << 31) 92#define USBH_HOST_CTRL_SCHDOVR(x) ((x) << 16) 93#define USBH_HOST_CTRL_RMTWUEN (1 << 4) 94#define USBH_HOST_CTRL_HCUSBSTE_RESET (0 << 2) 95#define USBH_HOST_CTRL_HCUSBSTE_RESUME (1 << 2) 96#define USBH_HOST_CTRL_HCUSBSTE_OPERATIONAL (2 << 2) 97#define USBH_HOST_CTRL_HCUSBSTE_SUSPEND (3 << 2) 98#define USBH_HOST_CTRL_CTLBLKSR_1 (0 << 0) 99#define USBH_HOST_CTRL_CTLBLKSR_2 (1 << 0) 100#define USBH_HOST_CTRL_CTLBLKSR_3 (2 << 0) 101#define USBH_HOST_CTRL_CTLBLKSR_4 (3 << 0) 102 103#define USBH_SYSISR 0x88 104#define USBH_SYSISR_PSCINT (1 << 6) 105#define USBH_SYSISR_FMOFINT (1 << 5) 106#define USBH_SYSISR_HERRINT (1 << 4) 107#define USBH_SYSISR_RESDETINT (1 << 3) 108#define USBH_SYSISR_SOFINT (1 << 2) 109#define USBH_SYSISR_DONEINT (1 << 1) 110#define USBH_SYSISR_SORINT (1 << 0) 111 112#define USBH_SYSIEN 0x8c 113#define USBH_SYSIEN_PSCINT (1 << 6) 114#define USBH_SYSIEN_FMOFINT (1 << 5) 115#define USBH_SYSIEN_HERRINT (1 << 4) 116#define USBH_SYSIEN_RESDETINT (1 << 3) 117#define USBH_SYSIEN_SOFINT (1 << 2) 118#define USBH_SYSIEN_DONEINT (1 << 1) 119#define USBH_SYSIEN_SORINT (1 << 0) 120 121#define USBH_XBUFSTAT 0x98 122#define USBH_YBUFSTAT 0x9c 123#define USBH_XYINTEN 0xa0 124#define USBH_XFILLSTAT 0xa8 125#define USBH_YFILLSTAT 0xac 126#define USBH_ETDENSET 0xc0 127#define USBH_ETDENCLR 0xc4 128#define USBH_IMMEDINT 0xcc 129#define USBH_ETDDONESTAT 0xd0 130#define USBH_ETDDONEEN 0xd4 131#define USBH_FRMNUB 0xe0 132#define USBH_LSTHRESH 0xe4 133 134#define USBH_ROOTHUBA 0xe8 135#define USBH_ROOTHUBA_PWRTOGOOD_MASK (0xff) 136#define USBH_ROOTHUBA_PWRTOGOOD_SHIFT (24) 137#define USBH_ROOTHUBA_NOOVRCURP (1 << 12) 138#define USBH_ROOTHUBA_OVRCURPM (1 << 11) 139#define USBH_ROOTHUBA_DEVTYPE (1 << 10) 140#define USBH_ROOTHUBA_PWRSWTMD (1 << 9) 141#define USBH_ROOTHUBA_NOPWRSWT (1 << 8) 142#define USBH_ROOTHUBA_NDNSTMPRT_MASK (0xff) 143 144#define USBH_ROOTHUBB 0xec 145#define USBH_ROOTHUBB_PRTPWRCM(x) (1 << ((x) + 16)) 146#define USBH_ROOTHUBB_DEVREMOVE(x) (1 << (x)) 147 148#define USBH_ROOTSTAT 0xf0 149#define USBH_ROOTSTAT_CLRRMTWUE (1 << 31) 150#define USBH_ROOTSTAT_OVRCURCHG (1 << 17) 151#define USBH_ROOTSTAT_DEVCONWUE (1 << 15) 152#define USBH_ROOTSTAT_OVRCURI (1 << 1) 153#define USBH_ROOTSTAT_LOCPWRS (1 << 0) 154 155#define USBH_PORTSTAT(x) (0xf4 + ((x) * 4)) 156#define USBH_PORTSTAT_PRTRSTSC (1 << 20) 157#define USBH_PORTSTAT_OVRCURIC (1 << 19) 158#define USBH_PORTSTAT_PRTSTATSC (1 << 18) 159#define USBH_PORTSTAT_PRTENBLSC (1 << 17) 160#define USBH_PORTSTAT_CONNECTSC (1 << 16) 161#define USBH_PORTSTAT_LSDEVCON (1 << 9) 162#define USBH_PORTSTAT_PRTPWRST (1 << 8) 163#define USBH_PORTSTAT_PRTRSTST (1 << 4) 164#define USBH_PORTSTAT_PRTOVRCURI (1 << 3) 165#define USBH_PORTSTAT_PRTSUSPST (1 << 2) 166#define USBH_PORTSTAT_PRTENABST (1 << 1) 167#define USBH_PORTSTAT_CURCONST (1 << 0) 168 169#define USB_DMAREV 0x800 170#define USB_DMAINTSTAT 0x804 171#define USB_DMAINTSTAT_EPERR (1 << 1) 172#define USB_DMAINTSTAT_ETDERR (1 << 0) 173 174#define USB_DMAINTEN 0x808 175#define USB_DMAINTEN_EPERRINTEN (1 << 1) 176#define USB_DMAINTEN_ETDERRINTEN (1 << 0) 177 178#define USB_ETDDMAERSTAT 0x80c 179#define USB_EPDMAERSTAT 0x810 180#define USB_ETDDMAEN 0x820 181#define USB_EPDMAEN 0x824 182#define USB_ETDDMAXTEN 0x828 183#define USB_EPDMAXTEN 0x82c 184#define USB_ETDDMAENXYT 0x830 185#define USB_EPDMAENXYT 0x834 186#define USB_ETDDMABST4EN 0x838 187#define USB_EPDMABST4EN 0x83c 188 189#define USB_MISCCONTROL 0x840 190#define USB_MISCCONTROL_ISOPREVFRM (1 << 3) 191#define USB_MISCCONTROL_SKPRTRY (1 << 2) 192#define USB_MISCCONTROL_ARBMODE (1 << 1) 193#define USB_MISCCONTROL_FILTCC (1 << 0) 194 195#define USB_ETDDMACHANLCLR 0x848 196#define USB_EPDMACHANLCLR 0x84c 197#define USB_ETDSMSA(x) (0x900 + ((x) * 4)) 198#define USB_EPSMSA(x) (0x980 + ((x) * 4)) 199#define USB_ETDDMABUFPTR(x) (0xa00 + ((x) * 4)) 200#define USB_EPDMABUFPTR(x) (0xa80 + ((x) * 4)) 201 202#define USB_ETD_DWORD(x, w) (0x200 + ((x) * 16) + ((w) * 4)) 203#define DW0_ADDRESS 0 204#define DW0_ENDPNT 7 205#define DW0_DIRECT 11 206#define DW0_SPEED 13 207#define DW0_FORMAT 14 208#define DW0_MAXPKTSIZ 16 209#define DW0_HALTED 27 210#define DW0_TOGCRY 28 211#define DW0_SNDNAK 30 212 213#define DW1_XBUFSRTAD 0 214#define DW1_YBUFSRTAD 16 215 216#define DW2_RTRYDELAY 0 217#define DW2_POLINTERV 0 218#define DW2_STARTFRM 0 219#define DW2_RELPOLPOS 8 220#define DW2_DIRPID 16 221#define DW2_BUFROUND 18 222#define DW2_DELAYINT 19 223#define DW2_DATATOG 22 224#define DW2_ERRORCNT 24 225#define DW2_COMPCODE 28 226 227#define DW3_TOTBYECNT 0 228#define DW3_PKTLEN0 0 229#define DW3_COMPCODE0 12 230#define DW3_PKTLEN1 16 231#define DW3_BUFSIZE 21 232#define DW3_COMPCODE1 28 233 234#define USBCTRL 0x600 235#define USBCTRL_I2C_WU_INT_STAT (1 << 27) 236#define USBCTRL_OTG_WU_INT_STAT (1 << 26) 237#define USBCTRL_HOST_WU_INT_STAT (1 << 25) 238#define USBCTRL_FNT_WU_INT_STAT (1 << 24) 239#define USBCTRL_I2C_WU_INT_EN (1 << 19) 240#define USBCTRL_OTG_WU_INT_EN (1 << 18) 241#define USBCTRL_HOST_WU_INT_EN (1 << 17) 242#define USBCTRL_FNT_WU_INT_EN (1 << 16) 243#define USBCTRL_OTC_RCV_RXDP (1 << 13) 244#define USBCTRL_HOST1_BYP_TLL (1 << 12) 245#define USBCTRL_OTG_BYP_VAL(x) ((x) << 10) 246#define USBCTRL_HOST1_BYP_VAL(x) ((x) << 8) 247#define USBCTRL_OTG_PWR_MASK (1 << 6) 248#define USBCTRL_HOST1_PWR_MASK (1 << 5) 249#define USBCTRL_HOST2_PWR_MASK (1 << 4) 250#define USBCTRL_USB_BYP (1 << 2) 251#define USBCTRL_HOST1_TXEN_OE (1 << 1) 252 253 254/* Values in TD blocks */ 255#define TD_DIR_SETUP 0 256#define TD_DIR_OUT 1 257#define TD_DIR_IN 2 258#define TD_FORMAT_CONTROL 0 259#define TD_FORMAT_ISO 1 260#define TD_FORMAT_BULK 2 261#define TD_FORMAT_INT 3 262#define TD_TOGGLE_CARRY 0 263#define TD_TOGGLE_DATA0 2 264#define TD_TOGGLE_DATA1 3 265 266/* control transfer states */ 267#define US_CTRL_SETUP 2 268#define US_CTRL_DATA 1 269#define US_CTRL_ACK 0 270 271/* bulk transfer main state and 0-length packet */ 272#define US_BULK 1 273#define US_BULK0 0 274 275/*ETD format description*/ 276#define IMX_FMT_CTRL 0x0 277#define IMX_FMT_ISO 0x1 278#define IMX_FMT_BULK 0x2 279#define IMX_FMT_INT 0x3 280 281static char fmt_urb_to_etd[4] = { 282/*PIPE_ISOCHRONOUS*/ IMX_FMT_ISO, 283/*PIPE_INTERRUPT*/ IMX_FMT_INT, 284/*PIPE_CONTROL*/ IMX_FMT_CTRL, 285/*PIPE_BULK*/ IMX_FMT_BULK 286}; 287 288/* condition (error) CC codes and mapping (OHCI like) */ 289 290#define TD_CC_NOERROR 0x00 291#define TD_CC_CRC 0x01 292#define TD_CC_BITSTUFFING 0x02 293#define TD_CC_DATATOGGLEM 0x03 294#define TD_CC_STALL 0x04 295#define TD_DEVNOTRESP 0x05 296#define TD_PIDCHECKFAIL 0x06 297/*#define TD_UNEXPECTEDPID 0x07 - reserved, not active on MX2*/ 298#define TD_DATAOVERRUN 0x08 299#define TD_DATAUNDERRUN 0x09 300#define TD_BUFFEROVERRUN 0x0C 301#define TD_BUFFERUNDERRUN 0x0D 302#define TD_SCHEDULEOVERRUN 0x0E 303#define TD_NOTACCESSED 0x0F 304 305static const int cc_to_error[16] = { 306 /* No Error */ 0, 307 /* CRC Error */ -EILSEQ, 308 /* Bit Stuff */ -EPROTO, 309 /* Data Togg */ -EILSEQ, 310 /* Stall */ -EPIPE, 311 /* DevNotResp */ -ETIMEDOUT, 312 /* PIDCheck */ -EPROTO, 313 /* UnExpPID */ -EPROTO, 314 /* DataOver */ -EOVERFLOW, 315 /* DataUnder */ -EREMOTEIO, 316 /* (for hw) */ -EIO, 317 /* (for hw) */ -EIO, 318 /* BufferOver */ -ECOMM, 319 /* BuffUnder */ -ENOSR, 320 /* (for HCD) */ -ENOSPC, 321 /* (for HCD) */ -EALREADY 322}; 323 324/* HCD data associated with a usb core URB */ 325struct urb_priv { 326 struct urb *urb; 327 struct usb_host_endpoint *ep; 328 int active; 329 int state; 330 struct td *isoc_td; 331 int isoc_remaining; 332 int isoc_status; 333}; 334 335/* HCD data associated with a usb core endpoint */ 336struct ep_priv { 337 struct usb_host_endpoint *ep; 338 struct list_head td_list; 339 struct list_head queue; 340 int etd[NUM_ISO_ETDS]; 341 int waiting_etd; 342}; 343 344/* isoc packet */ 345struct td { 346 struct list_head list; 347 struct urb *urb; 348 struct usb_host_endpoint *ep; 349 dma_addr_t data; 350 unsigned long buf_addr; 351 int len; 352 int frame; 353 int isoc_index; 354}; 355 356/* HCD data associated with a hardware ETD */ 357struct etd_priv { 358 struct usb_host_endpoint *ep; 359 struct urb *urb; 360 struct td *td; 361 struct list_head queue; 362 dma_addr_t dma_handle; 363 int alloc; 364 int len; 365 int dmem_size; 366 int dmem_offset; 367 int active_count; 368#ifdef DEBUG 369 int activated_frame; 370 int disactivated_frame; 371 int last_int_frame; 372 int last_req_frame; 373 u32 submitted_dwords[4]; 374#endif 375}; 376 377/* Hardware data memory info */ 378struct imx21_dmem_area { 379 struct usb_host_endpoint *ep; 380 unsigned int offset; 381 unsigned int size; 382 struct list_head list; 383}; 384 385#ifdef DEBUG 386struct debug_usage_stats { 387 unsigned int value; 388 unsigned int maximum; 389}; 390 391struct debug_stats { 392 unsigned long submitted; 393 unsigned long completed_ok; 394 unsigned long completed_failed; 395 unsigned long unlinked; 396 unsigned long queue_etd; 397 unsigned long queue_dmem; 398}; 399 400struct debug_isoc_trace { 401 int schedule_frame; 402 int submit_frame; 403 int request_len; 404 int done_frame; 405 int done_len; 406 int cc; 407 struct td *td; 408}; 409#endif 410 411/* HCD data structure */ 412struct imx21 { 413 spinlock_t lock; 414 struct device *dev; 415 struct mx21_usbh_platform_data *pdata; 416 struct list_head dmem_list; 417 struct list_head queue_for_etd; /* eps queued due to etd shortage */ 418 struct list_head queue_for_dmem; /* etds queued due to dmem shortage */ 419 struct etd_priv etd[USB_NUM_ETD]; 420 struct clk *clk; 421 void __iomem *regs; 422#ifdef DEBUG 423 struct dentry *debug_root; 424 struct debug_stats nonisoc_stats; 425 struct debug_stats isoc_stats; 426 struct debug_usage_stats etd_usage; 427 struct debug_usage_stats dmem_usage; 428 struct debug_isoc_trace isoc_trace[20]; 429 struct debug_isoc_trace isoc_trace_failed[20]; 430 unsigned long debug_unblocks; 431 int isoc_trace_index; 432 int isoc_trace_index_failed; 433#endif 434}; 435 436#endif 437