1/* 2 * Copyright (c) 2000-2004 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19#include <linux/module.h> 20#include <linux/pci.h> 21#include <linux/dmapool.h> 22#include <linux/kernel.h> 23#include <linux/delay.h> 24#include <linux/ioport.h> 25#include <linux/sched.h> 26#include <linux/vmalloc.h> 27#include <linux/errno.h> 28#include <linux/init.h> 29#include <linux/timer.h> 30#include <linux/ktime.h> 31#include <linux/list.h> 32#include <linux/interrupt.h> 33#include <linux/usb.h> 34#include <linux/usb/hcd.h> 35#include <linux/moduleparam.h> 36#include <linux/dma-mapping.h> 37#include <linux/debugfs.h> 38#include <linux/slab.h> 39#include <linux/uaccess.h> 40 41#include <asm/byteorder.h> 42#include <asm/io.h> 43#include <asm/irq.h> 44#include <asm/system.h> 45#include <asm/unaligned.h> 46 47/*-------------------------------------------------------------------------*/ 48 49/* 50 * EHCI hc_driver implementation ... experimental, incomplete. 51 * Based on the final 1.0 register interface specification. 52 * 53 * USB 2.0 shows up in upcoming www.pcmcia.org technology. 54 * First was PCMCIA, like ISA; then CardBus, which is PCI. 55 * Next comes "CardBay", using USB 2.0 signals. 56 * 57 * Contains additional contributions by Brad Hards, Rory Bolt, and others. 58 * Special thanks to Intel and VIA for providing host controllers to 59 * test this driver on, and Cypress (including In-System Design) for 60 * providing early devices for those host controllers to talk to! 61 */ 62 63#define DRIVER_AUTHOR "David Brownell" 64#define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" 65 66static const char hcd_name [] = "ehci_hcd"; 67 68 69#undef VERBOSE_DEBUG 70#undef EHCI_URB_TRACE 71 72#ifdef DEBUG 73#define EHCI_STATS 74#endif 75 76/* magic numbers that can affect system performance */ 77#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ 78#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ 79#define EHCI_TUNE_RL_TT 0 80#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ 81#define EHCI_TUNE_MULT_TT 1 82/* 83 * Some drivers think it's safe to schedule isochronous transfers more than 84 * 256 ms into the future (partly as a result of an old bug in the scheduling 85 * code). In an attempt to avoid trouble, we will use a minimum scheduling 86 * length of 512 frames instead of 256. 87 */ 88#define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */ 89 90#define EHCI_IAA_MSECS 10 /* arbitrary */ 91#define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ 92#define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ 93#define EHCI_SHRINK_FRAMES 5 /* async qh unlink delay */ 94 95/* Initial IRQ latency: faster than hw default */ 96static int log2_irq_thresh = 0; // 0 to 6 97module_param (log2_irq_thresh, int, S_IRUGO); 98MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); 99 100/* initial park setting: slower than hw default */ 101static unsigned park = 0; 102module_param (park, uint, S_IRUGO); 103MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); 104 105/* for flakey hardware, ignore overcurrent indicators */ 106static int ignore_oc = 0; 107module_param (ignore_oc, bool, S_IRUGO); 108MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications"); 109 110/* for link power management(LPM) feature */ 111static unsigned int hird; 112module_param(hird, int, S_IRUGO); 113MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us\n"); 114 115#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) 116 117/* for ASPM quirk of ISOC on AMD SB800 */ 118static struct pci_dev *amd_nb_dev; 119 120/*-------------------------------------------------------------------------*/ 121 122#include "ehci.h" 123#include "ehci-dbg.c" 124 125/*-------------------------------------------------------------------------*/ 126 127static void 128timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action) 129{ 130 /* Don't override timeouts which shrink or (later) disable 131 * the async ring; just the I/O watchdog. Note that if a 132 * SHRINK were pending, OFF would never be requested. 133 */ 134 if (timer_pending(&ehci->watchdog) 135 && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF)) 136 & ehci->actions)) 137 return; 138 139 if (!test_and_set_bit(action, &ehci->actions)) { 140 unsigned long t; 141 142 switch (action) { 143 case TIMER_IO_WATCHDOG: 144 if (!ehci->need_io_watchdog) 145 return; 146 t = EHCI_IO_JIFFIES; 147 break; 148 case TIMER_ASYNC_OFF: 149 t = EHCI_ASYNC_JIFFIES; 150 break; 151 /* case TIMER_ASYNC_SHRINK: */ 152 default: 153 /* add a jiffie since we synch against the 154 * 8 KHz uframe counter. 155 */ 156 t = DIV_ROUND_UP(EHCI_SHRINK_FRAMES * HZ, 1000) + 1; 157 break; 158 } 159 mod_timer(&ehci->watchdog, t + jiffies); 160 } 161} 162 163/*-------------------------------------------------------------------------*/ 164 165/* 166 * handshake - spin reading hc until handshake completes or fails 167 * @ptr: address of hc register to be read 168 * @mask: bits to look at in result of read 169 * @done: value of those bits when handshake succeeds 170 * @usec: timeout in microseconds 171 * 172 * Returns negative errno, or zero on success 173 * 174 * Success happens when the "mask" bits have the specified value (hardware 175 * handshake done). There are two failure modes: "usec" have passed (major 176 * hardware flakeout), or the register reads as all-ones (hardware removed). 177 * 178 * That last failure should_only happen in cases like physical cardbus eject 179 * before driver shutdown. But it also seems to be caused by bugs in cardbus 180 * bridge shutdown: shutting down the bridge before the devices using it. 181 */ 182static int handshake (struct ehci_hcd *ehci, void __iomem *ptr, 183 u32 mask, u32 done, int usec) 184{ 185 u32 result; 186 187 do { 188 result = ehci_readl(ehci, ptr); 189 if (result == ~(u32)0) /* card removed */ 190 return -ENODEV; 191 result &= mask; 192 if (result == done) 193 return 0; 194 udelay (1); 195 usec--; 196 } while (usec > 0); 197 return -ETIMEDOUT; 198} 199 200/* force HC to halt state from unknown (EHCI spec section 2.3) */ 201static int ehci_halt (struct ehci_hcd *ehci) 202{ 203 u32 temp = ehci_readl(ehci, &ehci->regs->status); 204 205 /* disable any irqs left enabled by previous code */ 206 ehci_writel(ehci, 0, &ehci->regs->intr_enable); 207 208 if ((temp & STS_HALT) != 0) 209 return 0; 210 211 temp = ehci_readl(ehci, &ehci->regs->command); 212 temp &= ~CMD_RUN; 213 ehci_writel(ehci, temp, &ehci->regs->command); 214 return handshake (ehci, &ehci->regs->status, 215 STS_HALT, STS_HALT, 16 * 125); 216} 217 218static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr, 219 u32 mask, u32 done, int usec) 220{ 221 int error; 222 223 error = handshake(ehci, ptr, mask, done, usec); 224 if (error) { 225 ehci_halt(ehci); 226 ehci_to_hcd(ehci)->state = HC_STATE_HALT; 227 ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n", 228 ptr, mask, done, error); 229 } 230 231 return error; 232} 233 234/* put TDI/ARC silicon into EHCI mode */ 235static void tdi_reset (struct ehci_hcd *ehci) 236{ 237 u32 __iomem *reg_ptr; 238 u32 tmp; 239 240 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); 241 tmp = ehci_readl(ehci, reg_ptr); 242 tmp |= USBMODE_CM_HC; 243 /* The default byte access to MMR space is LE after 244 * controller reset. Set the required endian mode 245 * for transfer buffers to match the host microprocessor 246 */ 247#if defined(CONFIG_MIPS) 248#if defined(CONFIG_CPU_BIG_ENDIAN) 249 tmp |= USBMODE_BE; 250#endif 251#if defined(CONFIG_CPU_LITTLE_ENDIAN) 252 tmp &= ~USBMODE_BE; 253#endif 254#else 255 if (ehci_big_endian_mmio(ehci)) 256 tmp |= USBMODE_BE; 257#endif 258 ehci_writel(ehci, tmp, reg_ptr); 259} 260 261/* reset a non-running (STS_HALT == 1) controller */ 262static int ehci_reset (struct ehci_hcd *ehci) 263{ 264 int retval; 265 u32 command = ehci_readl(ehci, &ehci->regs->command); 266 267 /* If the EHCI debug controller is active, special care must be 268 * taken before and after a host controller reset */ 269 if (ehci->debug && !dbgp_reset_prep()) 270 ehci->debug = NULL; 271 272 command |= CMD_RESET; 273 dbg_cmd (ehci, "reset", command); 274 ehci_writel(ehci, command, &ehci->regs->command); 275 ehci_to_hcd(ehci)->state = HC_STATE_HALT; 276 ehci->next_statechange = jiffies; 277 retval = handshake (ehci, &ehci->regs->command, 278 CMD_RESET, 0, 250 * 1000); 279 280 if (ehci->has_hostpc) { 281 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS, 282 (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX)); 283 ehci_writel(ehci, TXFIFO_DEFAULT, 284 (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING)); 285 } 286 if (retval) 287 return retval; 288 289 if (ehci_is_TDI(ehci)) 290 tdi_reset (ehci); 291 292 if (ehci->debug) 293 dbgp_external_startup(); 294 295 return retval; 296} 297 298/* idle the controller (from running) */ 299static void ehci_quiesce (struct ehci_hcd *ehci) 300{ 301 u32 temp; 302 303#ifdef DEBUG 304 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) 305 BUG (); 306#endif 307 308 /* wait for any schedule enables/disables to take effect */ 309 temp = ehci_readl(ehci, &ehci->regs->command) << 10; 310 temp &= STS_ASS | STS_PSS; 311 if (handshake_on_error_set_halt(ehci, &ehci->regs->status, 312 STS_ASS | STS_PSS, temp, 16 * 125)) 313 return; 314 315 /* then disable anything that's still active */ 316 temp = ehci_readl(ehci, &ehci->regs->command); 317 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); 318 ehci_writel(ehci, temp, &ehci->regs->command); 319 320 /* hardware can take 16 microframes to turn off ... */ 321 handshake_on_error_set_halt(ehci, &ehci->regs->status, 322 STS_ASS | STS_PSS, 0, 16 * 125); 323} 324 325/*-------------------------------------------------------------------------*/ 326 327static void end_unlink_async(struct ehci_hcd *ehci); 328static void ehci_work(struct ehci_hcd *ehci); 329 330#include "ehci-hub.c" 331#include "ehci-lpm.c" 332#include "ehci-mem.c" 333#include "ehci-q.c" 334#include "ehci-sched.c" 335 336/*-------------------------------------------------------------------------*/ 337 338static void ehci_iaa_watchdog(unsigned long param) 339{ 340 struct ehci_hcd *ehci = (struct ehci_hcd *) param; 341 unsigned long flags; 342 343 spin_lock_irqsave (&ehci->lock, flags); 344 345 /* Lost IAA irqs wedge things badly; seen first with a vt8235. 346 * So we need this watchdog, but must protect it against both 347 * (a) SMP races against real IAA firing and retriggering, and 348 * (b) clean HC shutdown, when IAA watchdog was pending. 349 */ 350 if (ehci->reclaim 351 && !timer_pending(&ehci->iaa_watchdog) 352 && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) { 353 u32 cmd, status; 354 355 /* If we get here, IAA is *REALLY* late. It's barely 356 * conceivable that the system is so busy that CMD_IAAD 357 * is still legitimately set, so let's be sure it's 358 * clear before we read STS_IAA. (The HC should clear 359 * CMD_IAAD when it sets STS_IAA.) 360 */ 361 cmd = ehci_readl(ehci, &ehci->regs->command); 362 if (cmd & CMD_IAAD) 363 ehci_writel(ehci, cmd & ~CMD_IAAD, 364 &ehci->regs->command); 365 366 /* If IAA is set here it either legitimately triggered 367 * before we cleared IAAD above (but _way_ late, so we'll 368 * still count it as lost) ... or a silicon erratum: 369 * - VIA seems to set IAA without triggering the IRQ; 370 * - IAAD potentially cleared without setting IAA. 371 */ 372 status = ehci_readl(ehci, &ehci->regs->status); 373 if ((status & STS_IAA) || !(cmd & CMD_IAAD)) { 374 COUNT (ehci->stats.lost_iaa); 375 ehci_writel(ehci, STS_IAA, &ehci->regs->status); 376 } 377 378 ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n", 379 status, cmd); 380 end_unlink_async(ehci); 381 } 382 383 spin_unlock_irqrestore(&ehci->lock, flags); 384} 385 386static void ehci_watchdog(unsigned long param) 387{ 388 struct ehci_hcd *ehci = (struct ehci_hcd *) param; 389 unsigned long flags; 390 391 spin_lock_irqsave(&ehci->lock, flags); 392 393 /* stop async processing after it's idled a bit */ 394 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions)) 395 start_unlink_async (ehci, ehci->async); 396 397 /* ehci could run by timer, without IRQs ... */ 398 ehci_work (ehci); 399 400 spin_unlock_irqrestore (&ehci->lock, flags); 401} 402 403/* On some systems, leaving remote wakeup enabled prevents system shutdown. 404 * The firmware seems to think that powering off is a wakeup event! 405 * This routine turns off remote wakeup and everything else, on all ports. 406 */ 407static void ehci_turn_off_all_ports(struct ehci_hcd *ehci) 408{ 409 int port = HCS_N_PORTS(ehci->hcs_params); 410 411 while (port--) 412 ehci_writel(ehci, PORT_RWC_BITS, 413 &ehci->regs->port_status[port]); 414} 415 416/* 417 * Halt HC, turn off all ports, and let the BIOS use the companion controllers. 418 * Should be called with ehci->lock held. 419 */ 420static void ehci_silence_controller(struct ehci_hcd *ehci) 421{ 422 ehci_halt(ehci); 423 ehci_turn_off_all_ports(ehci); 424 425 /* make BIOS/etc use companion controller during reboot */ 426 ehci_writel(ehci, 0, &ehci->regs->configured_flag); 427 428 /* unblock posted writes */ 429 ehci_readl(ehci, &ehci->regs->configured_flag); 430} 431 432/* ehci_shutdown kick in for silicon on any bus (not just pci, etc). 433 * This forcibly disables dma and IRQs, helping kexec and other cases 434 * where the next system software may expect clean state. 435 */ 436static void ehci_shutdown(struct usb_hcd *hcd) 437{ 438 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 439 440 del_timer_sync(&ehci->watchdog); 441 del_timer_sync(&ehci->iaa_watchdog); 442 443 spin_lock_irq(&ehci->lock); 444 ehci_silence_controller(ehci); 445 spin_unlock_irq(&ehci->lock); 446} 447 448static void ehci_port_power (struct ehci_hcd *ehci, int is_on) 449{ 450 unsigned port; 451 452 if (!HCS_PPC (ehci->hcs_params)) 453 return; 454 455 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); 456 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) 457 (void) ehci_hub_control(ehci_to_hcd(ehci), 458 is_on ? SetPortFeature : ClearPortFeature, 459 USB_PORT_FEAT_POWER, 460 port--, NULL, 0); 461 /* Flush those writes */ 462 ehci_readl(ehci, &ehci->regs->command); 463 msleep(20); 464} 465 466/*-------------------------------------------------------------------------*/ 467 468/* 469 * ehci_work is called from some interrupts, timers, and so on. 470 * it calls driver completion functions, after dropping ehci->lock. 471 */ 472static void ehci_work (struct ehci_hcd *ehci) 473{ 474 timer_action_done (ehci, TIMER_IO_WATCHDOG); 475 476 /* another CPU may drop ehci->lock during a schedule scan while 477 * it reports urb completions. this flag guards against bogus 478 * attempts at re-entrant schedule scanning. 479 */ 480 if (ehci->scanning) 481 return; 482 ehci->scanning = 1; 483 scan_async (ehci); 484 if (ehci->next_uframe != -1) 485 scan_periodic (ehci); 486 ehci->scanning = 0; 487 488 /* the IO watchdog guards against hardware or driver bugs that 489 * misplace IRQs, and should let us run completely without IRQs. 490 * such lossage has been observed on both VT6202 and VT8235. 491 */ 492 if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && 493 (ehci->async->qh_next.ptr != NULL || 494 ehci->periodic_sched != 0)) 495 timer_action (ehci, TIMER_IO_WATCHDOG); 496} 497 498/* 499 * Called when the ehci_hcd module is removed. 500 */ 501static void ehci_stop (struct usb_hcd *hcd) 502{ 503 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 504 505 ehci_dbg (ehci, "stop\n"); 506 507 /* no more interrupts ... */ 508 del_timer_sync (&ehci->watchdog); 509 del_timer_sync(&ehci->iaa_watchdog); 510 511 spin_lock_irq(&ehci->lock); 512 if (HC_IS_RUNNING (hcd->state)) 513 ehci_quiesce (ehci); 514 515 ehci_silence_controller(ehci); 516 ehci_reset (ehci); 517 spin_unlock_irq(&ehci->lock); 518 519 remove_companion_file(ehci); 520 remove_debug_files (ehci); 521 522 /* root hub is shut down separately (first, when possible) */ 523 spin_lock_irq (&ehci->lock); 524 if (ehci->async) 525 ehci_work (ehci); 526 spin_unlock_irq (&ehci->lock); 527 ehci_mem_cleanup (ehci); 528 529 if (amd_nb_dev) { 530 pci_dev_put(amd_nb_dev); 531 amd_nb_dev = NULL; 532 } 533 534#ifdef EHCI_STATS 535 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", 536 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, 537 ehci->stats.lost_iaa); 538 ehci_dbg (ehci, "complete %ld unlink %ld\n", 539 ehci->stats.complete, ehci->stats.unlink); 540#endif 541 542 dbg_status (ehci, "ehci_stop completed", 543 ehci_readl(ehci, &ehci->regs->status)); 544} 545 546/* one-time init, only for memory state */ 547static int ehci_init(struct usb_hcd *hcd) 548{ 549 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 550 u32 temp; 551 int retval; 552 u32 hcc_params; 553 struct ehci_qh_hw *hw; 554 555 spin_lock_init(&ehci->lock); 556 557 /* 558 * keep io watchdog by default, those good HCDs could turn off it later 559 */ 560 ehci->need_io_watchdog = 1; 561 init_timer(&ehci->watchdog); 562 ehci->watchdog.function = ehci_watchdog; 563 ehci->watchdog.data = (unsigned long) ehci; 564 565 init_timer(&ehci->iaa_watchdog); 566 ehci->iaa_watchdog.function = ehci_iaa_watchdog; 567 ehci->iaa_watchdog.data = (unsigned long) ehci; 568 569 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); 570 571 /* 572 * hw default: 1K periodic list heads, one per frame. 573 * periodic_size can shrink by USBCMD update if hcc_params allows. 574 */ 575 ehci->periodic_size = DEFAULT_I_TDPS; 576 INIT_LIST_HEAD(&ehci->cached_itd_list); 577 INIT_LIST_HEAD(&ehci->cached_sitd_list); 578 579 if (HCC_PGM_FRAMELISTLEN(hcc_params)) { 580 /* periodic schedule size can be smaller than default */ 581 switch (EHCI_TUNE_FLS) { 582 case 0: ehci->periodic_size = 1024; break; 583 case 1: ehci->periodic_size = 512; break; 584 case 2: ehci->periodic_size = 256; break; 585 default: BUG(); 586 } 587 } 588 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) 589 return retval; 590 591 /* controllers may cache some of the periodic schedule ... */ 592 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache 593 ehci->i_thresh = 2 + 8; 594 else // N microframes cached 595 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); 596 597 ehci->reclaim = NULL; 598 ehci->next_uframe = -1; 599 ehci->clock_frame = -1; 600 601 /* 602 * dedicate a qh for the async ring head, since we couldn't unlink 603 * a 'real' qh without stopping the async schedule [4.8]. use it 604 * as the 'reclamation list head' too. 605 * its dummy is used in hw_alt_next of many tds, to prevent the qh 606 * from automatically advancing to the next td after short reads. 607 */ 608 ehci->async->qh_next.qh = NULL; 609 hw = ehci->async->hw; 610 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma); 611 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD); 612 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT); 613 hw->hw_qtd_next = EHCI_LIST_END(ehci); 614 ehci->async->qh_state = QH_STATE_LINKED; 615 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma); 616 617 /* clear interrupt enables, set irq latency */ 618 if (log2_irq_thresh < 0 || log2_irq_thresh > 6) 619 log2_irq_thresh = 0; 620 temp = 1 << (16 + log2_irq_thresh); 621 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) { 622 ehci->has_ppcd = 1; 623 ehci_dbg(ehci, "enable per-port change event\n"); 624 temp |= CMD_PPCEE; 625 } 626 if (HCC_CANPARK(hcc_params)) { 627 /* HW default park == 3, on hardware that supports it (like 628 * NVidia and ALI silicon), maximizes throughput on the async 629 * schedule by avoiding QH fetches between transfers. 630 * 631 * With fast usb storage devices and NForce2, "park" seems to 632 * make problems: throughput reduction (!), data errors... 633 */ 634 if (park) { 635 park = min(park, (unsigned) 3); 636 temp |= CMD_PARK; 637 temp |= park << 8; 638 } 639 ehci_dbg(ehci, "park %d\n", park); 640 } 641 if (HCC_PGM_FRAMELISTLEN(hcc_params)) { 642 /* periodic schedule size can be smaller than default */ 643 temp &= ~(3 << 2); 644 temp |= (EHCI_TUNE_FLS << 2); 645 } 646 if (HCC_LPM(hcc_params)) { 647 /* support link power management EHCI 1.1 addendum */ 648 ehci_dbg(ehci, "support lpm\n"); 649 ehci->has_lpm = 1; 650 if (hird > 0xf) { 651 ehci_dbg(ehci, "hird %d invalid, use default 0", 652 hird); 653 hird = 0; 654 } 655 temp |= hird << 24; 656 } 657 ehci->command = temp; 658 659 /* Accept arbitrarily long scatter-gather lists */ 660 if (!(hcd->driver->flags & HCD_LOCAL_MEM)) 661 hcd->self.sg_tablesize = ~0; 662 return 0; 663} 664 665/* start HC running; it's halted, ehci_init() has been run (once) */ 666static int ehci_run (struct usb_hcd *hcd) 667{ 668 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 669 int retval; 670 u32 temp; 671 u32 hcc_params; 672 673 hcd->uses_new_polling = 1; 674 675 /* EHCI spec section 4.1 */ 676 if ((retval = ehci_reset(ehci)) != 0) { 677 ehci_mem_cleanup(ehci); 678 return retval; 679 } 680 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); 681 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); 682 683 /* 684 * hcc_params controls whether ehci->regs->segment must (!!!) 685 * be used; it constrains QH/ITD/SITD and QTD locations. 686 * pci_pool consistent memory always uses segment zero. 687 * streaming mappings for I/O buffers, like pci_map_single(), 688 * can return segments above 4GB, if the device allows. 689 * 690 * NOTE: the dma mask is visible through dma_supported(), so 691 * drivers can pass this info along ... like NETIF_F_HIGHDMA, 692 * Scsi_Host.highmem_io, and so forth. It's readonly to all 693 * host side drivers though. 694 */ 695 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); 696 if (HCC_64BIT_ADDR(hcc_params)) { 697 ehci_writel(ehci, 0, &ehci->regs->segment); 698 } 699 700 701 // Philips, Intel, and maybe others need CMD_RUN before the 702 // root hub will detect new devices (why?); NEC doesn't 703 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); 704 ehci->command |= CMD_RUN; 705 ehci_writel(ehci, ehci->command, &ehci->regs->command); 706 dbg_cmd (ehci, "init", ehci->command); 707 708 /* 709 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices 710 * are explicitly handed to companion controller(s), so no TT is 711 * involved with the root hub. (Except where one is integrated, 712 * and there's no companion controller unless maybe for USB OTG.) 713 * 714 * Turning on the CF flag will transfer ownership of all ports 715 * from the companions to the EHCI controller. If any of the 716 * companions are in the middle of a port reset at the time, it 717 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem 718 * guarantees that no resets are in progress. After we set CF, 719 * a short delay lets the hardware catch up; new resets shouldn't 720 * be started before the port switching actions could complete. 721 */ 722 down_write(&ehci_cf_port_reset_rwsem); 723 hcd->state = HC_STATE_RUNNING; 724 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); 725 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ 726 msleep(5); 727 up_write(&ehci_cf_port_reset_rwsem); 728 ehci->last_periodic_enable = ktime_get_real(); 729 730 temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase)); 731 ehci_info (ehci, 732 "USB %x.%x started, EHCI %x.%02x%s\n", 733 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), 734 temp >> 8, temp & 0xff, 735 ignore_oc ? ", overcurrent ignored" : ""); 736 737 ehci_writel(ehci, INTR_MASK, 738 &ehci->regs->intr_enable); /* Turn On Interrupts */ 739 740 /* GRR this is run-once init(), being done every time the HC starts. 741 * So long as they're part of class devices, we can't do it init() 742 * since the class device isn't created that early. 743 */ 744 create_debug_files(ehci); 745 create_companion_file(ehci); 746 747 return 0; 748} 749 750/*-------------------------------------------------------------------------*/ 751 752static irqreturn_t ehci_irq (struct usb_hcd *hcd) 753{ 754 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 755 u32 status, masked_status, pcd_status = 0, cmd; 756 int bh; 757 758 spin_lock (&ehci->lock); 759 760 status = ehci_readl(ehci, &ehci->regs->status); 761 762 /* e.g. cardbus physical eject */ 763 if (status == ~(u32) 0) { 764 ehci_dbg (ehci, "device removed\n"); 765 goto dead; 766 } 767 768 masked_status = status & INTR_MASK; 769 if (!masked_status) { /* irq sharing? */ 770 spin_unlock(&ehci->lock); 771 return IRQ_NONE; 772 } 773 774 /* clear (just) interrupts */ 775 ehci_writel(ehci, masked_status, &ehci->regs->status); 776 cmd = ehci_readl(ehci, &ehci->regs->command); 777 bh = 0; 778 779#ifdef VERBOSE_DEBUG 780 /* unrequested/ignored: Frame List Rollover */ 781 dbg_status (ehci, "irq", status); 782#endif 783 784 /* INT, ERR, and IAA interrupt rates can be throttled */ 785 786 /* normal [4.15.1.2] or error [4.15.1.1] completion */ 787 if (likely ((status & (STS_INT|STS_ERR)) != 0)) { 788 if (likely ((status & STS_ERR) == 0)) 789 COUNT (ehci->stats.normal); 790 else 791 COUNT (ehci->stats.error); 792 bh = 1; 793 } 794 795 /* complete the unlinking of some qh [4.15.2.3] */ 796 if (status & STS_IAA) { 797 /* guard against (alleged) silicon errata */ 798 if (cmd & CMD_IAAD) { 799 ehci_writel(ehci, cmd & ~CMD_IAAD, 800 &ehci->regs->command); 801 ehci_dbg(ehci, "IAA with IAAD still set?\n"); 802 } 803 if (ehci->reclaim) { 804 COUNT(ehci->stats.reclaim); 805 end_unlink_async(ehci); 806 } else 807 ehci_dbg(ehci, "IAA with nothing to reclaim?\n"); 808 } 809 810 /* remote wakeup [4.3.1] */ 811 if (status & STS_PCD) { 812 unsigned i = HCS_N_PORTS (ehci->hcs_params); 813 u32 ppcd = 0; 814 815 /* kick root hub later */ 816 pcd_status = status; 817 818 /* resume root hub? */ 819 if (!(cmd & CMD_RUN)) 820 usb_hcd_resume_root_hub(hcd); 821 822 /* get per-port change detect bits */ 823 if (ehci->has_ppcd) 824 ppcd = status >> 16; 825 826 while (i--) { 827 int pstatus; 828 829 /* leverage per-port change bits feature */ 830 if (ehci->has_ppcd && !(ppcd & (1 << i))) 831 continue; 832 pstatus = ehci_readl(ehci, 833 &ehci->regs->port_status[i]); 834 835 if (pstatus & PORT_OWNER) 836 continue; 837 if (!(test_bit(i, &ehci->suspended_ports) && 838 ((pstatus & PORT_RESUME) || 839 !(pstatus & PORT_SUSPEND)) && 840 (pstatus & PORT_PE) && 841 ehci->reset_done[i] == 0)) 842 continue; 843 844 /* start 20 msec resume signaling from this port, 845 * and make khubd collect PORT_STAT_C_SUSPEND to 846 * stop that signaling. Use 5 ms extra for safety, 847 * like usb_port_resume() does. 848 */ 849 ehci->reset_done[i] = jiffies + msecs_to_jiffies(25); 850 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); 851 mod_timer(&hcd->rh_timer, ehci->reset_done[i]); 852 } 853 } 854 855 /* PCI errors [4.15.2.4] */ 856 if (unlikely ((status & STS_FATAL) != 0)) { 857 ehci_err(ehci, "fatal error\n"); 858 dbg_cmd(ehci, "fatal", cmd); 859 dbg_status(ehci, "fatal", status); 860 ehci_halt(ehci); 861dead: 862 ehci_reset(ehci); 863 ehci_writel(ehci, 0, &ehci->regs->configured_flag); 864 /* generic layer kills/unlinks all urbs, then 865 * uses ehci_stop to clean up the rest 866 */ 867 bh = 1; 868 } 869 870 if (bh) 871 ehci_work (ehci); 872 spin_unlock (&ehci->lock); 873 if (pcd_status) 874 usb_hcd_poll_rh_status(hcd); 875 return IRQ_HANDLED; 876} 877 878/*-------------------------------------------------------------------------*/ 879 880/* 881 * non-error returns are a promise to giveback() the urb later 882 * we drop ownership so next owner (or urb unlink) can get it 883 * 884 * urb + dev is in hcd.self.controller.urb_list 885 * we're queueing TDs onto software and hardware lists 886 * 887 * hcd-specific init for hcpriv hasn't been done yet 888 * 889 * NOTE: control, bulk, and interrupt share the same code to append TDs 890 * to a (possibly active) QH, and the same QH scanning code. 891 */ 892static int ehci_urb_enqueue ( 893 struct usb_hcd *hcd, 894 struct urb *urb, 895 gfp_t mem_flags 896) { 897 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 898 struct list_head qtd_list; 899 900 INIT_LIST_HEAD (&qtd_list); 901 902 switch (usb_pipetype (urb->pipe)) { 903 case PIPE_CONTROL: 904 /* qh_completions() code doesn't handle all the fault cases 905 * in multi-TD control transfers. Even 1KB is rare anyway. 906 */ 907 if (urb->transfer_buffer_length > (16 * 1024)) 908 return -EMSGSIZE; 909 /* FALLTHROUGH */ 910 /* case PIPE_BULK: */ 911 default: 912 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) 913 return -ENOMEM; 914 return submit_async(ehci, urb, &qtd_list, mem_flags); 915 916 case PIPE_INTERRUPT: 917 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) 918 return -ENOMEM; 919 return intr_submit(ehci, urb, &qtd_list, mem_flags); 920 921 case PIPE_ISOCHRONOUS: 922 if (urb->dev->speed == USB_SPEED_HIGH) 923 return itd_submit (ehci, urb, mem_flags); 924 else 925 return sitd_submit (ehci, urb, mem_flags); 926 } 927} 928 929static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) 930{ 931 /* failfast */ 932 if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state) && ehci->reclaim) 933 end_unlink_async(ehci); 934 935 /* If the QH isn't linked then there's nothing we can do 936 * unless we were called during a giveback, in which case 937 * qh_completions() has to deal with it. 938 */ 939 if (qh->qh_state != QH_STATE_LINKED) { 940 if (qh->qh_state == QH_STATE_COMPLETING) 941 qh->needs_rescan = 1; 942 return; 943 } 944 945 /* defer till later if busy */ 946 if (ehci->reclaim) { 947 struct ehci_qh *last; 948 949 for (last = ehci->reclaim; 950 last->reclaim; 951 last = last->reclaim) 952 continue; 953 qh->qh_state = QH_STATE_UNLINK_WAIT; 954 last->reclaim = qh; 955 956 /* start IAA cycle */ 957 } else 958 start_unlink_async (ehci, qh); 959} 960 961/* remove from hardware lists 962 * completions normally happen asynchronously 963 */ 964 965static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 966{ 967 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 968 struct ehci_qh *qh; 969 unsigned long flags; 970 int rc; 971 972 spin_lock_irqsave (&ehci->lock, flags); 973 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 974 if (rc) 975 goto done; 976 977 switch (usb_pipetype (urb->pipe)) { 978 // case PIPE_CONTROL: 979 // case PIPE_BULK: 980 default: 981 qh = (struct ehci_qh *) urb->hcpriv; 982 if (!qh) 983 break; 984 switch (qh->qh_state) { 985 case QH_STATE_LINKED: 986 case QH_STATE_COMPLETING: 987 unlink_async(ehci, qh); 988 break; 989 case QH_STATE_UNLINK: 990 case QH_STATE_UNLINK_WAIT: 991 /* already started */ 992 break; 993 case QH_STATE_IDLE: 994 /* QH might be waiting for a Clear-TT-Buffer */ 995 qh_completions(ehci, qh); 996 break; 997 } 998 break; 999 1000 case PIPE_INTERRUPT: 1001 qh = (struct ehci_qh *) urb->hcpriv; 1002 if (!qh) 1003 break; 1004 switch (qh->qh_state) { 1005 case QH_STATE_LINKED: 1006 case QH_STATE_COMPLETING: 1007 intr_deschedule (ehci, qh); 1008 break; 1009 case QH_STATE_IDLE: 1010 qh_completions (ehci, qh); 1011 break; 1012 default: 1013 ehci_dbg (ehci, "bogus qh %p state %d\n", 1014 qh, qh->qh_state); 1015 goto done; 1016 } 1017 break; 1018 1019 case PIPE_ISOCHRONOUS: 1020 // itd or sitd ... 1021 1022 // wait till next completion, do it then. 1023 // completion irqs can wait up to 1024 msec, 1024 break; 1025 } 1026done: 1027 spin_unlock_irqrestore (&ehci->lock, flags); 1028 return rc; 1029} 1030 1031/*-------------------------------------------------------------------------*/ 1032 1033// bulk qh holds the data toggle 1034 1035static void 1036ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) 1037{ 1038 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1039 unsigned long flags; 1040 struct ehci_qh *qh, *tmp; 1041 1042 /* ASSERT: any requests/urbs are being unlinked */ 1043 /* ASSERT: nobody can be submitting urbs for this any more */ 1044 1045rescan: 1046 spin_lock_irqsave (&ehci->lock, flags); 1047 qh = ep->hcpriv; 1048 if (!qh) 1049 goto done; 1050 1051 /* endpoints can be iso streams. for now, we don't 1052 * accelerate iso completions ... so spin a while. 1053 */ 1054 if (qh->hw == NULL) { 1055 ehci_vdbg (ehci, "iso delay\n"); 1056 goto idle_timeout; 1057 } 1058 1059 if (!HC_IS_RUNNING (hcd->state)) 1060 qh->qh_state = QH_STATE_IDLE; 1061 switch (qh->qh_state) { 1062 case QH_STATE_LINKED: 1063 case QH_STATE_COMPLETING: 1064 for (tmp = ehci->async->qh_next.qh; 1065 tmp && tmp != qh; 1066 tmp = tmp->qh_next.qh) 1067 continue; 1068 /* periodic qh self-unlinks on empty, and a COMPLETING qh 1069 * may already be unlinked. 1070 */ 1071 if (tmp) 1072 unlink_async(ehci, qh); 1073 /* FALL THROUGH */ 1074 case QH_STATE_UNLINK: /* wait for hw to finish? */ 1075 case QH_STATE_UNLINK_WAIT: 1076idle_timeout: 1077 spin_unlock_irqrestore (&ehci->lock, flags); 1078 schedule_timeout_uninterruptible(1); 1079 goto rescan; 1080 case QH_STATE_IDLE: /* fully unlinked */ 1081 if (qh->clearing_tt) 1082 goto idle_timeout; 1083 if (list_empty (&qh->qtd_list)) { 1084 qh_put (qh); 1085 break; 1086 } 1087 /* else FALL THROUGH */ 1088 default: 1089 /* caller was supposed to have unlinked any requests; 1090 * that's not our job. just leak this memory. 1091 */ 1092 ehci_err (ehci, "qh %p (#%02x) state %d%s\n", 1093 qh, ep->desc.bEndpointAddress, qh->qh_state, 1094 list_empty (&qh->qtd_list) ? "" : "(has tds)"); 1095 break; 1096 } 1097 ep->hcpriv = NULL; 1098done: 1099 spin_unlock_irqrestore (&ehci->lock, flags); 1100 return; 1101} 1102 1103static void 1104ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep) 1105{ 1106 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 1107 struct ehci_qh *qh; 1108 int eptype = usb_endpoint_type(&ep->desc); 1109 int epnum = usb_endpoint_num(&ep->desc); 1110 int is_out = usb_endpoint_dir_out(&ep->desc); 1111 unsigned long flags; 1112 1113 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT) 1114 return; 1115 1116 spin_lock_irqsave(&ehci->lock, flags); 1117 qh = ep->hcpriv; 1118 1119 /* For Bulk and Interrupt endpoints we maintain the toggle state 1120 * in the hardware; the toggle bits in udev aren't used at all. 1121 * When an endpoint is reset by usb_clear_halt() we must reset 1122 * the toggle bit in the QH. 1123 */ 1124 if (qh) { 1125 usb_settoggle(qh->dev, epnum, is_out, 0); 1126 if (!list_empty(&qh->qtd_list)) { 1127 WARN_ONCE(1, "clear_halt for a busy endpoint\n"); 1128 } else if (qh->qh_state == QH_STATE_LINKED || 1129 qh->qh_state == QH_STATE_COMPLETING) { 1130 1131 /* The toggle value in the QH can't be updated 1132 * while the QH is active. Unlink it now; 1133 * re-linking will call qh_refresh(). 1134 */ 1135 if (eptype == USB_ENDPOINT_XFER_BULK) 1136 unlink_async(ehci, qh); 1137 else 1138 intr_deschedule(ehci, qh); 1139 } 1140 } 1141 spin_unlock_irqrestore(&ehci->lock, flags); 1142} 1143 1144static int ehci_get_frame (struct usb_hcd *hcd) 1145{ 1146 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1147 return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) % 1148 ehci->periodic_size; 1149} 1150 1151/*-------------------------------------------------------------------------*/ 1152 1153MODULE_DESCRIPTION(DRIVER_DESC); 1154MODULE_AUTHOR (DRIVER_AUTHOR); 1155MODULE_LICENSE ("GPL"); 1156 1157#ifdef CONFIG_PCI 1158#include "ehci-pci.c" 1159#define PCI_DRIVER ehci_pci_driver 1160#endif 1161 1162#ifdef CONFIG_USB_EHCI_FSL 1163#include "ehci-fsl.c" 1164#define PLATFORM_DRIVER ehci_fsl_driver 1165#endif 1166 1167#ifdef CONFIG_USB_EHCI_MXC 1168#include "ehci-mxc.c" 1169#define PLATFORM_DRIVER ehci_mxc_driver 1170#endif 1171 1172#ifdef CONFIG_SOC_AU1200 1173#include "ehci-au1xxx.c" 1174#define PLATFORM_DRIVER ehci_hcd_au1xxx_driver 1175#endif 1176 1177#ifdef CONFIG_ARCH_OMAP3 1178#include "ehci-omap.c" 1179#define PLATFORM_DRIVER ehci_hcd_omap_driver 1180#endif 1181 1182#ifdef CONFIG_PPC_PS3 1183#include "ehci-ps3.c" 1184#define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver 1185#endif 1186 1187#ifdef CONFIG_USB_EHCI_HCD_PPC_OF 1188#include "ehci-ppc-of.c" 1189#define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver 1190#endif 1191 1192#ifdef CONFIG_XPS_USB_HCD_XILINX 1193#include "ehci-xilinx-of.c" 1194#define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver 1195#endif 1196 1197#ifdef CONFIG_PLAT_ORION 1198#include "ehci-orion.c" 1199#define PLATFORM_DRIVER ehci_orion_driver 1200#endif 1201 1202#ifdef CONFIG_ARCH_IXP4XX 1203#include "ehci-ixp4xx.c" 1204#define PLATFORM_DRIVER ixp4xx_ehci_driver 1205#endif 1206 1207#ifdef CONFIG_USB_W90X900_EHCI 1208#include "ehci-w90x900.c" 1209#define PLATFORM_DRIVER ehci_hcd_w90x900_driver 1210#endif 1211 1212#ifdef CONFIG_ARCH_AT91 1213#include "ehci-atmel.c" 1214#define PLATFORM_DRIVER ehci_atmel_driver 1215#endif 1216 1217#ifdef CONFIG_MIPS_SEAD3 1218#include "ehci-mips.c" 1219#define PLATFORM_DRIVER ehci_hcd_mips_driver 1220#endif 1221 1222#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ 1223 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ 1224 !defined(XILINX_OF_PLATFORM_DRIVER) 1225#error "missing bus glue for ehci-hcd" 1226#endif 1227 1228static int __init ehci_hcd_init(void) 1229{ 1230 int retval = 0; 1231 1232 if (usb_disabled()) 1233 return -ENODEV; 1234 1235 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); 1236 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1237 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) || 1238 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded)) 1239 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded" 1240 " before uhci_hcd and ohci_hcd, not after\n"); 1241 1242 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", 1243 hcd_name, 1244 sizeof(struct ehci_qh), sizeof(struct ehci_qtd), 1245 sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); 1246 1247#ifdef DEBUG 1248 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root); 1249 if (!ehci_debug_root) { 1250 retval = -ENOENT; 1251 goto err_debug; 1252 } 1253#endif 1254 1255#ifdef PLATFORM_DRIVER 1256 retval = platform_driver_register(&PLATFORM_DRIVER); 1257 if (retval < 0) 1258 goto clean0; 1259#endif 1260 1261#ifdef PCI_DRIVER 1262 retval = pci_register_driver(&PCI_DRIVER); 1263 if (retval < 0) 1264 goto clean1; 1265#endif 1266 1267#ifdef PS3_SYSTEM_BUS_DRIVER 1268 retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER); 1269 if (retval < 0) 1270 goto clean2; 1271#endif 1272 1273#ifdef OF_PLATFORM_DRIVER 1274 retval = of_register_platform_driver(&OF_PLATFORM_DRIVER); 1275 if (retval < 0) 1276 goto clean3; 1277#endif 1278 1279#ifdef XILINX_OF_PLATFORM_DRIVER 1280 retval = of_register_platform_driver(&XILINX_OF_PLATFORM_DRIVER); 1281 if (retval < 0) 1282 goto clean4; 1283#endif 1284 return retval; 1285 1286#ifdef XILINX_OF_PLATFORM_DRIVER 1287 /* of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER); */ 1288clean4: 1289#endif 1290#ifdef OF_PLATFORM_DRIVER 1291 of_unregister_platform_driver(&OF_PLATFORM_DRIVER); 1292clean3: 1293#endif 1294#ifdef PS3_SYSTEM_BUS_DRIVER 1295 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1296clean2: 1297#endif 1298#ifdef PCI_DRIVER 1299 pci_unregister_driver(&PCI_DRIVER); 1300clean1: 1301#endif 1302#ifdef PLATFORM_DRIVER 1303 platform_driver_unregister(&PLATFORM_DRIVER); 1304clean0: 1305#endif 1306#ifdef DEBUG 1307 debugfs_remove(ehci_debug_root); 1308 ehci_debug_root = NULL; 1309err_debug: 1310#endif 1311 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1312 return retval; 1313} 1314module_init(ehci_hcd_init); 1315 1316static void __exit ehci_hcd_cleanup(void) 1317{ 1318#ifdef XILINX_OF_PLATFORM_DRIVER 1319 of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER); 1320#endif 1321#ifdef OF_PLATFORM_DRIVER 1322 of_unregister_platform_driver(&OF_PLATFORM_DRIVER); 1323#endif 1324#ifdef PLATFORM_DRIVER 1325 platform_driver_unregister(&PLATFORM_DRIVER); 1326#endif 1327#ifdef PCI_DRIVER 1328 pci_unregister_driver(&PCI_DRIVER); 1329#endif 1330#ifdef PS3_SYSTEM_BUS_DRIVER 1331 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1332#endif 1333#ifdef DEBUG 1334 debugfs_remove(ehci_debug_root); 1335#endif 1336 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1337} 1338module_exit(ehci_hcd_cleanup); 1339