1/***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2008 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28/* 29 * Support library for the hardware Packet Output unit. 30 */ 31 32#include <asm/octeon/octeon.h> 33 34#include "cvmx-config.h" 35#include "cvmx-pko.h" 36#include "cvmx-helper.h" 37 38/** 39 * Internal state of packet output 40 */ 41 42/** 43 * Call before any other calls to initialize the packet 44 * output system. This does chip global config, and should only be 45 * done by one core. 46 */ 47 48void cvmx_pko_initialize_global(void) 49{ 50 int i; 51 uint64_t priority = 8; 52 union cvmx_pko_reg_cmd_buf config; 53 54 /* 55 * Set the size of the PKO command buffers to an odd number of 56 * 64bit words. This allows the normal two word send to stay 57 * aligned and never span a comamnd word buffer. 58 */ 59 config.u64 = 0; 60 config.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL; 61 config.s.size = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE / 8 - 1; 62 63 cvmx_write_csr(CVMX_PKO_REG_CMD_BUF, config.u64); 64 65 for (i = 0; i < CVMX_PKO_MAX_OUTPUT_QUEUES; i++) 66 cvmx_pko_config_port(CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID, i, 1, 67 &priority); 68 69 /* 70 * If we aren't using all of the queues optimize PKO's 71 * internal memory. 72 */ 73 if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) 74 || OCTEON_IS_MODEL(OCTEON_CN56XX) 75 || OCTEON_IS_MODEL(OCTEON_CN52XX)) { 76 int num_interfaces = cvmx_helper_get_number_of_interfaces(); 77 int last_port = 78 cvmx_helper_get_last_ipd_port(num_interfaces - 1); 79 int max_queues = 80 cvmx_pko_get_base_queue(last_port) + 81 cvmx_pko_get_num_queues(last_port); 82 if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { 83 if (max_queues <= 32) 84 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2); 85 else if (max_queues <= 64) 86 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1); 87 } else { 88 if (max_queues <= 64) 89 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2); 90 else if (max_queues <= 128) 91 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1); 92 } 93 } 94} 95 96/** 97 * This function does per-core initialization required by the PKO routines. 98 * This must be called on all cores that will do packet output, and must 99 * be called after the FPA has been initialized and filled with pages. 100 * 101 * Returns 0 on success 102 * !0 on failure 103 */ 104int cvmx_pko_initialize_local(void) 105{ 106 /* Nothing to do */ 107 return 0; 108} 109 110/** 111 * Enables the packet output hardware. It must already be 112 * configured. 113 */ 114void cvmx_pko_enable(void) 115{ 116 union cvmx_pko_reg_flags flags; 117 118 flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS); 119 if (flags.s.ena_pko) 120 cvmx_dprintf 121 ("Warning: Enabling PKO when PKO already enabled.\n"); 122 123 flags.s.ena_dwb = 1; 124 flags.s.ena_pko = 1; 125 /* 126 * always enable big endian for 3-word command. Does nothing 127 * for 2-word. 128 */ 129 flags.s.store_be = 1; 130 cvmx_write_csr(CVMX_PKO_REG_FLAGS, flags.u64); 131} 132 133/** 134 * Disables the packet output. Does not affect any configuration. 135 */ 136void cvmx_pko_disable(void) 137{ 138 union cvmx_pko_reg_flags pko_reg_flags; 139 pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS); 140 pko_reg_flags.s.ena_pko = 0; 141 cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64); 142} 143 144 145/** 146 * Reset the packet output. 147 */ 148static void __cvmx_pko_reset(void) 149{ 150 union cvmx_pko_reg_flags pko_reg_flags; 151 pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS); 152 pko_reg_flags.s.reset = 1; 153 cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64); 154} 155 156/** 157 * Shutdown and free resources required by packet output. 158 */ 159void cvmx_pko_shutdown(void) 160{ 161 union cvmx_pko_mem_queue_ptrs config; 162 int queue; 163 164 cvmx_pko_disable(); 165 166 for (queue = 0; queue < CVMX_PKO_MAX_OUTPUT_QUEUES; queue++) { 167 config.u64 = 0; 168 config.s.tail = 1; 169 config.s.index = 0; 170 config.s.port = CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID; 171 config.s.queue = queue & 0x7f; 172 config.s.qos_mask = 0; 173 config.s.buf_ptr = 0; 174 if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) { 175 union cvmx_pko_reg_queue_ptrs1 config1; 176 config1.u64 = 0; 177 config1.s.qid7 = queue >> 7; 178 cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64); 179 } 180 cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64); 181 cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_PKO(queue)); 182 } 183 __cvmx_pko_reset(); 184} 185 186/** 187 * Configure a output port and the associated queues for use. 188 * 189 * @port: Port to configure. 190 * @base_queue: First queue number to associate with this port. 191 * @num_queues: Number of queues to associate with this port 192 * @priority: Array of priority levels for each queue. Values are 193 * allowed to be 0-8. A value of 8 get 8 times the traffic 194 * of a value of 1. A value of 0 indicates that no rounds 195 * will be participated in. These priorities can be changed 196 * on the fly while the pko is enabled. A priority of 9 197 * indicates that static priority should be used. If static 198 * priority is used all queues with static priority must be 199 * contiguous starting at the base_queue, and lower numbered 200 * queues have higher priority than higher numbered queues. 201 * There must be num_queues elements in the array. 202 */ 203cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, 204 uint64_t num_queues, 205 const uint64_t priority[]) 206{ 207 cvmx_pko_status_t result_code; 208 uint64_t queue; 209 union cvmx_pko_mem_queue_ptrs config; 210 union cvmx_pko_reg_queue_ptrs1 config1; 211 int static_priority_base = -1; 212 int static_priority_end = -1; 213 214 if ((port >= CVMX_PKO_NUM_OUTPUT_PORTS) 215 && (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID)) { 216 cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid port %llu\n", 217 (unsigned long long)port); 218 return CVMX_PKO_INVALID_PORT; 219 } 220 221 if (base_queue + num_queues > CVMX_PKO_MAX_OUTPUT_QUEUES) { 222 cvmx_dprintf 223 ("ERROR: cvmx_pko_config_port: Invalid queue range %llu\n", 224 (unsigned long long)(base_queue + num_queues)); 225 return CVMX_PKO_INVALID_QUEUE; 226 } 227 228 if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID) { 229 /* 230 * Validate the static queue priority setup and set 231 * static_priority_base and static_priority_end 232 * accordingly. 233 */ 234 for (queue = 0; queue < num_queues; queue++) { 235 /* Find first queue of static priority */ 236 if (static_priority_base == -1 237 && priority[queue] == 238 CVMX_PKO_QUEUE_STATIC_PRIORITY) 239 static_priority_base = queue; 240 /* Find last queue of static priority */ 241 if (static_priority_base != -1 242 && static_priority_end == -1 243 && priority[queue] != CVMX_PKO_QUEUE_STATIC_PRIORITY 244 && queue) 245 static_priority_end = queue - 1; 246 else if (static_priority_base != -1 247 && static_priority_end == -1 248 && queue == num_queues - 1) 249 /* all queues are static priority */ 250 static_priority_end = queue; 251 /* 252 * Check to make sure all static priority 253 * queues are contiguous. Also catches some 254 * cases of static priorites not starting at 255 * queue 0. 256 */ 257 if (static_priority_end != -1 258 && (int)queue > static_priority_end 259 && priority[queue] == 260 CVMX_PKO_QUEUE_STATIC_PRIORITY) { 261 cvmx_dprintf("ERROR: cvmx_pko_config_port: " 262 "Static priority queues aren't " 263 "contiguous or don't start at " 264 "base queue. q: %d, eq: %d\n", 265 (int)queue, static_priority_end); 266 return CVMX_PKO_INVALID_PRIORITY; 267 } 268 } 269 if (static_priority_base > 0) { 270 cvmx_dprintf("ERROR: cvmx_pko_config_port: Static " 271 "priority queues don't start at base " 272 "queue. sq: %d\n", 273 static_priority_base); 274 return CVMX_PKO_INVALID_PRIORITY; 275 } 276 } 277 /* 278 * At this point, static_priority_base and static_priority_end 279 * are either both -1, or are valid start/end queue 280 * numbers. 281 */ 282 283 result_code = CVMX_PKO_SUCCESS; 284 285#ifdef PKO_DEBUG 286 cvmx_dprintf("num queues: %d (%lld,%lld)\n", num_queues, 287 CVMX_PKO_QUEUES_PER_PORT_INTERFACE0, 288 CVMX_PKO_QUEUES_PER_PORT_INTERFACE1); 289#endif 290 291 for (queue = 0; queue < num_queues; queue++) { 292 uint64_t *buf_ptr = NULL; 293 294 config1.u64 = 0; 295 config1.s.idx3 = queue >> 3; 296 config1.s.qid7 = (base_queue + queue) >> 7; 297 298 config.u64 = 0; 299 config.s.tail = queue == (num_queues - 1); 300 config.s.index = queue; 301 config.s.port = port; 302 config.s.queue = base_queue + queue; 303 304 if (!cvmx_octeon_is_pass1()) { 305 config.s.static_p = static_priority_base >= 0; 306 config.s.static_q = (int)queue <= static_priority_end; 307 config.s.s_tail = (int)queue == static_priority_end; 308 } 309 /* 310 * Convert the priority into an enable bit field. Try 311 * to space the bits out evenly so the packet don't 312 * get grouped up 313 */ 314 switch ((int)priority[queue]) { 315 case 0: 316 config.s.qos_mask = 0x00; 317 break; 318 case 1: 319 config.s.qos_mask = 0x01; 320 break; 321 case 2: 322 config.s.qos_mask = 0x11; 323 break; 324 case 3: 325 config.s.qos_mask = 0x49; 326 break; 327 case 4: 328 config.s.qos_mask = 0x55; 329 break; 330 case 5: 331 config.s.qos_mask = 0x57; 332 break; 333 case 6: 334 config.s.qos_mask = 0x77; 335 break; 336 case 7: 337 config.s.qos_mask = 0x7f; 338 break; 339 case 8: 340 config.s.qos_mask = 0xff; 341 break; 342 case CVMX_PKO_QUEUE_STATIC_PRIORITY: 343 /* Pass 1 will fall through to the error case */ 344 if (!cvmx_octeon_is_pass1()) { 345 config.s.qos_mask = 0xff; 346 break; 347 } 348 default: 349 cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid " 350 "priority %llu\n", 351 (unsigned long long)priority[queue]); 352 config.s.qos_mask = 0xff; 353 result_code = CVMX_PKO_INVALID_PRIORITY; 354 break; 355 } 356 357 if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID) { 358 cvmx_cmd_queue_result_t cmd_res = 359 cvmx_cmd_queue_initialize(CVMX_CMD_QUEUE_PKO 360 (base_queue + queue), 361 CVMX_PKO_MAX_QUEUE_DEPTH, 362 CVMX_FPA_OUTPUT_BUFFER_POOL, 363 CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE 364 - 365 CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST 366 * 8); 367 if (cmd_res != CVMX_CMD_QUEUE_SUCCESS) { 368 switch (cmd_res) { 369 case CVMX_CMD_QUEUE_NO_MEMORY: 370 cvmx_dprintf("ERROR: " 371 "cvmx_pko_config_port: " 372 "Unable to allocate " 373 "output buffer.\n"); 374 return CVMX_PKO_NO_MEMORY; 375 case CVMX_CMD_QUEUE_ALREADY_SETUP: 376 cvmx_dprintf 377 ("ERROR: cvmx_pko_config_port: Port already setup.\n"); 378 return CVMX_PKO_PORT_ALREADY_SETUP; 379 case CVMX_CMD_QUEUE_INVALID_PARAM: 380 default: 381 cvmx_dprintf 382 ("ERROR: cvmx_pko_config_port: Command queue initialization failed.\n"); 383 return CVMX_PKO_CMD_QUEUE_INIT_ERROR; 384 } 385 } 386 387 buf_ptr = 388 (uint64_t *) 389 cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_PKO 390 (base_queue + queue)); 391 config.s.buf_ptr = cvmx_ptr_to_phys(buf_ptr); 392 } else 393 config.s.buf_ptr = 0; 394 395 CVMX_SYNCWS; 396 397 if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) 398 cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64); 399 cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64); 400 } 401 402 return result_code; 403} 404 405#ifdef PKO_DEBUG 406/** 407 * Show map of ports -> queues for different cores. 408 */ 409void cvmx_pko_show_queue_map() 410{ 411 int core, port; 412 int pko_output_ports = 36; 413 414 cvmx_dprintf("port"); 415 for (port = 0; port < pko_output_ports; port++) 416 cvmx_dprintf("%3d ", port); 417 cvmx_dprintf("\n"); 418 419 for (core = 0; core < CVMX_MAX_CORES; core++) { 420 cvmx_dprintf("\n%2d: ", core); 421 for (port = 0; port < pko_output_ports; port++) { 422 cvmx_dprintf("%3d ", 423 cvmx_pko_get_base_queue_per_core(port, 424 core)); 425 } 426 } 427 cvmx_dprintf("\n"); 428} 429#endif 430 431/** 432 * Rate limit a PKO port to a max packets/sec. This function is only 433 * supported on CN51XX and higher, excluding CN58XX. 434 * 435 * @port: Port to rate limit 436 * @packets_s: Maximum packet/sec 437 * @burst: Maximum number of packets to burst in a row before rate 438 * limiting cuts in. 439 * 440 * Returns Zero on success, negative on failure 441 */ 442int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst) 443{ 444 union cvmx_pko_mem_port_rate0 pko_mem_port_rate0; 445 union cvmx_pko_mem_port_rate1 pko_mem_port_rate1; 446 447 pko_mem_port_rate0.u64 = 0; 448 pko_mem_port_rate0.s.pid = port; 449 pko_mem_port_rate0.s.rate_pkt = 450 cvmx_sysinfo_get()->cpu_clock_hz / packets_s / 16; 451 /* No cost per word since we are limited by packets/sec, not bits/sec */ 452 pko_mem_port_rate0.s.rate_word = 0; 453 454 pko_mem_port_rate1.u64 = 0; 455 pko_mem_port_rate1.s.pid = port; 456 pko_mem_port_rate1.s.rate_lim = 457 ((uint64_t) pko_mem_port_rate0.s.rate_pkt * burst) >> 8; 458 459 cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64); 460 cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64); 461 return 0; 462} 463 464/** 465 * Rate limit a PKO port to a max bits/sec. This function is only 466 * supported on CN51XX and higher, excluding CN58XX. 467 * 468 * @port: Port to rate limit 469 * @bits_s: PKO rate limit in bits/sec 470 * @burst: Maximum number of bits to burst before rate 471 * limiting cuts in. 472 * 473 * Returns Zero on success, negative on failure 474 */ 475int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst) 476{ 477 union cvmx_pko_mem_port_rate0 pko_mem_port_rate0; 478 union cvmx_pko_mem_port_rate1 pko_mem_port_rate1; 479 uint64_t clock_rate = cvmx_sysinfo_get()->cpu_clock_hz; 480 uint64_t tokens_per_bit = clock_rate * 16 / bits_s; 481 482 pko_mem_port_rate0.u64 = 0; 483 pko_mem_port_rate0.s.pid = port; 484 /* 485 * Each packet has a 12 bytes of interframe gap, an 8 byte 486 * preamble, and a 4 byte CRC. These are not included in the 487 * per word count. Multiply by 8 to covert to bits and divide 488 * by 256 for limit granularity. 489 */ 490 pko_mem_port_rate0.s.rate_pkt = (12 + 8 + 4) * 8 * tokens_per_bit / 256; 491 /* Each 8 byte word has 64bits */ 492 pko_mem_port_rate0.s.rate_word = 64 * tokens_per_bit; 493 494 pko_mem_port_rate1.u64 = 0; 495 pko_mem_port_rate1.s.pid = port; 496 pko_mem_port_rate1.s.rate_lim = tokens_per_bit * burst / 256; 497 498 cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64); 499 cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64); 500 return 0; 501} 502