1/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 * You should have received a copy of the GNU General Public License 13 * along with this program; if not, write to the Free Software 14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 15 * 02110-1301, USA. 16 */ 17 18#include "msm_fb.h" 19#include "mddihost.h" 20#include "mddihosti.h" 21#include "mddi_toshiba.h" 22 23#define TM_GET_DID(id) ((id) & 0xff) 24#define TM_GET_PID(id) (((id) & 0xff00)>>8) 25 26#define MDDI_CLIENT_CORE_BASE 0x108000 27#define LCD_CONTROL_BLOCK_BASE 0x110000 28#define SPI_BLOCK_BASE 0x120000 29#define PWM_BLOCK_BASE 0x140000 30#define SYSTEM_BLOCK1_BASE 0x160000 31 32#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18) 33#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C) 34#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20) 35#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24) 36#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28) 37#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C) 38 39#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44) 40#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48) 41#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C) 42#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50) 43#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54) 44 45#define SRST (LCD_CONTROL_BLOCK_BASE|0x00) 46#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04) 47#define START (LCD_CONTROL_BLOCK_BASE|0x08) 48#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C) 49 50#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18) 51#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C) 52#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20) 53 54#define PXL (LCD_CONTROL_BLOCK_BASE|0x30) 55#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34) 56#define HSW (LCD_CONTROL_BLOCK_BASE|0x38) 57#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C) 58#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40) 59#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44) 60#define VSW (LCD_CONTROL_BLOCK_BASE|0x48) 61#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C) 62#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50) 63#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54) 64#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C) 65#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60) 66#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64) 67#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68) 68#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C) 69#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70) 70#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74) 71#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78) 72#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C) 73#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80) 74#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84) 75#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88) 76#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C) 77#define MONI (LCD_CONTROL_BLOCK_BASE|0xB0) 78#define VPOS (LCD_CONTROL_BLOCK_BASE|0xC0) 79 80#define SSICTL (SPI_BLOCK_BASE|0x00) 81#define SSITIME (SPI_BLOCK_BASE|0x04) 82#define SSITX (SPI_BLOCK_BASE|0x08) 83#define SSIINTS (SPI_BLOCK_BASE|0x14) 84 85#define TIMER0LOAD (PWM_BLOCK_BASE|0x00) 86#define TIMER0CTRL (PWM_BLOCK_BASE|0x08) 87#define PWM0OFF (PWM_BLOCK_BASE|0x1C) 88#define TIMER1LOAD (PWM_BLOCK_BASE|0x20) 89#define TIMER1CTRL (PWM_BLOCK_BASE|0x28) 90#define PWM1OFF (PWM_BLOCK_BASE|0x3C) 91#define TIMER2LOAD (PWM_BLOCK_BASE|0x40) 92#define TIMER2CTRL (PWM_BLOCK_BASE|0x48) 93#define PWM2OFF (PWM_BLOCK_BASE|0x5C) 94#define PWMCR (PWM_BLOCK_BASE|0x68) 95 96#define GPIOIS (GPIO_BLOCK_BASE|0x08) 97#define GPIOIEV (GPIO_BLOCK_BASE|0x10) 98#define GPIOIC (GPIO_BLOCK_BASE|0x20) 99 100#define WKREQ (SYSTEM_BLOCK1_BASE|0x00) 101#define CLKENB (SYSTEM_BLOCK1_BASE|0x04) 102#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08) 103#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C) 104#define CNT_DIS (SYSTEM_BLOCK1_BASE|0x10) 105 106typedef enum { 107 TOSHIBA_STATE_OFF, 108 TOSHIBA_STATE_PRIM_SEC_STANDBY, 109 TOSHIBA_STATE_PRIM_SEC_READY, 110 TOSHIBA_STATE_PRIM_NORMAL_MODE, 111 TOSHIBA_STATE_SEC_NORMAL_MODE 112} mddi_toshiba_state_t; 113 114static uint32 mddi_toshiba_curr_vpos; 115static boolean mddi_toshiba_monitor_refresh_value = FALSE; 116static boolean mddi_toshiba_report_refresh_measurements = FALSE; 117 118boolean mddi_toshiba_61Hz_refresh = TRUE; 119 120/* Modifications to timing to increase refresh rate to > 60Hz. 121 * 20MHz dot clock. 122 * 646 total rows. 123 * 506 total columns. 124 * refresh rate = 61.19Hz 125 */ 126static uint32 mddi_toshiba_rows_per_second = 39526; 127static uint32 mddi_toshiba_usecs_per_refresh = 16344; 128static uint32 mddi_toshiba_rows_per_refresh = 646; 129extern boolean mddi_vsync_detect_enabled; 130 131static msm_fb_vsync_handler_type mddi_toshiba_vsync_handler; 132static void *mddi_toshiba_vsync_handler_arg; 133static uint16 mddi_toshiba_vsync_attempts; 134 135static mddi_toshiba_state_t toshiba_state = TOSHIBA_STATE_OFF; 136 137static struct msm_panel_common_pdata *mddi_toshiba_pdata; 138 139static int mddi_toshiba_lcd_on(struct platform_device *pdev); 140static int mddi_toshiba_lcd_off(struct platform_device *pdev); 141 142static void mddi_toshiba_state_transition(mddi_toshiba_state_t a, 143 mddi_toshiba_state_t b) 144{ 145 if (toshiba_state != a) { 146 MDDI_MSG_ERR("toshiba state trans. (%d->%d) found %d\n", a, b, 147 toshiba_state); 148 } 149 toshiba_state = b; 150} 151 152#define GORDON_REG_IMGCTL1 0x10 /* Image interface control 1 */ 153#define GORDON_REG_IMGCTL2 0x11 /* Image interface control 2 */ 154#define GORDON_REG_IMGSET1 0x12 /* Image interface settings 1 */ 155#define GORDON_REG_IMGSET2 0x13 /* Image interface settings 2 */ 156#define GORDON_REG_IVBP1 0x14 /* DM0: Vert back porch */ 157#define GORDON_REG_IHBP1 0x15 /* DM0: Horiz back porch */ 158#define GORDON_REG_IVNUM1 0x16 /* DM0: Num of vert lines */ 159#define GORDON_REG_IHNUM1 0x17 /* DM0: Num of pixels per line */ 160#define GORDON_REG_IVBP2 0x18 /* DM1: Vert back porch */ 161#define GORDON_REG_IHBP2 0x19 /* DM1: Horiz back porch */ 162#define GORDON_REG_IVNUM2 0x1A /* DM1: Num of vert lines */ 163#define GORDON_REG_IHNUM2 0x1B /* DM1: Num of pixels per line */ 164#define GORDON_REG_LCDIFCTL1 0x30 /* LCD interface control 1 */ 165#define GORDON_REG_VALTRAN 0x31 /* LCD IF ctl: VALTRAN sync flag */ 166#define GORDON_REG_AVCTL 0x33 167#define GORDON_REG_LCDIFCTL2 0x34 /* LCD interface control 2 */ 168#define GORDON_REG_LCDIFCTL3 0x35 /* LCD interface control 3 */ 169#define GORDON_REG_LCDIFSET1 0x36 /* LCD interface settings 1 */ 170#define GORDON_REG_PCCTL 0x3C 171#define GORDON_REG_TPARAM1 0x40 172#define GORDON_REG_TLCDIF1 0x41 173#define GORDON_REG_TSSPB_ST1 0x42 174#define GORDON_REG_TSSPB_ED1 0x43 175#define GORDON_REG_TSCK_ST1 0x44 176#define GORDON_REG_TSCK_WD1 0x45 177#define GORDON_REG_TGSPB_VST1 0x46 178#define GORDON_REG_TGSPB_VED1 0x47 179#define GORDON_REG_TGSPB_CH1 0x48 180#define GORDON_REG_TGCK_ST1 0x49 181#define GORDON_REG_TGCK_ED1 0x4A 182#define GORDON_REG_TPCTL_ST1 0x4B 183#define GORDON_REG_TPCTL_ED1 0x4C 184#define GORDON_REG_TPCHG_ED1 0x4D 185#define GORDON_REG_TCOM_CH1 0x4E 186#define GORDON_REG_THBP1 0x4F 187#define GORDON_REG_TPHCTL1 0x50 188#define GORDON_REG_EVPH1 0x51 189#define GORDON_REG_EVPL1 0x52 190#define GORDON_REG_EVNH1 0x53 191#define GORDON_REG_EVNL1 0x54 192#define GORDON_REG_TBIAS1 0x55 193#define GORDON_REG_TPARAM2 0x56 194#define GORDON_REG_TLCDIF2 0x57 195#define GORDON_REG_TSSPB_ST2 0x58 196#define GORDON_REG_TSSPB_ED2 0x59 197#define GORDON_REG_TSCK_ST2 0x5A 198#define GORDON_REG_TSCK_WD2 0x5B 199#define GORDON_REG_TGSPB_VST2 0x5C 200#define GORDON_REG_TGSPB_VED2 0x5D 201#define GORDON_REG_TGSPB_CH2 0x5E 202#define GORDON_REG_TGCK_ST2 0x5F 203#define GORDON_REG_TGCK_ED2 0x60 204#define GORDON_REG_TPCTL_ST2 0x61 205#define GORDON_REG_TPCTL_ED2 0x62 206#define GORDON_REG_TPCHG_ED2 0x63 207#define GORDON_REG_TCOM_CH2 0x64 208#define GORDON_REG_THBP2 0x65 209#define GORDON_REG_TPHCTL2 0x66 210#define GORDON_REG_EVPH2 0x67 211#define GORDON_REG_EVPL2 0x68 212#define GORDON_REG_EVNH2 0x69 213#define GORDON_REG_EVNL2 0x6A 214#define GORDON_REG_TBIAS2 0x6B 215#define GORDON_REG_POWCTL 0x80 216#define GORDON_REG_POWOSC1 0x81 217#define GORDON_REG_POWOSC2 0x82 218#define GORDON_REG_POWSET 0x83 219#define GORDON_REG_POWTRM1 0x85 220#define GORDON_REG_POWTRM2 0x86 221#define GORDON_REG_POWTRM3 0x87 222#define GORDON_REG_POWTRMSEL 0x88 223#define GORDON_REG_POWHIZ 0x89 224 225void serigo(uint16 reg, uint8 data) 226{ 227 uint32 mddi_val = 0; 228 mddi_queue_register_read(SSIINTS, &mddi_val, TRUE, 0); 229 if (mddi_val & (1 << 8)) 230 mddi_wait(1); 231 /* No De-assert of CS and send 2 bytes */ 232 mddi_val = 0x90000 | ((0x00FF & reg) << 8) | data; 233 mddi_queue_register_write(SSITX, mddi_val, TRUE, 0); 234} 235 236void gordon_init(void) 237{ 238 /* Image interface settings ***/ 239 serigo(GORDON_REG_IMGCTL2, 0x00); 240 serigo(GORDON_REG_IMGSET1, 0x01); 241 242 /* Exchange the RGB signal for J510(Softbank mobile) */ 243 serigo(GORDON_REG_IMGSET2, 0x12); 244 serigo(GORDON_REG_LCDIFSET1, 0x00); 245 mddi_wait(2); 246 247 /* Pre-charge settings */ 248 serigo(GORDON_REG_PCCTL, 0x09); 249 serigo(GORDON_REG_LCDIFCTL2, 0x1B); 250 mddi_wait(1); 251} 252 253void gordon_disp_on(void) 254{ 255 /*gordon_dispmode setting */ 256 /*VGA settings */ 257 serigo(GORDON_REG_TPARAM1, 0x30); 258 serigo(GORDON_REG_TLCDIF1, 0x00); 259 serigo(GORDON_REG_TSSPB_ST1, 0x8B); 260 serigo(GORDON_REG_TSSPB_ED1, 0x93); 261 mddi_wait(2); 262 serigo(GORDON_REG_TSCK_ST1, 0x88); 263 serigo(GORDON_REG_TSCK_WD1, 0x00); 264 serigo(GORDON_REG_TGSPB_VST1, 0x01); 265 serigo(GORDON_REG_TGSPB_VED1, 0x02); 266 mddi_wait(2); 267 serigo(GORDON_REG_TGSPB_CH1, 0x5E); 268 serigo(GORDON_REG_TGCK_ST1, 0x80); 269 serigo(GORDON_REG_TGCK_ED1, 0x3C); 270 serigo(GORDON_REG_TPCTL_ST1, 0x50); 271 mddi_wait(2); 272 serigo(GORDON_REG_TPCTL_ED1, 0x74); 273 serigo(GORDON_REG_TPCHG_ED1, 0x78); 274 serigo(GORDON_REG_TCOM_CH1, 0x50); 275 serigo(GORDON_REG_THBP1, 0x84); 276 mddi_wait(2); 277 serigo(GORDON_REG_TPHCTL1, 0x00); 278 serigo(GORDON_REG_EVPH1, 0x70); 279 serigo(GORDON_REG_EVPL1, 0x64); 280 serigo(GORDON_REG_EVNH1, 0x56); 281 mddi_wait(2); 282 serigo(GORDON_REG_EVNL1, 0x48); 283 serigo(GORDON_REG_TBIAS1, 0x88); 284 mddi_wait(2); 285 serigo(GORDON_REG_TPARAM2, 0x28); 286 serigo(GORDON_REG_TLCDIF2, 0x14); 287 serigo(GORDON_REG_TSSPB_ST2, 0x49); 288 serigo(GORDON_REG_TSSPB_ED2, 0x4B); 289 mddi_wait(2); 290 serigo(GORDON_REG_TSCK_ST2, 0x4A); 291 serigo(GORDON_REG_TSCK_WD2, 0x02); 292 serigo(GORDON_REG_TGSPB_VST2, 0x02); 293 serigo(GORDON_REG_TGSPB_VED2, 0x03); 294 mddi_wait(2); 295 serigo(GORDON_REG_TGSPB_CH2, 0x2F); 296 serigo(GORDON_REG_TGCK_ST2, 0x40); 297 serigo(GORDON_REG_TGCK_ED2, 0x1E); 298 serigo(GORDON_REG_TPCTL_ST2, 0x2C); 299 mddi_wait(2); 300 serigo(GORDON_REG_TPCTL_ED2, 0x3A); 301 serigo(GORDON_REG_TPCHG_ED2, 0x3C); 302 serigo(GORDON_REG_TCOM_CH2, 0x28); 303 serigo(GORDON_REG_THBP2, 0x4D); 304 mddi_wait(2); 305 serigo(GORDON_REG_TPHCTL2, 0x1A); 306 mddi_wait(2); 307 serigo(GORDON_REG_IVBP1, 0x02); 308 serigo(GORDON_REG_IHBP1, 0x90); 309 serigo(GORDON_REG_IVNUM1, 0xA0); 310 serigo(GORDON_REG_IHNUM1, 0x78); 311 mddi_wait(2); 312 serigo(GORDON_REG_IVBP2, 0x02); 313 serigo(GORDON_REG_IHBP2, 0x48); 314 serigo(GORDON_REG_IVNUM2, 0x50); 315 serigo(GORDON_REG_IHNUM2, 0x3C); 316 mddi_wait(2); 317 serigo(GORDON_REG_POWCTL, 0x03); 318 mddi_wait(15); 319 serigo(GORDON_REG_POWCTL, 0x07); 320 mddi_wait(15); 321 serigo(GORDON_REG_POWCTL, 0x0F); 322 mddi_wait(15); 323 serigo(GORDON_REG_AVCTL, 0x03); 324 mddi_wait(15); 325 serigo(GORDON_REG_POWCTL, 0x1F); 326 mddi_wait(15); 327 serigo(GORDON_REG_POWCTL, 0x5F); 328 mddi_wait(15); 329 serigo(GORDON_REG_POWCTL, 0x7F); 330 mddi_wait(15); 331 serigo(GORDON_REG_LCDIFCTL1, 0x02); 332 mddi_wait(15); 333 serigo(GORDON_REG_IMGCTL1, 0x00); 334 mddi_wait(15); 335 serigo(GORDON_REG_LCDIFCTL3, 0x00); 336 mddi_wait(15); 337 serigo(GORDON_REG_VALTRAN, 0x01); 338 mddi_wait(15); 339 serigo(GORDON_REG_LCDIFCTL1, 0x03); 340 serigo(GORDON_REG_LCDIFCTL1, 0x03); 341 mddi_wait(1); 342} 343 344void gordon_disp_off(void) 345{ 346 serigo(GORDON_REG_LCDIFCTL2, 0x7B); 347 serigo(GORDON_REG_VALTRAN, 0x01); 348 serigo(GORDON_REG_LCDIFCTL1, 0x02); 349 serigo(GORDON_REG_LCDIFCTL3, 0x01); 350 mddi_wait(20); 351 serigo(GORDON_REG_VALTRAN, 0x01); 352 serigo(GORDON_REG_IMGCTL1, 0x01); 353 serigo(GORDON_REG_LCDIFCTL1, 0x00); 354 mddi_wait(20); 355 serigo(GORDON_REG_POWCTL, 0x1F); 356 mddi_wait(40); 357 serigo(GORDON_REG_POWCTL, 0x07); 358 mddi_wait(40); 359 serigo(GORDON_REG_POWCTL, 0x03); 360 mddi_wait(40); 361 serigo(GORDON_REG_POWCTL, 0x00); 362 mddi_wait(40); 363} 364 365void gordon_disp_init(void) 366{ 367 gordon_init(); 368 mddi_wait(20); 369 gordon_disp_on(); 370} 371 372static void toshiba_common_initial_setup(struct msm_fb_data_type *mfd) 373{ 374 if (TM_GET_PID(mfd->panel.id) == LCD_TOSHIBA_2P4_WVGA_PT) { 375 write_client_reg(DPSET0 , 0x4bec0066, TRUE); 376 write_client_reg(DPSET1 , 0x00000113, TRUE); 377 write_client_reg(DPSUS , 0x00000000, TRUE); 378 write_client_reg(DPRUN , 0x00000001, TRUE); 379 mddi_wait(5); 380 write_client_reg(SYSCKENA , 0x00000001, TRUE); 381 write_client_reg(CLKENB , 0x0000a0e9, TRUE); 382 383 write_client_reg(GPIODATA , 0x03FF0000, TRUE); 384 write_client_reg(GPIODIR , 0x0000024D, TRUE); 385 write_client_reg(GPIOSEL , 0x00000173, TRUE); 386 write_client_reg(GPIOPC , 0x03C300C0, TRUE); 387 write_client_reg(WKREQ , 0x00000000, TRUE); 388 write_client_reg(GPIOIS , 0x00000000, TRUE); 389 write_client_reg(GPIOIEV , 0x00000001, TRUE); 390 write_client_reg(GPIOIC , 0x000003FF, TRUE); 391 write_client_reg(GPIODATA , 0x00040004, TRUE); 392 393 write_client_reg(GPIODATA , 0x00080008, TRUE); 394 write_client_reg(DRAMPWR , 0x00000001, TRUE); 395 write_client_reg(CLKENB , 0x0000a0eb, TRUE); 396 write_client_reg(PWMCR , 0x00000000, TRUE); 397 mddi_wait(1); 398 399 write_client_reg(SSICTL , 0x00060399, TRUE); 400 write_client_reg(SSITIME , 0x00000100, TRUE); 401 write_client_reg(CNT_DIS , 0x00000002, TRUE); 402 write_client_reg(SSICTL , 0x0006039b, TRUE); 403 404 write_client_reg(SSITX , 0x00000000, TRUE); 405 mddi_wait(7); 406 write_client_reg(SSITX , 0x00000000, TRUE); 407 mddi_wait(7); 408 write_client_reg(SSITX , 0x00000000, TRUE); 409 mddi_wait(7); 410 411 write_client_reg(SSITX , 0x000800BA, TRUE); 412 write_client_reg(SSITX , 0x00000111, TRUE); 413 write_client_reg(SSITX , 0x00080036, TRUE); 414 write_client_reg(SSITX , 0x00000100, TRUE); 415 mddi_wait(1); 416 write_client_reg(SSITX , 0x0008003A, TRUE); 417 write_client_reg(SSITX , 0x00000160, TRUE); 418 write_client_reg(SSITX , 0x000800B1, TRUE); 419 write_client_reg(SSITX , 0x0000015D, TRUE); 420 mddi_wait(1); 421 write_client_reg(SSITX , 0x000800B2, TRUE); 422 write_client_reg(SSITX , 0x00000133, TRUE); 423 write_client_reg(SSITX , 0x000800B3, TRUE); 424 write_client_reg(SSITX , 0x00000122, TRUE); 425 mddi_wait(1); 426 write_client_reg(SSITX , 0x000800B4, TRUE); 427 write_client_reg(SSITX , 0x00000102, TRUE); 428 write_client_reg(SSITX , 0x000800B5, TRUE); 429 write_client_reg(SSITX , 0x0000011E, TRUE); 430 mddi_wait(1); 431 write_client_reg(SSITX , 0x000800B6, TRUE); 432 write_client_reg(SSITX , 0x00000127, TRUE); 433 write_client_reg(SSITX , 0x000800B7, TRUE); 434 write_client_reg(SSITX , 0x00000103, TRUE); 435 mddi_wait(1); 436 write_client_reg(SSITX , 0x000800B9, TRUE); 437 write_client_reg(SSITX , 0x00000124, TRUE); 438 write_client_reg(SSITX , 0x000800BD, TRUE); 439 write_client_reg(SSITX , 0x000001A1, TRUE); 440 mddi_wait(1); 441 write_client_reg(SSITX , 0x000800BB, TRUE); 442 write_client_reg(SSITX , 0x00000100, TRUE); 443 write_client_reg(SSITX , 0x000800BF, TRUE); 444 write_client_reg(SSITX , 0x00000101, TRUE); 445 mddi_wait(1); 446 write_client_reg(SSITX , 0x000800BE, TRUE); 447 write_client_reg(SSITX , 0x00000100, TRUE); 448 write_client_reg(SSITX , 0x000800C0, TRUE); 449 write_client_reg(SSITX , 0x00000111, TRUE); 450 mddi_wait(1); 451 write_client_reg(SSITX , 0x000800C1, TRUE); 452 write_client_reg(SSITX , 0x00000111, TRUE); 453 write_client_reg(SSITX , 0x000800C2, TRUE); 454 write_client_reg(SSITX , 0x00000111, TRUE); 455 mddi_wait(1); 456 write_client_reg(SSITX , 0x000800C3, TRUE); 457 write_client_reg(SSITX , 0x00080132, TRUE); 458 write_client_reg(SSITX , 0x00000132, TRUE); 459 mddi_wait(1); 460 write_client_reg(SSITX , 0x000800C4, TRUE); 461 write_client_reg(SSITX , 0x00080132, TRUE); 462 write_client_reg(SSITX , 0x00000132, TRUE); 463 mddi_wait(1); 464 write_client_reg(SSITX , 0x000800C5, TRUE); 465 write_client_reg(SSITX , 0x00080132, TRUE); 466 write_client_reg(SSITX , 0x00000132, TRUE); 467 mddi_wait(1); 468 write_client_reg(SSITX , 0x000800C6, TRUE); 469 write_client_reg(SSITX , 0x00080132, TRUE); 470 write_client_reg(SSITX , 0x00000132, TRUE); 471 mddi_wait(1); 472 write_client_reg(SSITX , 0x000800C7, TRUE); 473 write_client_reg(SSITX , 0x00080164, TRUE); 474 write_client_reg(SSITX , 0x00000145, TRUE); 475 mddi_wait(1); 476 write_client_reg(SSITX , 0x000800C8, TRUE); 477 write_client_reg(SSITX , 0x00000144, TRUE); 478 write_client_reg(SSITX , 0x000800C9, TRUE); 479 write_client_reg(SSITX , 0x00000152, TRUE); 480 mddi_wait(1); 481 write_client_reg(SSITX , 0x000800CA, TRUE); 482 write_client_reg(SSITX , 0x00000100, TRUE); 483 mddi_wait(1); 484 write_client_reg(SSITX , 0x000800EC, TRUE); 485 write_client_reg(SSITX , 0x00080101, TRUE); 486 write_client_reg(SSITX , 0x000001FC, TRUE); 487 mddi_wait(1); 488 write_client_reg(SSITX , 0x000800CF, TRUE); 489 write_client_reg(SSITX , 0x00000101, TRUE); 490 mddi_wait(1); 491 write_client_reg(SSITX , 0x000800D0, TRUE); 492 write_client_reg(SSITX , 0x00080110, TRUE); 493 write_client_reg(SSITX , 0x00000104, TRUE); 494 mddi_wait(1); 495 write_client_reg(SSITX , 0x000800D1, TRUE); 496 write_client_reg(SSITX , 0x00000101, TRUE); 497 mddi_wait(1); 498 write_client_reg(SSITX , 0x000800D2, TRUE); 499 write_client_reg(SSITX , 0x00080100, TRUE); 500 write_client_reg(SSITX , 0x00000128, TRUE); 501 mddi_wait(1); 502 write_client_reg(SSITX , 0x000800D3, TRUE); 503 write_client_reg(SSITX , 0x00080100, TRUE); 504 write_client_reg(SSITX , 0x00000128, TRUE); 505 mddi_wait(1); 506 write_client_reg(SSITX , 0x000800D4, TRUE); 507 write_client_reg(SSITX , 0x00080126, TRUE); 508 write_client_reg(SSITX , 0x000001A4, TRUE); 509 mddi_wait(1); 510 write_client_reg(SSITX , 0x000800D5, TRUE); 511 write_client_reg(SSITX , 0x00000120, TRUE); 512 mddi_wait(1); 513 write_client_reg(SSITX , 0x000800EF, TRUE); 514 write_client_reg(SSITX , 0x00080132, TRUE); 515 write_client_reg(SSITX , 0x00000100, TRUE); 516 mddi_wait(1); 517 518 write_client_reg(BITMAP0 , 0x032001E0, TRUE); 519 write_client_reg(BITMAP1 , 0x032001E0, TRUE); 520 write_client_reg(BITMAP2 , 0x014000F0, TRUE); 521 write_client_reg(BITMAP3 , 0x014000F0, TRUE); 522 write_client_reg(BITMAP4 , 0x014000F0, TRUE); 523 write_client_reg(CLKENB , 0x0000A1EB, TRUE); 524 write_client_reg(PORT_ENB , 0x00000001, TRUE); 525 write_client_reg(PORT , 0x00000004, TRUE); 526 write_client_reg(PXL , 0x00000002, TRUE); 527 write_client_reg(MPLFBUF , 0x00000000, TRUE); 528 write_client_reg(HCYCLE , 0x000000FD, TRUE); 529 write_client_reg(HSW , 0x00000003, TRUE); 530 write_client_reg(HDE_START , 0x00000007, TRUE); 531 write_client_reg(HDE_SIZE , 0x000000EF, TRUE); 532 write_client_reg(VCYCLE , 0x00000325, TRUE); 533 write_client_reg(VSW , 0x00000001, TRUE); 534 write_client_reg(VDE_START , 0x00000003, TRUE); 535 write_client_reg(VDE_SIZE , 0x0000031F, TRUE); 536 write_client_reg(START , 0x00000001, TRUE); 537 mddi_wait(32); 538 write_client_reg(SSITX , 0x000800BC, TRUE); 539 write_client_reg(SSITX , 0x00000180, TRUE); 540 write_client_reg(SSITX , 0x0008003B, TRUE); 541 write_client_reg(SSITX , 0x00000100, TRUE); 542 mddi_wait(1); 543 write_client_reg(SSITX , 0x000800B0, TRUE); 544 write_client_reg(SSITX , 0x00000116, TRUE); 545 mddi_wait(1); 546 write_client_reg(SSITX , 0x000800B8, TRUE); 547 write_client_reg(SSITX , 0x000801FF, TRUE); 548 write_client_reg(SSITX , 0x000001F5, TRUE); 549 mddi_wait(1); 550 write_client_reg(SSITX , 0x00000011, TRUE); 551 mddi_wait(5); 552 write_client_reg(SSITX , 0x00000029, TRUE); 553 return; 554 } 555 556 if (TM_GET_PID(mfd->panel.id) == LCD_SHARP_2P4_VGA) { 557 write_client_reg(DPSET0, 0x4BEC0066, TRUE); 558 write_client_reg(DPSET1, 0x00000113, TRUE); 559 write_client_reg(DPSUS, 0x00000000, TRUE); 560 write_client_reg(DPRUN, 0x00000001, TRUE); 561 mddi_wait(14); 562 write_client_reg(SYSCKENA, 0x00000001, TRUE); 563 write_client_reg(CLKENB, 0x000000EF, TRUE); 564 write_client_reg(GPIO_BLOCK_BASE, 0x03FF0000, TRUE); 565 write_client_reg(GPIODIR, 0x0000024D, TRUE); 566 write_client_reg(SYSTEM_BLOCK2_BASE, 0x00000173, TRUE); 567 write_client_reg(GPIOPC, 0x03C300C0, TRUE); 568 write_client_reg(SYSTEM_BLOCK1_BASE, 0x00000000, TRUE); 569 write_client_reg(GPIOIS, 0x00000000, TRUE); 570 write_client_reg(GPIOIEV, 0x00000001, TRUE); 571 write_client_reg(GPIOIC, 0x000003FF, TRUE); 572 write_client_reg(GPIO_BLOCK_BASE, 0x00060006, TRUE); 573 write_client_reg(GPIO_BLOCK_BASE, 0x00080008, TRUE); 574 write_client_reg(GPIO_BLOCK_BASE, 0x02000200, TRUE); 575 write_client_reg(DRAMPWR, 0x00000001, TRUE); 576 write_client_reg(TIMER0CTRL, 0x00000060, TRUE); 577 write_client_reg(PWM_BLOCK_BASE, 0x00001388, TRUE); 578 write_client_reg(PWM0OFF, 0x00001387, TRUE); 579 write_client_reg(TIMER1CTRL, 0x00000060, TRUE); 580 write_client_reg(TIMER1LOAD, 0x00001388, TRUE); 581 write_client_reg(PWM1OFF, 0x00001387, TRUE); 582 write_client_reg(TIMER0CTRL, 0x000000E0, TRUE); 583 write_client_reg(TIMER1CTRL, 0x000000E0, TRUE); 584 write_client_reg(PWMCR, 0x00000003, TRUE); 585 mddi_wait(1); 586 write_client_reg(SPI_BLOCK_BASE, 0x00063111, TRUE); 587 write_client_reg(SSITIME, 0x00000100, TRUE); 588 write_client_reg(SPI_BLOCK_BASE, 0x00063113, TRUE); 589 mddi_wait(1); 590 write_client_reg(SSITX, 0x00000000, TRUE); 591 mddi_wait(1); 592 write_client_reg(SSITX, 0x00000000, TRUE); 593 mddi_wait(1); 594 write_client_reg(SSITX, 0x00000000, TRUE); 595 mddi_wait(1); 596 write_client_reg(CLKENB, 0x0000A1EF, TRUE); 597 write_client_reg(START, 0x00000000, TRUE); 598 write_client_reg(WRSTB, 0x0000003F, TRUE); 599 write_client_reg(RDSTB, 0x00000432, TRUE); 600 write_client_reg(PORT_ENB, 0x00000002, TRUE); 601 write_client_reg(VSYNIF, 0x00000000, TRUE); 602 write_client_reg(ASY_DATA, 0x80000000, TRUE); 603 write_client_reg(ASY_DATB, 0x00000001, TRUE); 604 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 605 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 606 mddi_wait(10); 607 write_client_reg(ASY_DATA, 0x80000000, TRUE); 608 write_client_reg(ASY_DATB, 0x80000000, TRUE); 609 write_client_reg(ASY_DATC, 0x80000000, TRUE); 610 write_client_reg(ASY_DATD, 0x80000000, TRUE); 611 write_client_reg(ASY_CMDSET, 0x00000009, TRUE); 612 write_client_reg(ASY_CMDSET, 0x00000008, TRUE); 613 write_client_reg(ASY_DATA, 0x80000007, TRUE); 614 write_client_reg(ASY_DATB, 0x00004005, TRUE); 615 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 616 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 617 mddi_wait(20); 618 write_client_reg(ASY_DATA, 0x80000059, TRUE); 619 write_client_reg(ASY_DATB, 0x00000000, TRUE); 620 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 621 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 622 623 write_client_reg(VSYNIF, 0x00000001, TRUE); 624 write_client_reg(PORT_ENB, 0x00000001, TRUE); 625 } else { 626 write_client_reg(DPSET0, 0x4BEC0066, TRUE); 627 write_client_reg(DPSET1, 0x00000113, TRUE); 628 write_client_reg(DPSUS, 0x00000000, TRUE); 629 write_client_reg(DPRUN, 0x00000001, TRUE); 630 mddi_wait(14); 631 write_client_reg(SYSCKENA, 0x00000001, TRUE); 632 write_client_reg(CLKENB, 0x000000EF, TRUE); 633 write_client_reg(GPIODATA, 0x03FF0000, TRUE); 634 write_client_reg(GPIODIR, 0x0000024D, TRUE); 635 write_client_reg(GPIOSEL, 0x00000173, TRUE); 636 write_client_reg(GPIOPC, 0x03C300C0, TRUE); 637 write_client_reg(WKREQ, 0x00000000, TRUE); 638 write_client_reg(GPIOIS, 0x00000000, TRUE); 639 write_client_reg(GPIOIEV, 0x00000001, TRUE); 640 write_client_reg(GPIOIC, 0x000003FF, TRUE); 641 write_client_reg(GPIODATA, 0x00060006, TRUE); 642 write_client_reg(GPIODATA, 0x00080008, TRUE); 643 write_client_reg(GPIODATA, 0x02000200, TRUE); 644 645 if (TM_GET_PID(mfd->panel.id) == LCD_TOSHIBA_2P4_WVGA) { 646 mddi_wait(400); 647 write_client_reg(DRAMPWR, 0x00000001, TRUE); 648 649 write_client_reg(CNT_DIS, 0x00000002, TRUE); 650 write_client_reg(BITMAP0, 0x01E00320, TRUE); 651 write_client_reg(PORT_ENB, 0x00000001, TRUE); 652 write_client_reg(PORT, 0x00000004, TRUE); 653 write_client_reg(PXL, 0x0000003A, TRUE); 654 write_client_reg(MPLFBUF, 0x00000000, TRUE); 655 write_client_reg(HCYCLE, 0x00000253, TRUE); 656 write_client_reg(HSW, 0x00000003, TRUE); 657 write_client_reg(HDE_START, 0x00000017, TRUE); 658 write_client_reg(HDE_SIZE, 0x0000018F, TRUE); 659 write_client_reg(VCYCLE, 0x000001FF, TRUE); 660 write_client_reg(VSW, 0x00000001, TRUE); 661 write_client_reg(VDE_START, 0x00000003, TRUE); 662 write_client_reg(VDE_SIZE, 0x000001DF, TRUE); 663 write_client_reg(START, 0x00000001, TRUE); 664 mddi_wait(1); 665 write_client_reg(TIMER0CTRL, 0x00000060, TRUE); 666 write_client_reg(TIMER0LOAD, 0x00001388, TRUE); 667 write_client_reg(TIMER1CTRL, 0x00000060, TRUE); 668 write_client_reg(TIMER1LOAD, 0x00001388, TRUE); 669 write_client_reg(PWM1OFF, 0x00000087, TRUE); 670 } else { 671 write_client_reg(DRAMPWR, 0x00000001, TRUE); 672 write_client_reg(TIMER0CTRL, 0x00000060, TRUE); 673 write_client_reg(TIMER0LOAD, 0x00001388, TRUE); 674 write_client_reg(TIMER1CTRL, 0x00000060, TRUE); 675 write_client_reg(TIMER1LOAD, 0x00001388, TRUE); 676 write_client_reg(PWM1OFF, 0x00001387, TRUE); 677 } 678 679 write_client_reg(TIMER0CTRL, 0x000000E0, TRUE); 680 write_client_reg(TIMER1CTRL, 0x000000E0, TRUE); 681 write_client_reg(PWMCR, 0x00000003, TRUE); 682 mddi_wait(1); 683 write_client_reg(SSICTL, 0x00000799, TRUE); 684 write_client_reg(SSITIME, 0x00000100, TRUE); 685 write_client_reg(SSICTL, 0x0000079b, TRUE); 686 write_client_reg(SSITX, 0x00000000, TRUE); 687 mddi_wait(1); 688 write_client_reg(SSITX, 0x00000000, TRUE); 689 mddi_wait(1); 690 write_client_reg(SSITX, 0x00000000, TRUE); 691 mddi_wait(1); 692 write_client_reg(SSITX, 0x000800BA, TRUE); 693 write_client_reg(SSITX, 0x00000111, TRUE); 694 write_client_reg(SSITX, 0x00080036, TRUE); 695 write_client_reg(SSITX, 0x00000100, TRUE); 696 mddi_wait(2); 697 write_client_reg(SSITX, 0x000800BB, TRUE); 698 write_client_reg(SSITX, 0x00000100, TRUE); 699 write_client_reg(SSITX, 0x0008003A, TRUE); 700 write_client_reg(SSITX, 0x00000160, TRUE); 701 mddi_wait(2); 702 write_client_reg(SSITX, 0x000800BF, TRUE); 703 write_client_reg(SSITX, 0x00000100, TRUE); 704 write_client_reg(SSITX, 0x000800B1, TRUE); 705 write_client_reg(SSITX, 0x0000015D, TRUE); 706 mddi_wait(2); 707 write_client_reg(SSITX, 0x000800B2, TRUE); 708 write_client_reg(SSITX, 0x00000133, TRUE); 709 write_client_reg(SSITX, 0x000800B3, TRUE); 710 write_client_reg(SSITX, 0x00000122, TRUE); 711 mddi_wait(2); 712 write_client_reg(SSITX, 0x000800B4, TRUE); 713 write_client_reg(SSITX, 0x00000102, TRUE); 714 write_client_reg(SSITX, 0x000800B5, TRUE); 715 write_client_reg(SSITX, 0x0000011F, TRUE); 716 mddi_wait(2); 717 write_client_reg(SSITX, 0x000800B6, TRUE); 718 write_client_reg(SSITX, 0x00000128, TRUE); 719 write_client_reg(SSITX, 0x000800B7, TRUE); 720 write_client_reg(SSITX, 0x00000103, TRUE); 721 mddi_wait(2); 722 write_client_reg(SSITX, 0x000800B9, TRUE); 723 write_client_reg(SSITX, 0x00000120, TRUE); 724 write_client_reg(SSITX, 0x000800BD, TRUE); 725 write_client_reg(SSITX, 0x00000102, TRUE); 726 mddi_wait(2); 727 write_client_reg(SSITX, 0x000800BE, TRUE); 728 write_client_reg(SSITX, 0x00000100, TRUE); 729 write_client_reg(SSITX, 0x000800C0, TRUE); 730 write_client_reg(SSITX, 0x00000111, TRUE); 731 mddi_wait(2); 732 write_client_reg(SSITX, 0x000800C1, TRUE); 733 write_client_reg(SSITX, 0x00000111, TRUE); 734 write_client_reg(SSITX, 0x000800C2, TRUE); 735 write_client_reg(SSITX, 0x00000111, TRUE); 736 mddi_wait(2); 737 write_client_reg(SSITX, 0x000800C3, TRUE); 738 write_client_reg(SSITX, 0x0008010A, TRUE); 739 write_client_reg(SSITX, 0x0000010A, TRUE); 740 mddi_wait(2); 741 write_client_reg(SSITX, 0x000800C4, TRUE); 742 write_client_reg(SSITX, 0x00080160, TRUE); 743 write_client_reg(SSITX, 0x00000160, TRUE); 744 mddi_wait(2); 745 write_client_reg(SSITX, 0x000800C5, TRUE); 746 write_client_reg(SSITX, 0x00080160, TRUE); 747 write_client_reg(SSITX, 0x00000160, TRUE); 748 mddi_wait(2); 749 write_client_reg(SSITX, 0x000800C6, TRUE); 750 write_client_reg(SSITX, 0x00080160, TRUE); 751 write_client_reg(SSITX, 0x00000160, TRUE); 752 mddi_wait(2); 753 write_client_reg(SSITX, 0x000800C7, TRUE); 754 write_client_reg(SSITX, 0x00080133, TRUE); 755 write_client_reg(SSITX, 0x00000143, TRUE); 756 mddi_wait(2); 757 write_client_reg(SSITX, 0x000800C8, TRUE); 758 write_client_reg(SSITX, 0x00000144, TRUE); 759 write_client_reg(SSITX, 0x000800C9, TRUE); 760 write_client_reg(SSITX, 0x00000133, TRUE); 761 mddi_wait(2); 762 write_client_reg(SSITX, 0x000800CA, TRUE); 763 write_client_reg(SSITX, 0x00000100, TRUE); 764 mddi_wait(2); 765 write_client_reg(SSITX, 0x000800EC, TRUE); 766 write_client_reg(SSITX, 0x00080102, TRUE); 767 write_client_reg(SSITX, 0x00000118, TRUE); 768 mddi_wait(2); 769 write_client_reg(SSITX, 0x000800CF, TRUE); 770 write_client_reg(SSITX, 0x00000101, TRUE); 771 mddi_wait(2); 772 write_client_reg(SSITX, 0x000800D0, TRUE); 773 write_client_reg(SSITX, 0x00080110, TRUE); 774 write_client_reg(SSITX, 0x00000104, TRUE); 775 mddi_wait(2); 776 write_client_reg(SSITX, 0x000800D1, TRUE); 777 write_client_reg(SSITX, 0x00000101, TRUE); 778 mddi_wait(2); 779 write_client_reg(SSITX, 0x000800D2, TRUE); 780 write_client_reg(SSITX, 0x00080100, TRUE); 781 write_client_reg(SSITX, 0x0000013A, TRUE); 782 mddi_wait(2); 783 write_client_reg(SSITX, 0x000800D3, TRUE); 784 write_client_reg(SSITX, 0x00080100, TRUE); 785 write_client_reg(SSITX, 0x0000013A, TRUE); 786 mddi_wait(2); 787 write_client_reg(SSITX, 0x000800D4, TRUE); 788 write_client_reg(SSITX, 0x00080124, TRUE); 789 write_client_reg(SSITX, 0x0000016E, TRUE); 790 mddi_wait(1); 791 write_client_reg(SSITX, 0x000800D5, TRUE); 792 write_client_reg(SSITX, 0x00000124, TRUE); 793 mddi_wait(2); 794 write_client_reg(SSITX, 0x000800ED, TRUE); 795 write_client_reg(SSITX, 0x00080101, TRUE); 796 write_client_reg(SSITX, 0x0000010A, TRUE); 797 mddi_wait(2); 798 write_client_reg(SSITX, 0x000800D6, TRUE); 799 write_client_reg(SSITX, 0x00000101, TRUE); 800 mddi_wait(2); 801 write_client_reg(SSITX, 0x000800D7, TRUE); 802 write_client_reg(SSITX, 0x00080110, TRUE); 803 write_client_reg(SSITX, 0x0000010A, TRUE); 804 mddi_wait(2); 805 write_client_reg(SSITX, 0x000800D8, TRUE); 806 write_client_reg(SSITX, 0x00000101, TRUE); 807 mddi_wait(2); 808 write_client_reg(SSITX, 0x000800D9, TRUE); 809 write_client_reg(SSITX, 0x00080100, TRUE); 810 write_client_reg(SSITX, 0x00000114, TRUE); 811 mddi_wait(2); 812 write_client_reg(SSITX, 0x000800DE, TRUE); 813 write_client_reg(SSITX, 0x00080100, TRUE); 814 write_client_reg(SSITX, 0x00000114, TRUE); 815 mddi_wait(2); 816 write_client_reg(SSITX, 0x000800DF, TRUE); 817 write_client_reg(SSITX, 0x00080112, TRUE); 818 write_client_reg(SSITX, 0x0000013F, TRUE); 819 mddi_wait(2); 820 write_client_reg(SSITX, 0x000800E0, TRUE); 821 write_client_reg(SSITX, 0x0000010B, TRUE); 822 write_client_reg(SSITX, 0x000800E2, TRUE); 823 write_client_reg(SSITX, 0x00000101, TRUE); 824 mddi_wait(2); 825 write_client_reg(SSITX, 0x000800E3, TRUE); 826 write_client_reg(SSITX, 0x00000136, TRUE); 827 mddi_wait(2); 828 write_client_reg(SSITX, 0x000800E4, TRUE); 829 write_client_reg(SSITX, 0x00080100, TRUE); 830 write_client_reg(SSITX, 0x00000103, TRUE); 831 mddi_wait(2); 832 write_client_reg(SSITX, 0x000800E5, TRUE); 833 write_client_reg(SSITX, 0x00080102, TRUE); 834 write_client_reg(SSITX, 0x00000104, TRUE); 835 mddi_wait(2); 836 write_client_reg(SSITX, 0x000800E6, TRUE); 837 write_client_reg(SSITX, 0x00000103, TRUE); 838 mddi_wait(2); 839 write_client_reg(SSITX, 0x000800E7, TRUE); 840 write_client_reg(SSITX, 0x00080104, TRUE); 841 write_client_reg(SSITX, 0x0000010A, TRUE); 842 mddi_wait(2); 843 write_client_reg(SSITX, 0x000800E8, TRUE); 844 write_client_reg(SSITX, 0x00000104, TRUE); 845 write_client_reg(CLKENB, 0x000001EF, TRUE); 846 write_client_reg(START, 0x00000000, TRUE); 847 write_client_reg(WRSTB, 0x0000003F, TRUE); 848 write_client_reg(RDSTB, 0x00000432, TRUE); 849 write_client_reg(PORT_ENB, 0x00000002, TRUE); 850 write_client_reg(VSYNIF, 0x00000000, TRUE); 851 write_client_reg(ASY_DATA, 0x80000000, TRUE); 852 write_client_reg(ASY_DATB, 0x00000001, TRUE); 853 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 854 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 855 mddi_wait(10); 856 write_client_reg(ASY_DATA, 0x80000000, TRUE); 857 write_client_reg(ASY_DATB, 0x80000000, TRUE); 858 write_client_reg(ASY_DATC, 0x80000000, TRUE); 859 write_client_reg(ASY_DATD, 0x80000000, TRUE); 860 write_client_reg(ASY_CMDSET, 0x00000009, TRUE); 861 write_client_reg(ASY_CMDSET, 0x00000008, TRUE); 862 write_client_reg(ASY_DATA, 0x80000007, TRUE); 863 write_client_reg(ASY_DATB, 0x00004005, TRUE); 864 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 865 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 866 mddi_wait(20); 867 write_client_reg(ASY_DATA, 0x80000059, TRUE); 868 write_client_reg(ASY_DATB, 0x00000000, TRUE); 869 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 870 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 871 write_client_reg(VSYNIF, 0x00000001, TRUE); 872 write_client_reg(PORT_ENB, 0x00000001, TRUE); 873 } 874 875 mddi_toshiba_state_transition(TOSHIBA_STATE_PRIM_SEC_STANDBY, 876 TOSHIBA_STATE_PRIM_SEC_READY); 877} 878 879static void toshiba_prim_start(struct msm_fb_data_type *mfd) 880{ 881 if (TM_GET_PID(mfd->panel.id) == LCD_TOSHIBA_2P4_WVGA_PT) 882 return; 883 884 if (TM_GET_PID(mfd->panel.id) == LCD_SHARP_2P4_VGA) { 885 write_client_reg(BITMAP1, 0x01E000F0, TRUE); 886 write_client_reg(BITMAP2, 0x01E000F0, TRUE); 887 write_client_reg(BITMAP3, 0x01E000F0, TRUE); 888 write_client_reg(BITMAP4, 0x00DC00B0, TRUE); 889 write_client_reg(CLKENB, 0x000001EF, TRUE); 890 write_client_reg(PORT_ENB, 0x00000001, TRUE); 891 write_client_reg(PORT, 0x00000016, TRUE); 892 write_client_reg(PXL, 0x00000002, TRUE); 893 write_client_reg(MPLFBUF, 0x00000000, TRUE); 894 write_client_reg(HCYCLE, 0x00000185, TRUE); 895 write_client_reg(HSW, 0x00000018, TRUE); 896 write_client_reg(HDE_START, 0x0000004A, TRUE); 897 write_client_reg(HDE_SIZE, 0x000000EF, TRUE); 898 write_client_reg(VCYCLE, 0x0000028E, TRUE); 899 write_client_reg(VSW, 0x00000004, TRUE); 900 write_client_reg(VDE_START, 0x00000009, TRUE); 901 write_client_reg(VDE_SIZE, 0x0000027F, TRUE); 902 write_client_reg(START, 0x00000001, TRUE); 903 write_client_reg(SYSTEM_BLOCK1_BASE, 0x00000002, TRUE); 904 } else{ 905 906 write_client_reg(VSYNIF, 0x00000001, TRUE); 907 write_client_reg(PORT_ENB, 0x00000001, TRUE); 908 write_client_reg(BITMAP1, 0x01E000F0, TRUE); 909 write_client_reg(BITMAP2, 0x01E000F0, TRUE); 910 write_client_reg(BITMAP3, 0x01E000F0, TRUE); 911 write_client_reg(BITMAP4, 0x00DC00B0, TRUE); 912 write_client_reg(CLKENB, 0x000001EF, TRUE); 913 write_client_reg(PORT_ENB, 0x00000001, TRUE); 914 write_client_reg(PORT, 0x00000004, TRUE); 915 write_client_reg(PXL, 0x00000002, TRUE); 916 write_client_reg(MPLFBUF, 0x00000000, TRUE); 917 918 if (mddi_toshiba_61Hz_refresh) { 919 write_client_reg(HCYCLE, 0x000000FC, TRUE); 920 mddi_toshiba_rows_per_second = 39526; 921 mddi_toshiba_rows_per_refresh = 646; 922 mddi_toshiba_usecs_per_refresh = 16344; 923 } else { 924 write_client_reg(HCYCLE, 0x0000010b, TRUE); 925 mddi_toshiba_rows_per_second = 37313; 926 mddi_toshiba_rows_per_refresh = 646; 927 mddi_toshiba_usecs_per_refresh = 17313; 928 } 929 930 write_client_reg(HSW, 0x00000003, TRUE); 931 write_client_reg(HDE_START, 0x00000007, TRUE); 932 write_client_reg(HDE_SIZE, 0x000000EF, TRUE); 933 write_client_reg(VCYCLE, 0x00000285, TRUE); 934 write_client_reg(VSW, 0x00000001, TRUE); 935 write_client_reg(VDE_START, 0x00000003, TRUE); 936 write_client_reg(VDE_SIZE, 0x0000027F, TRUE); 937 write_client_reg(START, 0x00000001, TRUE); 938 mddi_wait(10); 939 write_client_reg(SSITX, 0x000800BC, TRUE); 940 write_client_reg(SSITX, 0x00000180, TRUE); 941 write_client_reg(SSITX, 0x0008003B, TRUE); 942 write_client_reg(SSITX, 0x00000100, TRUE); 943 mddi_wait(1); 944 write_client_reg(SSITX, 0x000800B0, TRUE); 945 write_client_reg(SSITX, 0x00000116, TRUE); 946 mddi_wait(1); 947 write_client_reg(SSITX, 0x000800B8, TRUE); 948 write_client_reg(SSITX, 0x000801FF, TRUE); 949 write_client_reg(SSITX, 0x000001F5, TRUE); 950 mddi_wait(1); 951 write_client_reg(SSITX, 0x00000011, TRUE); 952 write_client_reg(SSITX, 0x00000029, TRUE); 953 write_client_reg(WKREQ, 0x00000000, TRUE); 954 write_client_reg(WAKEUP, 0x00000000, TRUE); 955 write_client_reg(INTMSK, 0x00000001, TRUE); 956 } 957 958 mddi_toshiba_state_transition(TOSHIBA_STATE_PRIM_SEC_READY, 959 TOSHIBA_STATE_PRIM_NORMAL_MODE); 960} 961 962static void toshiba_sec_start(struct msm_fb_data_type *mfd) 963{ 964 if (TM_GET_PID(mfd->panel.id) == LCD_TOSHIBA_2P4_WVGA_PT) 965 return; 966 967 write_client_reg(VSYNIF, 0x00000000, TRUE); 968 write_client_reg(PORT_ENB, 0x00000002, TRUE); 969 write_client_reg(CLKENB, 0x000011EF, TRUE); 970 write_client_reg(BITMAP0, 0x028001E0, TRUE); 971 write_client_reg(BITMAP1, 0x00000000, TRUE); 972 write_client_reg(BITMAP2, 0x00000000, TRUE); 973 write_client_reg(BITMAP3, 0x00000000, TRUE); 974 write_client_reg(BITMAP4, 0x00DC00B0, TRUE); 975 write_client_reg(PORT, 0x00000000, TRUE); 976 write_client_reg(PXL, 0x00000000, TRUE); 977 write_client_reg(MPLFBUF, 0x00000004, TRUE); 978 write_client_reg(HCYCLE, 0x0000006B, TRUE); 979 write_client_reg(HSW, 0x00000003, TRUE); 980 write_client_reg(HDE_START, 0x00000007, TRUE); 981 write_client_reg(HDE_SIZE, 0x00000057, TRUE); 982 write_client_reg(VCYCLE, 0x000000E6, TRUE); 983 write_client_reg(VSW, 0x00000001, TRUE); 984 write_client_reg(VDE_START, 0x00000003, TRUE); 985 write_client_reg(VDE_SIZE, 0x000000DB, TRUE); 986 write_client_reg(ASY_DATA, 0x80000001, TRUE); 987 write_client_reg(ASY_DATB, 0x0000011B, TRUE); 988 write_client_reg(ASY_DATC, 0x80000002, TRUE); 989 write_client_reg(ASY_DATD, 0x00000700, TRUE); 990 write_client_reg(ASY_DATE, 0x80000003, TRUE); 991 write_client_reg(ASY_DATF, 0x00000230, TRUE); 992 write_client_reg(ASY_DATG, 0x80000008, TRUE); 993 write_client_reg(ASY_DATH, 0x00000402, TRUE); 994 write_client_reg(ASY_CMDSET, 0x00000001, TRUE); 995 write_client_reg(ASY_CMDSET, 0x00000000, TRUE); 996 write_client_reg(ASY_DATA, 0x80000009, TRUE); 997 write_client_reg(ASY_DATB, 0x00000000, TRUE); 998 write_client_reg(ASY_DATC, 0x8000000B, TRUE); 999 write_client_reg(ASY_DATD, 0x00000000, TRUE); 1000 write_client_reg(ASY_DATE, 0x8000000C, TRUE); 1001 write_client_reg(ASY_DATF, 0x00000000, TRUE); 1002 write_client_reg(ASY_DATG, 0x8000000D, TRUE); 1003 write_client_reg(ASY_DATH, 0x00000409, TRUE); 1004 write_client_reg(ASY_CMDSET, 0x00000001, TRUE); 1005 write_client_reg(ASY_CMDSET, 0x00000000, TRUE); 1006 write_client_reg(ASY_DATA, 0x8000000E, TRUE); 1007 write_client_reg(ASY_DATB, 0x00000409, TRUE); 1008 write_client_reg(ASY_DATC, 0x80000030, TRUE); 1009 write_client_reg(ASY_DATD, 0x00000000, TRUE); 1010 write_client_reg(ASY_DATE, 0x80000031, TRUE); 1011 write_client_reg(ASY_DATF, 0x00000100, TRUE); 1012 write_client_reg(ASY_DATG, 0x80000032, TRUE); 1013 write_client_reg(ASY_DATH, 0x00000104, TRUE); 1014 write_client_reg(ASY_CMDSET, 0x00000001, TRUE); 1015 write_client_reg(ASY_CMDSET, 0x00000000, TRUE); 1016 write_client_reg(ASY_DATA, 0x80000033, TRUE); 1017 write_client_reg(ASY_DATB, 0x00000400, TRUE); 1018 write_client_reg(ASY_DATC, 0x80000034, TRUE); 1019 write_client_reg(ASY_DATD, 0x00000306, TRUE); 1020 write_client_reg(ASY_DATE, 0x80000035, TRUE); 1021 write_client_reg(ASY_DATF, 0x00000706, TRUE); 1022 write_client_reg(ASY_DATG, 0x80000036, TRUE); 1023 write_client_reg(ASY_DATH, 0x00000707, TRUE); 1024 write_client_reg(ASY_CMDSET, 0x00000001, TRUE); 1025 write_client_reg(ASY_CMDSET, 0x00000000, TRUE); 1026 write_client_reg(ASY_DATA, 0x80000037, TRUE); 1027 write_client_reg(ASY_DATB, 0x00000004, TRUE); 1028 write_client_reg(ASY_DATC, 0x80000038, TRUE); 1029 write_client_reg(ASY_DATD, 0x00000000, TRUE); 1030 write_client_reg(ASY_DATE, 0x80000039, TRUE); 1031 write_client_reg(ASY_DATF, 0x00000000, TRUE); 1032 write_client_reg(ASY_DATG, 0x8000003A, TRUE); 1033 write_client_reg(ASY_DATH, 0x00000001, TRUE); 1034 write_client_reg(ASY_CMDSET, 0x00000001, TRUE); 1035 write_client_reg(ASY_CMDSET, 0x00000000, TRUE); 1036 write_client_reg(ASY_DATA, 0x80000044, TRUE); 1037 write_client_reg(ASY_DATB, 0x0000AF00, TRUE); 1038 write_client_reg(ASY_DATC, 0x80000045, TRUE); 1039 write_client_reg(ASY_DATD, 0x0000DB00, TRUE); 1040 write_client_reg(ASY_DATE, 0x08000042, TRUE); 1041 write_client_reg(ASY_DATF, 0x0000DB00, TRUE); 1042 write_client_reg(ASY_DATG, 0x80000021, TRUE); 1043 write_client_reg(ASY_DATH, 0x00000000, TRUE); 1044 write_client_reg(ASY_CMDSET, 0x00000001, TRUE); 1045 write_client_reg(ASY_CMDSET, 0x00000000, TRUE); 1046 write_client_reg(PXL, 0x0000000C, TRUE); 1047 write_client_reg(VSYNIF, 0x00000001, TRUE); 1048 write_client_reg(ASY_DATA, 0x80000022, TRUE); 1049 write_client_reg(ASY_CMDSET, 0x00000003, TRUE); 1050 write_client_reg(START, 0x00000001, TRUE); 1051 mddi_wait(60); 1052 write_client_reg(PXL, 0x00000000, TRUE); 1053 write_client_reg(VSYNIF, 0x00000000, TRUE); 1054 write_client_reg(START, 0x00000000, TRUE); 1055 write_client_reg(ASY_CMDSET, 0x00000000, TRUE); 1056 write_client_reg(ASY_DATA, 0x80000050, TRUE); 1057 write_client_reg(ASY_DATB, 0x00000000, TRUE); 1058 write_client_reg(ASY_DATC, 0x80000051, TRUE); 1059 write_client_reg(ASY_DATD, 0x00000E00, TRUE); 1060 write_client_reg(ASY_DATE, 0x80000052, TRUE); 1061 write_client_reg(ASY_DATF, 0x00000D01, TRUE); 1062 write_client_reg(ASY_DATG, 0x80000053, TRUE); 1063 write_client_reg(ASY_DATH, 0x00000000, TRUE); 1064 write_client_reg(ASY_CMDSET, 0x00000001, TRUE); 1065 write_client_reg(ASY_CMDSET, 0x00000000, TRUE); 1066 write_client_reg(ASY_DATA, 0x80000058, TRUE); 1067 write_client_reg(ASY_DATB, 0x00000000, TRUE); 1068 write_client_reg(ASY_DATC, 0x8000005A, TRUE); 1069 write_client_reg(ASY_DATD, 0x00000E01, TRUE); 1070 write_client_reg(ASY_CMDSET, 0x00000009, TRUE); 1071 write_client_reg(ASY_CMDSET, 0x00000008, TRUE); 1072 write_client_reg(ASY_DATA, 0x80000011, TRUE); 1073 write_client_reg(ASY_DATB, 0x00000812, TRUE); 1074 write_client_reg(ASY_DATC, 0x80000012, TRUE); 1075 write_client_reg(ASY_DATD, 0x00000003, TRUE); 1076 write_client_reg(ASY_DATE, 0x80000013, TRUE); 1077 write_client_reg(ASY_DATF, 0x00000909, TRUE); 1078 write_client_reg(ASY_DATG, 0x80000010, TRUE); 1079 write_client_reg(ASY_DATH, 0x00000040, TRUE); 1080 write_client_reg(ASY_CMDSET, 0x00000001, TRUE); 1081 write_client_reg(ASY_CMDSET, 0x00000000, TRUE); 1082 mddi_wait(40); 1083 write_client_reg(ASY_DATA, 0x80000010, TRUE); 1084 write_client_reg(ASY_DATB, 0x00000340, TRUE); 1085 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1086 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1087 mddi_wait(60); 1088 write_client_reg(ASY_DATA, 0x80000010, TRUE); 1089 write_client_reg(ASY_DATB, 0x00003340, TRUE); 1090 write_client_reg(ASY_DATC, 0x80000007, TRUE); 1091 write_client_reg(ASY_DATD, 0x00004007, TRUE); 1092 write_client_reg(ASY_CMDSET, 0x00000009, TRUE); 1093 write_client_reg(ASY_CMDSET, 0x00000008, TRUE); 1094 mddi_wait(1); 1095 write_client_reg(ASY_DATA, 0x80000007, TRUE); 1096 write_client_reg(ASY_DATB, 0x00004017, TRUE); 1097 write_client_reg(ASY_DATC, 0x8000005B, TRUE); 1098 write_client_reg(ASY_DATD, 0x00000000, TRUE); 1099 write_client_reg(ASY_DATE, 0x80000059, TRUE); 1100 write_client_reg(ASY_DATF, 0x00000011, TRUE); 1101 write_client_reg(ASY_CMDSET, 0x0000000D, TRUE); 1102 write_client_reg(ASY_CMDSET, 0x0000000C, TRUE); 1103 mddi_wait(20); 1104 write_client_reg(ASY_DATA, 0x80000059, TRUE); 1105 /* LTPS I/F control */ 1106 write_client_reg(ASY_DATB, 0x00000019, TRUE); 1107 /* Direct cmd transfer enable */ 1108 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1109 /* Direct cmd transfer disable */ 1110 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1111 mddi_wait(20); 1112 /* Index setting of SUB LCDD */ 1113 write_client_reg(ASY_DATA, 0x80000059, TRUE); 1114 /* LTPS I/F control */ 1115 write_client_reg(ASY_DATB, 0x00000079, TRUE); 1116 /* Direct cmd transfer enable */ 1117 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1118 /* Direct cmd transfer disable */ 1119 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1120 mddi_wait(20); 1121 /* Index setting of SUB LCDD */ 1122 write_client_reg(ASY_DATA, 0x80000059, TRUE); 1123 /* LTPS I/F control */ 1124 write_client_reg(ASY_DATB, 0x000003FD, TRUE); 1125 /* Direct cmd transfer enable */ 1126 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1127 /* Direct cmd transfer disable */ 1128 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1129 mddi_wait(20); 1130 mddi_toshiba_state_transition(TOSHIBA_STATE_PRIM_SEC_READY, 1131 TOSHIBA_STATE_SEC_NORMAL_MODE); 1132} 1133 1134static void toshiba_prim_lcd_off(struct msm_fb_data_type *mfd) 1135{ 1136 if (TM_GET_PID(mfd->panel.id) == LCD_SHARP_2P4_VGA) { 1137 gordon_disp_off(); 1138 } else{ 1139 1140 /* Main panel power off (Deep standby in) */ 1141 write_client_reg(SSITX, 0x000800BC, TRUE); 1142 write_client_reg(SSITX, 0x00000100, TRUE); 1143 write_client_reg(SSITX, 0x00000028, TRUE); 1144 mddi_wait(1); 1145 write_client_reg(SSITX, 0x000800B8, TRUE); 1146 write_client_reg(SSITX, 0x00000180, TRUE); 1147 write_client_reg(SSITX, 0x00000102, TRUE); 1148 write_client_reg(SSITX, 0x00000010, TRUE); 1149 } 1150 write_client_reg(PORT, 0x00000003, TRUE); 1151 write_client_reg(REGENB, 0x00000001, TRUE); 1152 mddi_wait(1); 1153 write_client_reg(PXL, 0x00000000, TRUE); 1154 write_client_reg(START, 0x00000000, TRUE); 1155 write_client_reg(REGENB, 0x00000001, TRUE); 1156 mddi_wait(3); 1157 if (TM_GET_PID(mfd->panel.id) != LCD_SHARP_2P4_VGA) { 1158 write_client_reg(SSITX, 0x000800B0, TRUE); 1159 write_client_reg(SSITX, 0x00000100, TRUE); 1160 } 1161 mddi_toshiba_state_transition(TOSHIBA_STATE_PRIM_NORMAL_MODE, 1162 TOSHIBA_STATE_PRIM_SEC_STANDBY); 1163} 1164 1165static void toshiba_sec_lcd_off(struct msm_fb_data_type *mfd) 1166{ 1167 if (TM_GET_PID(mfd->panel.id) == LCD_TOSHIBA_2P4_WVGA_PT) 1168 return; 1169 1170 write_client_reg(VSYNIF, 0x00000000, TRUE); 1171 write_client_reg(PORT_ENB, 0x00000002, TRUE); 1172 write_client_reg(ASY_DATA, 0x80000007, TRUE); 1173 write_client_reg(ASY_DATB, 0x00004016, TRUE); 1174 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1175 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1176 mddi_wait(2); 1177 write_client_reg(ASY_DATA, 0x80000059, TRUE); 1178 write_client_reg(ASY_DATB, 0x00000019, TRUE); 1179 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1180 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1181 mddi_wait(2); 1182 write_client_reg(ASY_DATA, 0x80000059, TRUE); 1183 write_client_reg(ASY_DATB, 0x0000000B, TRUE); 1184 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1185 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1186 mddi_wait(2); 1187 write_client_reg(ASY_DATA, 0x80000059, TRUE); 1188 write_client_reg(ASY_DATB, 0x00000002, TRUE); 1189 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1190 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1191 mddi_wait(4); 1192 write_client_reg(ASY_DATA, 0x80000010, TRUE); 1193 write_client_reg(ASY_DATB, 0x00000300, TRUE); 1194 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1195 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1196 mddi_wait(4); 1197 write_client_reg(ASY_DATA, 0x80000059, TRUE); 1198 write_client_reg(ASY_DATB, 0x00000000, TRUE); 1199 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1200 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1201 mddi_wait(2); 1202 write_client_reg(ASY_DATA, 0x80000007, TRUE); 1203 write_client_reg(ASY_DATB, 0x00004004, TRUE); 1204 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1205 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1206 mddi_wait(2); 1207 write_client_reg(PORT, 0x00000000, TRUE); 1208 write_client_reg(PXL, 0x00000000, TRUE); 1209 write_client_reg(START, 0x00000000, TRUE); 1210 write_client_reg(VSYNIF, 0x00000001, TRUE); 1211 write_client_reg(PORT_ENB, 0x00000001, TRUE); 1212 write_client_reg(REGENB, 0x00000001, TRUE); 1213 mddi_toshiba_state_transition(TOSHIBA_STATE_SEC_NORMAL_MODE, 1214 TOSHIBA_STATE_PRIM_SEC_STANDBY); 1215} 1216 1217static void toshiba_sec_cont_update_start(struct msm_fb_data_type *mfd) 1218{ 1219 1220 if (TM_GET_PID(mfd->panel.id) == LCD_TOSHIBA_2P4_WVGA_PT) 1221 return; 1222 1223 write_client_reg(VSYNIF, 0x00000000, TRUE); 1224 write_client_reg(PORT_ENB, 0x00000002, TRUE); 1225 write_client_reg(INTMASK, 0x00000001, TRUE); 1226 write_client_reg(TTBUSSEL, 0x0000000B, TRUE); 1227 write_client_reg(MONI, 0x00000008, TRUE); 1228 write_client_reg(CLKENB, 0x000000EF, TRUE); 1229 write_client_reg(CLKENB, 0x000010EF, TRUE); 1230 write_client_reg(CLKENB, 0x000011EF, TRUE); 1231 write_client_reg(BITMAP4, 0x00DC00B0, TRUE); 1232 write_client_reg(HCYCLE, 0x0000006B, TRUE); 1233 write_client_reg(HSW, 0x00000003, TRUE); 1234 write_client_reg(HDE_START, 0x00000002, TRUE); 1235 write_client_reg(HDE_SIZE, 0x00000057, TRUE); 1236 write_client_reg(VCYCLE, 0x000000E6, TRUE); 1237 write_client_reg(VSW, 0x00000001, TRUE); 1238 write_client_reg(VDE_START, 0x00000003, TRUE); 1239 write_client_reg(VDE_SIZE, 0x000000DB, TRUE); 1240 write_client_reg(WRSTB, 0x00000015, TRUE); 1241 write_client_reg(MPLFBUF, 0x00000004, TRUE); 1242 write_client_reg(ASY_DATA, 0x80000021, TRUE); 1243 write_client_reg(ASY_DATB, 0x00000000, TRUE); 1244 write_client_reg(ASY_DATC, 0x80000022, TRUE); 1245 write_client_reg(ASY_CMDSET, 0x00000007, TRUE); 1246 write_client_reg(PXL, 0x00000089, TRUE); 1247 write_client_reg(VSYNIF, 0x00000001, TRUE); 1248 mddi_wait(2); 1249} 1250 1251static void toshiba_sec_cont_update_stop(struct msm_fb_data_type *mfd) 1252{ 1253 if (TM_GET_PID(mfd->panel.id) == LCD_TOSHIBA_2P4_WVGA_PT) 1254 return; 1255 1256 write_client_reg(PXL, 0x00000000, TRUE); 1257 write_client_reg(VSYNIF, 0x00000000, TRUE); 1258 write_client_reg(START, 0x00000000, TRUE); 1259 write_client_reg(ASY_CMDSET, 0x00000000, TRUE); 1260 mddi_wait(3); 1261 write_client_reg(SRST, 0x00000002, TRUE); 1262 mddi_wait(3); 1263 write_client_reg(SRST, 0x00000003, TRUE); 1264} 1265 1266static void toshiba_sec_backlight_on(struct msm_fb_data_type *mfd) 1267{ 1268 if (TM_GET_PID(mfd->panel.id) == LCD_TOSHIBA_2P4_WVGA_PT) 1269 return; 1270 1271 write_client_reg(TIMER0CTRL, 0x00000060, TRUE); 1272 write_client_reg(TIMER0LOAD, 0x00001388, TRUE); 1273 write_client_reg(PWM0OFF, 0x00000001, TRUE); 1274 write_client_reg(TIMER1CTRL, 0x00000060, TRUE); 1275 write_client_reg(TIMER1LOAD, 0x00001388, TRUE); 1276 write_client_reg(PWM1OFF, 0x00001387, TRUE); 1277 write_client_reg(TIMER0CTRL, 0x000000E0, TRUE); 1278 write_client_reg(TIMER1CTRL, 0x000000E0, TRUE); 1279 write_client_reg(PWMCR, 0x00000003, TRUE); 1280} 1281 1282static void toshiba_sec_sleep_in(struct msm_fb_data_type *mfd) 1283{ 1284 if (TM_GET_PID(mfd->panel.id) == LCD_TOSHIBA_2P4_WVGA_PT) 1285 return; 1286 1287 write_client_reg(VSYNIF, 0x00000000, TRUE); 1288 write_client_reg(PORT_ENB, 0x00000002, TRUE); 1289 write_client_reg(ASY_DATA, 0x80000007, TRUE); 1290 write_client_reg(ASY_DATB, 0x00004016, TRUE); 1291 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1292 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1293 mddi_wait(2); 1294 write_client_reg(ASY_DATA, 0x80000059, TRUE); 1295 write_client_reg(ASY_DATB, 0x00000019, TRUE); 1296 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1297 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1298 mddi_wait(2); 1299 write_client_reg(ASY_DATA, 0x80000059, TRUE); 1300 write_client_reg(ASY_DATB, 0x0000000B, TRUE); 1301 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1302 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1303 mddi_wait(2); 1304 write_client_reg(ASY_DATA, 0x80000059, TRUE); 1305 write_client_reg(ASY_DATB, 0x00000002, TRUE); 1306 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1307 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1308 mddi_wait(4); 1309 write_client_reg(ASY_DATA, 0x80000010, TRUE); 1310 write_client_reg(ASY_DATB, 0x00000300, TRUE); 1311 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1312 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1313 mddi_wait(4); 1314 write_client_reg(ASY_DATA, 0x80000059, TRUE); 1315 write_client_reg(ASY_DATB, 0x00000000, TRUE); 1316 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1317 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1318 mddi_wait(2); 1319 write_client_reg(ASY_DATA, 0x80000007, TRUE); 1320 write_client_reg(ASY_DATB, 0x00004004, TRUE); 1321 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1322 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1323 mddi_wait(2); 1324 write_client_reg(PORT, 0x00000000, TRUE); 1325 write_client_reg(PXL, 0x00000000, TRUE); 1326 write_client_reg(START, 0x00000000, TRUE); 1327 write_client_reg(REGENB, 0x00000001, TRUE); 1328 /* Sleep in sequence */ 1329 write_client_reg(ASY_DATA, 0x80000010, TRUE); 1330 write_client_reg(ASY_DATB, 0x00000302, TRUE); 1331 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1332 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1333} 1334 1335static void toshiba_sec_sleep_out(struct msm_fb_data_type *mfd) 1336{ 1337 if (TM_GET_PID(mfd->panel.id) == LCD_TOSHIBA_2P4_WVGA_PT) 1338 return; 1339 1340 write_client_reg(VSYNIF, 0x00000000, TRUE); 1341 write_client_reg(PORT_ENB, 0x00000002, TRUE); 1342 write_client_reg(ASY_DATA, 0x80000010, TRUE); 1343 write_client_reg(ASY_DATB, 0x00000300, TRUE); 1344 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1345 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1346 /* Display ON sequence */ 1347 write_client_reg(ASY_DATA, 0x80000011, TRUE); 1348 write_client_reg(ASY_DATB, 0x00000812, TRUE); 1349 write_client_reg(ASY_DATC, 0x80000012, TRUE); 1350 write_client_reg(ASY_DATD, 0x00000003, TRUE); 1351 write_client_reg(ASY_DATE, 0x80000013, TRUE); 1352 write_client_reg(ASY_DATF, 0x00000909, TRUE); 1353 write_client_reg(ASY_DATG, 0x80000010, TRUE); 1354 write_client_reg(ASY_DATH, 0x00000040, TRUE); 1355 write_client_reg(ASY_CMDSET, 0x00000001, TRUE); 1356 write_client_reg(ASY_CMDSET, 0x00000000, TRUE); 1357 mddi_wait(4); 1358 write_client_reg(ASY_DATA, 0x80000010, TRUE); 1359 write_client_reg(ASY_DATB, 0x00000340, TRUE); 1360 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1361 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1362 mddi_wait(6); 1363 write_client_reg(ASY_DATA, 0x80000010, TRUE); 1364 write_client_reg(ASY_DATB, 0x00003340, TRUE); 1365 write_client_reg(ASY_DATC, 0x80000007, TRUE); 1366 write_client_reg(ASY_DATD, 0x00004007, TRUE); 1367 write_client_reg(ASY_CMDSET, 0x00000009, TRUE); 1368 write_client_reg(ASY_CMDSET, 0x00000008, TRUE); 1369 mddi_wait(1); 1370 write_client_reg(ASY_DATA, 0x80000007, TRUE); 1371 write_client_reg(ASY_DATB, 0x00004017, TRUE); 1372 write_client_reg(ASY_DATC, 0x8000005B, TRUE); 1373 write_client_reg(ASY_DATD, 0x00000000, TRUE); 1374 write_client_reg(ASY_DATE, 0x80000059, TRUE); 1375 write_client_reg(ASY_DATF, 0x00000011, TRUE); 1376 write_client_reg(ASY_CMDSET, 0x0000000D, TRUE); 1377 write_client_reg(ASY_CMDSET, 0x0000000C, TRUE); 1378 mddi_wait(2); 1379 write_client_reg(ASY_DATA, 0x80000059, TRUE); 1380 write_client_reg(ASY_DATB, 0x00000019, TRUE); 1381 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1382 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1383 mddi_wait(2); 1384 write_client_reg(ASY_DATA, 0x80000059, TRUE); 1385 write_client_reg(ASY_DATB, 0x00000079, TRUE); 1386 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1387 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1388 mddi_wait(2); 1389 write_client_reg(ASY_DATA, 0x80000059, TRUE); 1390 write_client_reg(ASY_DATB, 0x000003FD, TRUE); 1391 write_client_reg(ASY_CMDSET, 0x00000005, TRUE); 1392 write_client_reg(ASY_CMDSET, 0x00000004, TRUE); 1393 mddi_wait(2); 1394} 1395 1396static void mddi_toshiba_lcd_set_backlight(struct msm_fb_data_type *mfd) 1397{ 1398 int32 level; 1399 int ret = -EPERM; 1400 int max = mfd->panel_info.bl_max; 1401 int min = mfd->panel_info.bl_min; 1402 1403 if (mddi_toshiba_pdata && mddi_toshiba_pdata->pmic_backlight) { 1404 ret = mddi_toshiba_pdata->pmic_backlight(mfd->bl_level); 1405 if (!ret) 1406 return; 1407 } 1408 1409 if (ret && mddi_toshiba_pdata && mddi_toshiba_pdata->backlight_level) { 1410 level = mddi_toshiba_pdata->backlight_level(mfd->bl_level, 1411 max, min); 1412 1413 if (level < 0) 1414 return; 1415 1416 if (TM_GET_PID(mfd->panel.id) == LCD_SHARP_2P4_VGA) 1417 write_client_reg(TIMER0LOAD, 0x00001388, TRUE); 1418 } else { 1419 if (!max) 1420 level = 0; 1421 else 1422 level = (mfd->bl_level * 4999) / max; 1423 } 1424 1425 write_client_reg(PWM0OFF, level, TRUE); 1426} 1427 1428static void mddi_toshiba_vsync_set_handler(msm_fb_vsync_handler_type handler, /* ISR to be executed */ 1429 void *arg) 1430{ 1431 boolean error = FALSE; 1432 unsigned long flags; 1433 1434 /* Disable interrupts */ 1435 spin_lock_irqsave(&mddi_host_spin_lock, flags); 1436 /* INTLOCK(); */ 1437 1438 if (mddi_toshiba_vsync_handler != NULL) { 1439 error = TRUE; 1440 } else { 1441 /* Register the handler for this particular GROUP interrupt source */ 1442 mddi_toshiba_vsync_handler = handler; 1443 mddi_toshiba_vsync_handler_arg = arg; 1444 } 1445 1446 /* Restore interrupts */ 1447 spin_unlock_irqrestore(&mddi_host_spin_lock, flags); 1448 /* MDDI_INTFREE(); */ 1449 if (error) { 1450 MDDI_MSG_ERR("MDDI: Previous Vsync handler never called\n"); 1451 } else { 1452 /* Enable the vsync wakeup */ 1453 mddi_queue_register_write(INTMSK, 0x0000, FALSE, 0); 1454 1455 mddi_toshiba_vsync_attempts = 1; 1456 mddi_vsync_detect_enabled = TRUE; 1457 } 1458} /* mddi_toshiba_vsync_set_handler */ 1459 1460static void mddi_toshiba_lcd_vsync_detected(boolean detected) 1461{ 1462 /* static timetick_type start_time = 0; */ 1463 static struct timeval start_time; 1464 static boolean first_time = TRUE; 1465 /* uint32 mdp_cnt_val = 0; */ 1466 /* timetick_type elapsed_us; */ 1467 struct timeval now; 1468 uint32 elapsed_us; 1469 uint32 num_vsyncs; 1470 1471 if ((detected) || (mddi_toshiba_vsync_attempts > 5)) { 1472 if ((detected) && (mddi_toshiba_monitor_refresh_value)) { 1473 /* if (start_time != 0) */ 1474 if (!first_time) { 1475 jiffies_to_timeval(jiffies, &now); 1476 elapsed_us = 1477 (now.tv_sec - start_time.tv_sec) * 1000000 + 1478 now.tv_usec - start_time.tv_usec; 1479 /* 1480 * LCD is configured for a refresh every usecs, 1481 * so to determine the number of vsyncs that 1482 * have occurred since the last measurement 1483 * add half that to the time difference and 1484 * divide by the refresh rate. 1485 */ 1486 num_vsyncs = (elapsed_us + 1487 (mddi_toshiba_usecs_per_refresh >> 1488 1)) / 1489 mddi_toshiba_usecs_per_refresh; 1490 /* 1491 * LCD is configured for * hsyncs (rows) per 1492 * refresh cycle. Calculate new rows_per_second 1493 * value based upon these new measurements. 1494 * MDP can update with this new value. 1495 */ 1496 mddi_toshiba_rows_per_second = 1497 (mddi_toshiba_rows_per_refresh * 1000 * 1498 num_vsyncs) / (elapsed_us / 1000); 1499 } 1500 /* start_time = timetick_get(); */ 1501 first_time = FALSE; 1502 jiffies_to_timeval(jiffies, &start_time); 1503 if (mddi_toshiba_report_refresh_measurements) { 1504 (void)mddi_queue_register_read_int(VPOS, 1505 &mddi_toshiba_curr_vpos); 1506 /* mdp_cnt_val = MDP_LINE_COUNT; */ 1507 } 1508 } 1509 /* if detected = TRUE, client initiated wakeup was detected */ 1510 if (mddi_toshiba_vsync_handler != NULL) { 1511 (*mddi_toshiba_vsync_handler) 1512 (mddi_toshiba_vsync_handler_arg); 1513 mddi_toshiba_vsync_handler = NULL; 1514 } 1515 mddi_vsync_detect_enabled = FALSE; 1516 mddi_toshiba_vsync_attempts = 0; 1517 /* need to disable the interrupt wakeup */ 1518 if (!mddi_queue_register_write_int(INTMSK, 0x0001)) 1519 MDDI_MSG_ERR("Vsync interrupt disable failed!\n"); 1520 if (!detected) { 1521 /* give up after 5 failed attempts but show error */ 1522 MDDI_MSG_NOTICE("Vsync detection failed!\n"); 1523 } else if ((mddi_toshiba_monitor_refresh_value) && 1524 (mddi_toshiba_report_refresh_measurements)) { 1525 MDDI_MSG_NOTICE(" Last Line Counter=%d!\n", 1526 mddi_toshiba_curr_vpos); 1527 /* MDDI_MSG_NOTICE(" MDP Line Counter=%d!\n",mdp_cnt_val); */ 1528 MDDI_MSG_NOTICE(" Lines Per Second=%d!\n", 1529 mddi_toshiba_rows_per_second); 1530 } 1531 /* clear the interrupt */ 1532 if (!mddi_queue_register_write_int(INTFLG, 0x0001)) 1533 MDDI_MSG_ERR("Vsync interrupt clear failed!\n"); 1534 } else { 1535 /* if detected = FALSE, we woke up from hibernation, but did not 1536 * detect client initiated wakeup. 1537 */ 1538 mddi_toshiba_vsync_attempts++; 1539 } 1540} 1541 1542static void mddi_toshiba_prim_init(struct msm_fb_data_type *mfd) 1543{ 1544 1545 switch (toshiba_state) { 1546 case TOSHIBA_STATE_PRIM_SEC_READY: 1547 break; 1548 case TOSHIBA_STATE_OFF: 1549 toshiba_state = TOSHIBA_STATE_PRIM_SEC_STANDBY; 1550 toshiba_common_initial_setup(mfd); 1551 break; 1552 case TOSHIBA_STATE_PRIM_SEC_STANDBY: 1553 toshiba_common_initial_setup(mfd); 1554 break; 1555 case TOSHIBA_STATE_SEC_NORMAL_MODE: 1556 toshiba_sec_cont_update_stop(mfd); 1557 toshiba_sec_sleep_in(mfd); 1558 toshiba_sec_sleep_out(mfd); 1559 toshiba_sec_lcd_off(mfd); 1560 toshiba_common_initial_setup(mfd); 1561 break; 1562 default: 1563 MDDI_MSG_ERR("mddi_toshiba_prim_init from state %d\n", 1564 toshiba_state); 1565 } 1566 1567 toshiba_prim_start(mfd); 1568 if (TM_GET_PID(mfd->panel.id) == LCD_SHARP_2P4_VGA) 1569 gordon_disp_init(); 1570 mddi_host_write_pix_attr_reg(0x00C3); 1571} 1572 1573static void mddi_toshiba_sec_init(struct msm_fb_data_type *mfd) 1574{ 1575 1576 switch (toshiba_state) { 1577 case TOSHIBA_STATE_PRIM_SEC_READY: 1578 break; 1579 case TOSHIBA_STATE_PRIM_SEC_STANDBY: 1580 toshiba_common_initial_setup(mfd); 1581 break; 1582 case TOSHIBA_STATE_PRIM_NORMAL_MODE: 1583 toshiba_prim_lcd_off(mfd); 1584 toshiba_common_initial_setup(mfd); 1585 break; 1586 default: 1587 MDDI_MSG_ERR("mddi_toshiba_sec_init from state %d\n", 1588 toshiba_state); 1589 } 1590 1591 toshiba_sec_start(mfd); 1592 toshiba_sec_backlight_on(mfd); 1593 toshiba_sec_cont_update_start(mfd); 1594 mddi_host_write_pix_attr_reg(0x0400); 1595} 1596 1597static void mddi_toshiba_lcd_powerdown(struct msm_fb_data_type *mfd) 1598{ 1599 switch (toshiba_state) { 1600 case TOSHIBA_STATE_PRIM_SEC_READY: 1601 mddi_toshiba_prim_init(mfd); 1602 mddi_toshiba_lcd_powerdown(mfd); 1603 return; 1604 case TOSHIBA_STATE_PRIM_SEC_STANDBY: 1605 break; 1606 case TOSHIBA_STATE_PRIM_NORMAL_MODE: 1607 toshiba_prim_lcd_off(mfd); 1608 break; 1609 case TOSHIBA_STATE_SEC_NORMAL_MODE: 1610 toshiba_sec_cont_update_stop(mfd); 1611 toshiba_sec_sleep_in(mfd); 1612 toshiba_sec_sleep_out(mfd); 1613 toshiba_sec_lcd_off(mfd); 1614 break; 1615 default: 1616 MDDI_MSG_ERR("mddi_toshiba_lcd_powerdown from state %d\n", 1617 toshiba_state); 1618 } 1619} 1620 1621static int mddi_sharpgordon_firsttime = 1; 1622 1623static int mddi_toshiba_lcd_on(struct platform_device *pdev) 1624{ 1625 struct msm_fb_data_type *mfd; 1626 mfd = platform_get_drvdata(pdev); 1627 if (!mfd) 1628 return -ENODEV; 1629 if (mfd->key != MFD_KEY) 1630 return -EINVAL; 1631 1632 if (TM_GET_DID(mfd->panel.id) == TOSHIBA_VGA_PRIM) 1633 mddi_toshiba_prim_init(mfd); 1634 else 1635 mddi_toshiba_sec_init(mfd); 1636 if (TM_GET_PID(mfd->panel.id) == LCD_SHARP_2P4_VGA) { 1637 if (mddi_sharpgordon_firsttime) { 1638 mddi_sharpgordon_firsttime = 0; 1639 write_client_reg(REGENB, 0x00000001, TRUE); 1640 } 1641 } 1642 return 0; 1643} 1644 1645static int mddi_toshiba_lcd_off(struct platform_device *pdev) 1646{ 1647 mddi_toshiba_lcd_powerdown(platform_get_drvdata(pdev)); 1648 return 0; 1649} 1650 1651static int __init mddi_toshiba_lcd_probe(struct platform_device *pdev) 1652{ 1653 if (pdev->id == 0) { 1654 mddi_toshiba_pdata = pdev->dev.platform_data; 1655 return 0; 1656 } 1657 1658 msm_fb_add_device(pdev); 1659 1660 return 0; 1661} 1662 1663static struct platform_driver this_driver = { 1664 .probe = mddi_toshiba_lcd_probe, 1665 .driver = { 1666 .name = "mddi_toshiba", 1667 }, 1668}; 1669 1670static struct msm_fb_panel_data toshiba_panel_data = { 1671 .on = mddi_toshiba_lcd_on, 1672 .off = mddi_toshiba_lcd_off, 1673}; 1674 1675static int ch_used[3]; 1676 1677int mddi_toshiba_device_register(struct msm_panel_info *pinfo, 1678 u32 channel, u32 panel) 1679{ 1680 struct platform_device *pdev = NULL; 1681 int ret; 1682 1683 if ((channel >= 3) || ch_used[channel]) 1684 return -ENODEV; 1685 1686 if ((channel != TOSHIBA_VGA_PRIM) && 1687 mddi_toshiba_pdata && mddi_toshiba_pdata->panel_num) 1688 if (mddi_toshiba_pdata->panel_num() < 2) 1689 return -ENODEV; 1690 1691 ch_used[channel] = TRUE; 1692 1693 pdev = platform_device_alloc("mddi_toshiba", (panel << 8)|channel); 1694 if (!pdev) 1695 return -ENOMEM; 1696 1697 if (channel == TOSHIBA_VGA_PRIM) { 1698 toshiba_panel_data.set_backlight = 1699 mddi_toshiba_lcd_set_backlight; 1700 1701 if (pinfo->lcd.vsync_enable) { 1702 toshiba_panel_data.set_vsync_notifier = 1703 mddi_toshiba_vsync_set_handler; 1704 mddi_lcd.vsync_detected = 1705 mddi_toshiba_lcd_vsync_detected; 1706 } 1707 } else { 1708 toshiba_panel_data.set_backlight = NULL; 1709 toshiba_panel_data.set_vsync_notifier = NULL; 1710 } 1711 1712 toshiba_panel_data.panel_info = *pinfo; 1713 1714 ret = platform_device_add_data(pdev, &toshiba_panel_data, 1715 sizeof(toshiba_panel_data)); 1716 if (ret) { 1717 printk(KERN_ERR 1718 "%s: platform_device_add_data failed!\n", __func__); 1719 goto err_device_put; 1720 } 1721 1722 ret = platform_device_add(pdev); 1723 if (ret) { 1724 printk(KERN_ERR 1725 "%s: platform_device_register failed!\n", __func__); 1726 goto err_device_put; 1727 } 1728 1729 return 0; 1730 1731err_device_put: 1732 platform_device_put(pdev); 1733 return ret; 1734} 1735 1736static int __init mddi_toshiba_lcd_init(void) 1737{ 1738 return platform_driver_register(&this_driver); 1739} 1740 1741module_init(mddi_toshiba_lcd_init); 1742