1/* 2 * Agere Systems Inc. 3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs 4 * 5 * Copyright * 2005 Agere Systems Inc. 6 * All rights reserved. 7 * http://www.agere.com 8 * 9 *------------------------------------------------------------------------------ 10 * 11 * et1310_phy.c - Routines for configuring and accessing the PHY 12 * 13 *------------------------------------------------------------------------------ 14 * 15 * SOFTWARE LICENSE 16 * 17 * This software is provided subject to the following terms and conditions, 18 * which you should read carefully before using the software. Using this 19 * software indicates your acceptance of these terms and conditions. If you do 20 * not agree with these terms and conditions, do not use the software. 21 * 22 * Copyright * 2005 Agere Systems Inc. 23 * All rights reserved. 24 * 25 * Redistribution and use in source or binary forms, with or without 26 * modifications, are permitted provided that the following conditions are met: 27 * 28 * . Redistributions of source code must retain the above copyright notice, this 29 * list of conditions and the following Disclaimer as comments in the code as 30 * well as in the documentation and/or other materials provided with the 31 * distribution. 32 * 33 * . Redistributions in binary form must reproduce the above copyright notice, 34 * this list of conditions and the following Disclaimer in the documentation 35 * and/or other materials provided with the distribution. 36 * 37 * . Neither the name of Agere Systems Inc. nor the names of the contributors 38 * may be used to endorse or promote products derived from this software 39 * without specific prior written permission. 40 * 41 * Disclaimer 42 * 43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF 45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY 46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN 47 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY 48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 51 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT 52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 54 * DAMAGE. 55 * 56 */ 57 58#include "et131x_version.h" 59#include "et131x_defs.h" 60 61#include <linux/pci.h> 62#include <linux/init.h> 63#include <linux/module.h> 64#include <linux/types.h> 65#include <linux/kernel.h> 66 67#include <linux/sched.h> 68#include <linux/ptrace.h> 69#include <linux/ctype.h> 70#include <linux/string.h> 71#include <linux/timer.h> 72#include <linux/interrupt.h> 73#include <linux/in.h> 74#include <linux/delay.h> 75#include <linux/io.h> 76#include <linux/bitops.h> 77#include <asm/system.h> 78 79#include <linux/netdevice.h> 80#include <linux/etherdevice.h> 81#include <linux/skbuff.h> 82#include <linux/if_arp.h> 83#include <linux/ioport.h> 84#include <linux/random.h> 85 86#include "et1310_phy.h" 87 88#include "et131x_adapter.h" 89 90#include "et1310_address_map.h" 91#include "et1310_tx.h" 92#include "et1310_rx.h" 93 94#include "et131x.h" 95 96/* Prototypes for functions with local scope */ 97static void et131x_xcvr_init(struct et131x_adapter *etdev); 98 99/** 100 * PhyMiRead - Read from the PHY through the MII Interface on the MAC 101 * @etdev: pointer to our private adapter structure 102 * @xcvrAddr: the address of the transciever 103 * @xcvrReg: the register to read 104 * @value: pointer to a 16-bit value in which the value will be stored 105 * 106 * Returns 0 on success, errno on failure (as defined in errno.h) 107 */ 108int PhyMiRead(struct et131x_adapter *etdev, u8 xcvrAddr, 109 u8 xcvrReg, u16 *value) 110{ 111 struct _MAC_t __iomem *mac = &etdev->regs->mac; 112 int status = 0; 113 u32 delay; 114 u32 miiAddr; 115 u32 miiCmd; 116 u32 miiIndicator; 117 118 /* Save a local copy of the registers we are dealing with so we can 119 * set them back 120 */ 121 miiAddr = readl(&mac->mii_mgmt_addr); 122 miiCmd = readl(&mac->mii_mgmt_cmd); 123 124 /* Stop the current operation */ 125 writel(0, &mac->mii_mgmt_cmd); 126 127 /* Set up the register we need to read from on the correct PHY */ 128 writel(MII_ADDR(xcvrAddr, xcvrReg), &mac->mii_mgmt_addr); 129 130 /* Kick the read cycle off */ 131 delay = 0; 132 133 writel(0x1, &mac->mii_mgmt_cmd); 134 135 do { 136 udelay(50); 137 delay++; 138 miiIndicator = readl(&mac->mii_mgmt_indicator); 139 } while ((miiIndicator & MGMT_WAIT) && delay < 50); 140 141 /* If we hit the max delay, we could not read the register */ 142 if (delay == 50) { 143 dev_warn(&etdev->pdev->dev, 144 "xcvrReg 0x%08x could not be read\n", xcvrReg); 145 dev_warn(&etdev->pdev->dev, "status is 0x%08x\n", 146 miiIndicator); 147 148 status = -EIO; 149 } 150 151 /* If we hit here we were able to read the register and we need to 152 * return the value to the caller */ 153 *value = readl(&mac->mii_mgmt_stat) & 0xFFFF; 154 155 /* Stop the read operation */ 156 writel(0, &mac->mii_mgmt_cmd); 157 158 /* set the registers we touched back to the state at which we entered 159 * this function 160 */ 161 writel(miiAddr, &mac->mii_mgmt_addr); 162 writel(miiCmd, &mac->mii_mgmt_cmd); 163 164 return status; 165} 166 167int MiWrite(struct et131x_adapter *etdev, u8 xcvrReg, u16 value) 168{ 169 struct _MAC_t __iomem *mac = &etdev->regs->mac; 170 int status = 0; 171 u8 xcvrAddr = etdev->Stats.xcvr_addr; 172 u32 delay; 173 u32 miiAddr; 174 u32 miiCmd; 175 u32 miiIndicator; 176 177 /* Save a local copy of the registers we are dealing with so we can 178 * set them back 179 */ 180 miiAddr = readl(&mac->mii_mgmt_addr); 181 miiCmd = readl(&mac->mii_mgmt_cmd); 182 183 /* Stop the current operation */ 184 writel(0, &mac->mii_mgmt_cmd); 185 186 /* Set up the register we need to write to on the correct PHY */ 187 writel(MII_ADDR(xcvrAddr, xcvrReg), &mac->mii_mgmt_addr); 188 189 /* Add the value to write to the registers to the mac */ 190 writel(value, &mac->mii_mgmt_ctrl); 191 delay = 0; 192 193 do { 194 udelay(50); 195 delay++; 196 miiIndicator = readl(&mac->mii_mgmt_indicator); 197 } while ((miiIndicator & MGMT_BUSY) && delay < 100); 198 199 /* If we hit the max delay, we could not write the register */ 200 if (delay == 100) { 201 u16 TempValue; 202 203 dev_warn(&etdev->pdev->dev, 204 "xcvrReg 0x%08x could not be written", xcvrReg); 205 dev_warn(&etdev->pdev->dev, "status is 0x%08x\n", 206 miiIndicator); 207 dev_warn(&etdev->pdev->dev, "command is 0x%08x\n", 208 readl(&mac->mii_mgmt_cmd)); 209 210 MiRead(etdev, xcvrReg, &TempValue); 211 212 status = -EIO; 213 } 214 /* Stop the write operation */ 215 writel(0, &mac->mii_mgmt_cmd); 216 217 /* set the registers we touched back to the state at which we entered 218 * this function 219 */ 220 writel(miiAddr, &mac->mii_mgmt_addr); 221 writel(miiCmd, &mac->mii_mgmt_cmd); 222 223 return status; 224} 225 226/** 227 * et131x_xcvr_find - Find the PHY ID 228 * @etdev: pointer to our private adapter structure 229 * 230 * Returns 0 on success, errno on failure (as defined in errno.h) 231 */ 232int et131x_xcvr_find(struct et131x_adapter *etdev) 233{ 234 u8 xcvr_addr; 235 MI_IDR1_t idr1; 236 MI_IDR2_t idr2; 237 u32 xcvr_id; 238 239 /* We need to get xcvr id and address we just get the first one */ 240 for (xcvr_addr = 0; xcvr_addr < 32; xcvr_addr++) { 241 /* Read the ID from the PHY */ 242 PhyMiRead(etdev, xcvr_addr, 243 (u8) offsetof(MI_REGS_t, idr1), 244 &idr1.value); 245 PhyMiRead(etdev, xcvr_addr, 246 (u8) offsetof(MI_REGS_t, idr2), 247 &idr2.value); 248 249 xcvr_id = (u32) ((idr1.value << 16) | idr2.value); 250 251 if (idr1.value != 0 && idr1.value != 0xffff) { 252 etdev->Stats.xcvr_id = xcvr_id; 253 etdev->Stats.xcvr_addr = xcvr_addr; 254 return 0; 255 } 256 } 257 return -ENODEV; 258} 259 260void ET1310_PhyReset(struct et131x_adapter *etdev) 261{ 262 MiWrite(etdev, PHY_CONTROL, 0x8000); 263} 264 265/** 266 * ET1310_PhyPowerDown - PHY power control 267 * @etdev: device to control 268 * @down: true for off/false for back on 269 * 270 * one hundred, ten, one thousand megs 271 * How would you like to have your LAN accessed 272 * Can't you see that this code processed 273 * Phy power, phy power.. 274 */ 275 276void ET1310_PhyPowerDown(struct et131x_adapter *etdev, bool down) 277{ 278 u16 data; 279 280 MiRead(etdev, PHY_CONTROL, &data); 281 data &= ~0x0800; /* Power UP */ 282 if (down) /* Power DOWN */ 283 data |= 0x0800; 284 MiWrite(etdev, PHY_CONTROL, data); 285} 286 287/** 288 * ET130_PhyAutoNEg - autonegotiate control 289 * @etdev: device to control 290 * @enabe: autoneg on/off 291 * 292 * Set up the autonegotiation state according to whether we will be 293 * negotiating the state or forcing a speed. 294 */ 295 296static void ET1310_PhyAutoNeg(struct et131x_adapter *etdev, bool enable) 297{ 298 u16 data; 299 300 MiRead(etdev, PHY_CONTROL, &data); 301 data &= ~0x1000; /* Autonegotiation OFF */ 302 if (enable) 303 data |= 0x1000; /* Autonegotiation ON */ 304 MiWrite(etdev, PHY_CONTROL, data); 305} 306 307/** 308 * ET130_PhyDuplexMode - duplex control 309 * @etdev: device to control 310 * @duplex: duplex on/off 311 * 312 * Set up the duplex state on the PHY 313 */ 314 315static void ET1310_PhyDuplexMode(struct et131x_adapter *etdev, u16 duplex) 316{ 317 u16 data; 318 319 MiRead(etdev, PHY_CONTROL, &data); 320 data &= ~0x100; /* Set Half Duplex */ 321 if (duplex == TRUEPHY_DUPLEX_FULL) 322 data |= 0x100; /* Set Full Duplex */ 323 MiWrite(etdev, PHY_CONTROL, data); 324} 325 326/** 327 * ET130_PhySpeedSelect - speed control 328 * @etdev: device to control 329 * @duplex: duplex on/off 330 * 331 * Set the speed of our PHY. 332 */ 333 334static void ET1310_PhySpeedSelect(struct et131x_adapter *etdev, u16 speed) 335{ 336 u16 data; 337 static const u16 bits[3] = {0x0000, 0x2000, 0x0040}; 338 339 /* Read the PHY control register */ 340 MiRead(etdev, PHY_CONTROL, &data); 341 /* Clear all Speed settings (Bits 6, 13) */ 342 data &= ~0x2040; 343 /* Write back the new speed */ 344 MiWrite(etdev, PHY_CONTROL, data | bits[speed]); 345} 346 347/** 348 * ET1310_PhyLinkStatus - read link state 349 * @etdev: device to read 350 * @link_status: reported link state 351 * @autoneg: reported autonegotiation state (complete/incomplete/disabled) 352 * @linkspeed: returnedlink speed in use 353 * @duplex_mode: reported half/full duplex state 354 * @mdi_mdix: not yet working 355 * @masterslave: report whether we are master or slave 356 * @polarity: link polarity 357 * 358 * I can read your lan like a magazine 359 * I see if your up 360 * I know your link speed 361 * I see all the setting that you'd rather keep 362 */ 363 364static void ET1310_PhyLinkStatus(struct et131x_adapter *etdev, 365 u8 *link_status, 366 u32 *autoneg, 367 u32 *linkspeed, 368 u32 *duplex_mode, 369 u32 *mdi_mdix, 370 u32 *masterslave, u32 *polarity) 371{ 372 u16 mistatus = 0; 373 u16 is1000BaseT = 0; 374 u16 vmi_phystatus = 0; 375 u16 control = 0; 376 377 MiRead(etdev, PHY_STATUS, &mistatus); 378 MiRead(etdev, PHY_1000_STATUS, &is1000BaseT); 379 MiRead(etdev, PHY_PHY_STATUS, &vmi_phystatus); 380 MiRead(etdev, PHY_CONTROL, &control); 381 382 *link_status = (vmi_phystatus & 0x0040) ? 1 : 0; 383 *autoneg = (control & 0x1000) ? ((vmi_phystatus & 0x0020) ? 384 TRUEPHY_ANEG_COMPLETE : 385 TRUEPHY_ANEG_NOT_COMPLETE) : 386 TRUEPHY_ANEG_DISABLED; 387 *linkspeed = (vmi_phystatus & 0x0300) >> 8; 388 *duplex_mode = (vmi_phystatus & 0x0080) >> 7; 389 /* NOTE: Need to complete this */ 390 *mdi_mdix = 0; 391 392 *masterslave = (is1000BaseT & 0x4000) ? 393 TRUEPHY_CFG_MASTER : TRUEPHY_CFG_SLAVE; 394 *polarity = (vmi_phystatus & 0x0400) ? 395 TRUEPHY_POLARITY_INVERTED : TRUEPHY_POLARITY_NORMAL; 396} 397 398static void ET1310_PhyAndOrReg(struct et131x_adapter *etdev, 399 u16 regnum, u16 andMask, u16 orMask) 400{ 401 u16 reg; 402 403 MiRead(etdev, regnum, ®); 404 reg &= andMask; 405 reg |= orMask; 406 MiWrite(etdev, regnum, reg); 407} 408 409/* Still used from _mac for BIT_READ */ 410void ET1310_PhyAccessMiBit(struct et131x_adapter *etdev, u16 action, 411 u16 regnum, u16 bitnum, u8 *value) 412{ 413 u16 reg; 414 u16 mask = 0x0001 << bitnum; 415 416 /* Read the requested register */ 417 MiRead(etdev, regnum, ®); 418 419 switch (action) { 420 case TRUEPHY_BIT_READ: 421 *value = (reg & mask) >> bitnum; 422 break; 423 424 case TRUEPHY_BIT_SET: 425 MiWrite(etdev, regnum, reg | mask); 426 break; 427 428 case TRUEPHY_BIT_CLEAR: 429 MiWrite(etdev, regnum, reg & ~mask); 430 break; 431 432 default: 433 break; 434 } 435} 436 437void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *etdev, 438 u16 duplex) 439{ 440 u16 data; 441 442 /* Read the PHY 1000 Base-T Control Register */ 443 MiRead(etdev, PHY_1000_CONTROL, &data); 444 445 /* Clear Bits 8,9 */ 446 data &= ~0x0300; 447 448 switch (duplex) { 449 case TRUEPHY_ADV_DUPLEX_NONE: 450 /* Duplex already cleared, do nothing */ 451 break; 452 453 case TRUEPHY_ADV_DUPLEX_FULL: 454 /* Set Bit 9 */ 455 data |= 0x0200; 456 break; 457 458 case TRUEPHY_ADV_DUPLEX_HALF: 459 /* Set Bit 8 */ 460 data |= 0x0100; 461 break; 462 463 case TRUEPHY_ADV_DUPLEX_BOTH: 464 default: 465 data |= 0x0300; 466 break; 467 } 468 469 /* Write back advertisement */ 470 MiWrite(etdev, PHY_1000_CONTROL, data); 471} 472 473static void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *etdev, 474 u16 duplex) 475{ 476 u16 data; 477 478 /* Read the Autonegotiation Register (10/100) */ 479 MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data); 480 481 /* Clear bits 7,8 */ 482 data &= ~0x0180; 483 484 switch (duplex) { 485 case TRUEPHY_ADV_DUPLEX_NONE: 486 /* Duplex already cleared, do nothing */ 487 break; 488 489 case TRUEPHY_ADV_DUPLEX_FULL: 490 /* Set Bit 8 */ 491 data |= 0x0100; 492 break; 493 494 case TRUEPHY_ADV_DUPLEX_HALF: 495 /* Set Bit 7 */ 496 data |= 0x0080; 497 break; 498 499 case TRUEPHY_ADV_DUPLEX_BOTH: 500 default: 501 /* Set Bits 7,8 */ 502 data |= 0x0180; 503 break; 504 } 505 506 /* Write back advertisement */ 507 MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data); 508} 509 510static void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *etdev, 511 u16 duplex) 512{ 513 u16 data; 514 515 /* Read the Autonegotiation Register (10/100) */ 516 MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data); 517 518 /* Clear bits 5,6 */ 519 data &= ~0x0060; 520 521 switch (duplex) { 522 case TRUEPHY_ADV_DUPLEX_NONE: 523 /* Duplex already cleared, do nothing */ 524 break; 525 526 case TRUEPHY_ADV_DUPLEX_FULL: 527 /* Set Bit 6 */ 528 data |= 0x0040; 529 break; 530 531 case TRUEPHY_ADV_DUPLEX_HALF: 532 /* Set Bit 5 */ 533 data |= 0x0020; 534 break; 535 536 case TRUEPHY_ADV_DUPLEX_BOTH: 537 default: 538 /* Set Bits 5,6 */ 539 data |= 0x0060; 540 break; 541 } 542 543 /* Write back advertisement */ 544 MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data); 545} 546 547/** 548 * et131x_setphy_normal - Set PHY for normal operation. 549 * @etdev: pointer to our private adapter structure 550 * 551 * Used by Power Management to force the PHY into 10 Base T half-duplex mode, 552 * when going to D3 in WOL mode. Also used during initialization to set the 553 * PHY for normal operation. 554 */ 555void et131x_setphy_normal(struct et131x_adapter *etdev) 556{ 557 /* Make sure the PHY is powered up */ 558 ET1310_PhyPowerDown(etdev, 0); 559 et131x_xcvr_init(etdev); 560} 561 562 563/** 564 * et131x_xcvr_init - Init the phy if we are setting it into force mode 565 * @etdev: pointer to our private adapter structure 566 * 567 */ 568static void et131x_xcvr_init(struct et131x_adapter *etdev) 569{ 570 MI_IMR_t imr; 571 MI_ISR_t isr; 572 MI_LCR2_t lcr2; 573 574 /* Zero out the adapter structure variable representing BMSR */ 575 etdev->Bmsr.value = 0; 576 577 MiRead(etdev, (u8) offsetof(MI_REGS_t, isr), &isr.value); 578 MiRead(etdev, (u8) offsetof(MI_REGS_t, imr), &imr.value); 579 580 /* Set the link status interrupt only. Bad behavior when link status 581 * and auto neg are set, we run into a nested interrupt problem 582 */ 583 imr.bits.int_en = 0x1; 584 imr.bits.link_status = 0x1; 585 imr.bits.autoneg_status = 0x1; 586 587 MiWrite(etdev, (u8) offsetof(MI_REGS_t, imr), imr.value); 588 589 /* Set the LED behavior such that LED 1 indicates speed (off = 590 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates 591 * link and activity (on for link, blink off for activity). 592 * 593 * NOTE: Some customizations have been added here for specific 594 * vendors; The LED behavior is now determined by vendor data in the 595 * EEPROM. However, the above description is the default. 596 */ 597 if ((etdev->eepromData[1] & 0x4) == 0) { 598 MiRead(etdev, (u8) offsetof(MI_REGS_t, lcr2), 599 &lcr2.value); 600 if ((etdev->eepromData[1] & 0x8) == 0) 601 lcr2.bits.led_tx_rx = 0x3; 602 else 603 lcr2.bits.led_tx_rx = 0x4; 604 lcr2.bits.led_link = 0xa; 605 MiWrite(etdev, (u8) offsetof(MI_REGS_t, lcr2), 606 lcr2.value); 607 } 608 609 /* Determine if we need to go into a force mode and set it */ 610 if (etdev->AiForceSpeed == 0 && etdev->AiForceDpx == 0) { 611 if (etdev->RegistryFlowControl == TxOnly || 612 etdev->RegistryFlowControl == Both) 613 ET1310_PhyAccessMiBit(etdev, 614 TRUEPHY_BIT_SET, 4, 11, NULL); 615 else 616 ET1310_PhyAccessMiBit(etdev, 617 TRUEPHY_BIT_CLEAR, 4, 11, NULL); 618 619 if (etdev->RegistryFlowControl == Both) 620 ET1310_PhyAccessMiBit(etdev, 621 TRUEPHY_BIT_SET, 4, 10, NULL); 622 else 623 ET1310_PhyAccessMiBit(etdev, 624 TRUEPHY_BIT_CLEAR, 4, 10, NULL); 625 626 /* Set the phy to autonegotiation */ 627 ET1310_PhyAutoNeg(etdev, true); 628 629 /* NOTE - Do we need this? */ 630 ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_SET, 0, 9, NULL); 631 return; 632 } 633 634 ET1310_PhyAutoNeg(etdev, false); 635 636 /* Set to the correct force mode. */ 637 if (etdev->AiForceDpx != 1) { 638 if (etdev->RegistryFlowControl == TxOnly || 639 etdev->RegistryFlowControl == Both) 640 ET1310_PhyAccessMiBit(etdev, 641 TRUEPHY_BIT_SET, 4, 11, NULL); 642 else 643 ET1310_PhyAccessMiBit(etdev, 644 TRUEPHY_BIT_CLEAR, 4, 11, NULL); 645 646 if (etdev->RegistryFlowControl == Both) 647 ET1310_PhyAccessMiBit(etdev, 648 TRUEPHY_BIT_SET, 4, 10, NULL); 649 else 650 ET1310_PhyAccessMiBit(etdev, 651 TRUEPHY_BIT_CLEAR, 4, 10, NULL); 652 } else { 653 ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_CLEAR, 4, 10, NULL); 654 ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_CLEAR, 4, 11, NULL); 655 } 656 ET1310_PhyPowerDown(etdev, 1); 657 switch (etdev->AiForceSpeed) { 658 case 10: 659 /* First we need to turn off all other advertisement */ 660 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); 661 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); 662 if (etdev->AiForceDpx == 1) { 663 /* Set our advertise values accordingly */ 664 ET1310_PhyAdvertise10BaseT(etdev, 665 TRUEPHY_ADV_DUPLEX_HALF); 666 } else if (etdev->AiForceDpx == 2) { 667 /* Set our advertise values accordingly */ 668 ET1310_PhyAdvertise10BaseT(etdev, 669 TRUEPHY_ADV_DUPLEX_FULL); 670 } else { 671 /* Disable autoneg */ 672 ET1310_PhyAutoNeg(etdev, false); 673 /* Disable rest of the advertisements */ 674 ET1310_PhyAdvertise10BaseT(etdev, 675 TRUEPHY_ADV_DUPLEX_NONE); 676 /* Force 10 Mbps */ 677 ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_10MBPS); 678 /* Force Full duplex */ 679 ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL); 680 } 681 break; 682 case 100: 683 /* first we need to turn off all other advertisement */ 684 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); 685 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); 686 if (etdev->AiForceDpx == 1) { 687 /* Set our advertise values accordingly */ 688 ET1310_PhyAdvertise100BaseT(etdev, 689 TRUEPHY_ADV_DUPLEX_HALF); 690 /* Set speed */ 691 ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS); 692 } else if (etdev->AiForceDpx == 2) { 693 /* Set our advertise values accordingly */ 694 ET1310_PhyAdvertise100BaseT(etdev, 695 TRUEPHY_ADV_DUPLEX_FULL); 696 } else { 697 /* Disable autoneg */ 698 ET1310_PhyAutoNeg(etdev, false); 699 /* Disable other advertisement */ 700 ET1310_PhyAdvertise100BaseT(etdev, 701 TRUEPHY_ADV_DUPLEX_NONE); 702 /* Force 100 Mbps */ 703 ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS); 704 /* Force Full duplex */ 705 ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL); 706 } 707 break; 708 case 1000: 709 /* first we need to turn off all other advertisement */ 710 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); 711 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); 712 /* set our advertise values accordingly */ 713 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL); 714 break; 715 } 716 ET1310_PhyPowerDown(etdev, 0); 717} 718 719void et131x_Mii_check(struct et131x_adapter *etdev, 720 MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints) 721{ 722 u8 link_status; 723 u32 autoneg_status; 724 u32 speed; 725 u32 duplex; 726 u32 mdi_mdix; 727 u32 masterslave; 728 u32 polarity; 729 unsigned long flags; 730 731 if (bmsr_ints.bits.link_status) { 732 if (bmsr.bits.link_status) { 733 etdev->PoMgmt.TransPhyComaModeOnBoot = 20; 734 735 /* Update our state variables and indicate the 736 * connected state 737 */ 738 spin_lock_irqsave(&etdev->Lock, flags); 739 740 etdev->MediaState = NETIF_STATUS_MEDIA_CONNECT; 741 etdev->Flags &= ~fMP_ADAPTER_LINK_DETECTION; 742 743 spin_unlock_irqrestore(&etdev->Lock, flags); 744 745 netif_carrier_on(etdev->netdev); 746 } else { 747 dev_warn(&etdev->pdev->dev, 748 "Link down - cable problem ?\n"); 749 750 if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) { 751 /* NOTE - Is there a way to query this without 752 * TruePHY? 753 * && TRU_QueryCoreType(etdev->hTruePhy, 0) == 754 * EMI_TRUEPHY_A13O) { 755 */ 756 u16 Register18; 757 758 MiRead(etdev, 0x12, &Register18); 759 MiWrite(etdev, 0x12, Register18 | 0x4); 760 MiWrite(etdev, 0x10, Register18 | 0x8402); 761 MiWrite(etdev, 0x11, Register18 | 511); 762 MiWrite(etdev, 0x12, Register18); 763 } 764 765 /* For the first N seconds of life, we are in "link 766 * detection" When we are in this state, we should 767 * only report "connected". When the LinkDetection 768 * Timer expires, we can report disconnected (handled 769 * in the LinkDetectionDPC). 770 */ 771 if (!(etdev->Flags & fMP_ADAPTER_LINK_DETECTION) || 772 (etdev->MediaState == NETIF_STATUS_MEDIA_DISCONNECT)) { 773 spin_lock_irqsave(&etdev->Lock, flags); 774 etdev->MediaState = 775 NETIF_STATUS_MEDIA_DISCONNECT; 776 spin_unlock_irqrestore(&etdev->Lock, 777 flags); 778 779 netif_carrier_off(etdev->netdev); 780 } 781 782 etdev->linkspeed = 0; 783 etdev->duplex_mode = 0; 784 785 /* Free the packets being actively sent & stopped */ 786 et131x_free_busy_send_packets(etdev); 787 788 /* Re-initialize the send structures */ 789 et131x_init_send(etdev); 790 791 /* Reset the RFD list and re-start RU */ 792 et131x_reset_recv(etdev); 793 794 /* 795 * Bring the device back to the state it was during 796 * init prior to autonegotiation being complete. This 797 * way, when we get the auto-neg complete interrupt, 798 * we can complete init by calling ConfigMacREGS2. 799 */ 800 et131x_soft_reset(etdev); 801 802 /* Setup ET1310 as per the documentation */ 803 et131x_adapter_setup(etdev); 804 805 /* Setup the PHY into coma mode until the cable is 806 * plugged back in 807 */ 808 if (etdev->RegistryPhyComa == 1) 809 EnablePhyComa(etdev); 810 } 811 } 812 813 if (bmsr_ints.bits.auto_neg_complete || 814 (etdev->AiForceDpx == 3 && bmsr_ints.bits.link_status)) { 815 if (bmsr.bits.auto_neg_complete || etdev->AiForceDpx == 3) { 816 ET1310_PhyLinkStatus(etdev, 817 &link_status, &autoneg_status, 818 &speed, &duplex, &mdi_mdix, 819 &masterslave, &polarity); 820 821 etdev->linkspeed = speed; 822 etdev->duplex_mode = duplex; 823 824 etdev->PoMgmt.TransPhyComaModeOnBoot = 20; 825 826 if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) { 827 /* 828 * NOTE - Is there a way to query this without 829 * TruePHY? 830 * && TRU_QueryCoreType(etdev->hTruePhy, 0)== 831 * EMI_TRUEPHY_A13O) { 832 */ 833 u16 Register18; 834 835 MiRead(etdev, 0x12, &Register18); 836 MiWrite(etdev, 0x12, Register18 | 0x4); 837 MiWrite(etdev, 0x10, Register18 | 0x8402); 838 MiWrite(etdev, 0x11, Register18 | 511); 839 MiWrite(etdev, 0x12, Register18); 840 } 841 842 ConfigFlowControl(etdev); 843 844 if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS && 845 etdev->RegistryJumboPacket > 2048) 846 ET1310_PhyAndOrReg(etdev, 0x16, 0xcfff, 847 0x2000); 848 849 SetRxDmaTimer(etdev); 850 ConfigMACRegs2(etdev); 851 } 852 } 853} 854 855/* 856 * The routines which follow provide low-level access to the PHY, and are used 857 * primarily by the routines above (although there are a few places elsewhere 858 * in the driver where this level of access is required). 859 */ 860 861static const u16 ConfigPhy[25][2] = { 862 /* Reg Value Register */ 863 /* Addr */ 864 {0x880B, 0x0926}, /* AfeIfCreg4B1000Msbs */ 865 {0x880C, 0x0926}, /* AfeIfCreg4B100Msbs */ 866 {0x880D, 0x0926}, /* AfeIfCreg4B10Msbs */ 867 868 {0x880E, 0xB4D3}, /* AfeIfCreg4B1000Lsbs */ 869 {0x880F, 0xB4D3}, /* AfeIfCreg4B100Lsbs */ 870 {0x8810, 0xB4D3}, /* AfeIfCreg4B10Lsbs */ 871 872 {0x8805, 0xB03E}, /* AfeIfCreg3B1000Msbs */ 873 {0x8806, 0xB03E}, /* AfeIfCreg3B100Msbs */ 874 {0x8807, 0xFF00}, /* AfeIfCreg3B10Msbs */ 875 876 {0x8808, 0xE090}, /* AfeIfCreg3B1000Lsbs */ 877 {0x8809, 0xE110}, /* AfeIfCreg3B100Lsbs */ 878 {0x880A, 0x0000}, /* AfeIfCreg3B10Lsbs */ 879 880 {0x300D, 1}, /* DisableNorm */ 881 882 {0x280C, 0x0180}, /* LinkHoldEnd */ 883 884 {0x1C21, 0x0002}, /* AlphaM */ 885 886 {0x3821, 6}, /* FfeLkgTx0 */ 887 {0x381D, 1}, /* FfeLkg1g4 */ 888 {0x381E, 1}, /* FfeLkg1g5 */ 889 {0x381F, 1}, /* FfeLkg1g6 */ 890 {0x3820, 1}, /* FfeLkg1g7 */ 891 892 {0x8402, 0x01F0}, /* Btinact */ 893 {0x800E, 20}, /* LftrainTime */ 894 {0x800F, 24}, /* DvguardTime */ 895 {0x8010, 46}, /* IdlguardTime */ 896 897 {0, 0} 898 899}; 900 901/* condensed version of the phy initialization routine */ 902void ET1310_PhyInit(struct et131x_adapter *etdev) 903{ 904 u16 data, index; 905 906 if (etdev == NULL) 907 return; 908 909 /* get the identity (again ?) */ 910 MiRead(etdev, PHY_ID_1, &data); 911 MiRead(etdev, PHY_ID_2, &data); 912 913 /* what does this do/achieve ? */ 914 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */ 915 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006); 916 917 /* read modem register 0402, should I do something with the return 918 data ? */ 919 MiWrite(etdev, PHY_INDEX_REG, 0x0402); 920 MiRead(etdev, PHY_DATA_REG, &data); 921 922 /* what does this do/achieve ? */ 923 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002); 924 925 /* get the identity (again ?) */ 926 MiRead(etdev, PHY_ID_1, &data); 927 MiRead(etdev, PHY_ID_2, &data); 928 929 /* what does this achieve ? */ 930 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */ 931 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006); 932 933 /* read modem register 0402, should I do something with 934 the return data? */ 935 MiWrite(etdev, PHY_INDEX_REG, 0x0402); 936 MiRead(etdev, PHY_DATA_REG, &data); 937 938 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002); 939 940 /* what does this achieve (should return 0x1040) */ 941 MiRead(etdev, PHY_CONTROL, &data); 942 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */ 943 MiWrite(etdev, PHY_CONTROL, 0x1840); 944 945 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0007); 946 947 /* here the writing of the array starts.... */ 948 index = 0; 949 while (ConfigPhy[index][0] != 0x0000) { 950 /* write value */ 951 MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]); 952 MiWrite(etdev, PHY_DATA_REG, ConfigPhy[index][1]); 953 954 /* read it back */ 955 MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]); 956 MiRead(etdev, PHY_DATA_REG, &data); 957 958 /* do a check on the value read back ? */ 959 index++; 960 } 961 /* here the writing of the array ends... */ 962 963 MiRead(etdev, PHY_CONTROL, &data); /* 0x1840 */ 964 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data);/* should read 0007 */ 965 MiWrite(etdev, PHY_CONTROL, 0x1040); 966 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002); 967} 968