1/* 2 * Copyright (c) 2000-2010 LSI Corporation. 3 * 4 * 5 * Name: mpi2.h 6 * Title: MPI Message independent structures and definitions 7 * including System Interface Register Set and 8 * scatter/gather formats. 9 * Creation Date: June 21, 2006 10 * 11 * mpi2.h Version: 02.00.15 12 * 13 * Version History 14 * --------------- 15 * 16 * Date Version Description 17 * -------- -------- ------------------------------------------------------ 18 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 19 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT. 20 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT. 21 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT. 22 * Moved ReplyPostHostIndex register to offset 0x6C of the 23 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for 24 * MPI2_REPLY_POST_HOST_INDEX_OFFSET. 25 * Added union of request descriptors. 26 * Added union of reply descriptors. 27 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT. 28 * Added define for MPI2_VERSION_02_00. 29 * Fixed the size of the FunctionDependent5 field in the 30 * MPI2_DEFAULT_REPLY structure. 31 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT. 32 * Removed the MPI-defined Fault Codes and extended the 33 * product specific codes up to 0xEFFF. 34 * Added a sixth key value for the WriteSequence register 35 * and changed the flush value to 0x0. 36 * Added message function codes for Diagnostic Buffer Post 37 * and Diagnsotic Release. 38 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED 39 * Moved MPI2_VERSION_UNION from mpi2_ioc.h. 40 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT. 41 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT. 42 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT. 43 * Added #defines for marking a reply descriptor as unused. 44 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT. 45 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT. 46 * Moved LUN field defines from mpi2_init.h. 47 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT. 48 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT. 49 * In all request and reply descriptors, replaced VF_ID 50 * field with MSIxIndex field. 51 * Removed DevHandle field from 52 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those 53 * bytes reserved. 54 * Added RAID Accelerator functionality. 55 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT. 56 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT. 57 * Added MSI-x index mask and shift for Reply Post Host 58 * Index register. 59 * Added function code for Host Based Discovery Action. 60 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT. 61 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL. 62 * Added defines for product-specific range of message 63 * function codes, 0xF0 to 0xFF. 64 * -------------------------------------------------------------------------- 65 */ 66 67#ifndef MPI2_H 68#define MPI2_H 69 70 71/***************************************************************************** 72* 73* MPI Version Definitions 74* 75*****************************************************************************/ 76 77#define MPI2_VERSION_MAJOR (0x02) 78#define MPI2_VERSION_MINOR (0x00) 79#define MPI2_VERSION_MAJOR_MASK (0xFF00) 80#define MPI2_VERSION_MAJOR_SHIFT (8) 81#define MPI2_VERSION_MINOR_MASK (0x00FF) 82#define MPI2_VERSION_MINOR_SHIFT (0) 83#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 84 MPI2_VERSION_MINOR) 85 86#define MPI2_VERSION_02_00 (0x0200) 87 88/* versioning for this MPI header set */ 89#define MPI2_HEADER_VERSION_UNIT (0x0F) 90#define MPI2_HEADER_VERSION_DEV (0x00) 91#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 92#define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 93#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 94#define MPI2_HEADER_VERSION_DEV_SHIFT (0) 95#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 96 97 98/***************************************************************************** 99* 100* IOC State Definitions 101* 102*****************************************************************************/ 103 104#define MPI2_IOC_STATE_RESET (0x00000000) 105#define MPI2_IOC_STATE_READY (0x10000000) 106#define MPI2_IOC_STATE_OPERATIONAL (0x20000000) 107#define MPI2_IOC_STATE_FAULT (0x40000000) 108 109#define MPI2_IOC_STATE_MASK (0xF0000000) 110#define MPI2_IOC_STATE_SHIFT (28) 111 112/* Fault state range for prodcut specific codes */ 113#define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000) 114#define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF) 115 116 117/***************************************************************************** 118* 119* System Interface Register Definitions 120* 121*****************************************************************************/ 122 123typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS 124{ 125 U32 Doorbell; /* 0x00 */ 126 U32 WriteSequence; /* 0x04 */ 127 U32 HostDiagnostic; /* 0x08 */ 128 U32 Reserved1; /* 0x0C */ 129 U32 DiagRWData; /* 0x10 */ 130 U32 DiagRWAddressLow; /* 0x14 */ 131 U32 DiagRWAddressHigh; /* 0x18 */ 132 U32 Reserved2[5]; /* 0x1C */ 133 U32 HostInterruptStatus; /* 0x30 */ 134 U32 HostInterruptMask; /* 0x34 */ 135 U32 DCRData; /* 0x38 */ 136 U32 DCRAddress; /* 0x3C */ 137 U32 Reserved3[2]; /* 0x40 */ 138 U32 ReplyFreeHostIndex; /* 0x48 */ 139 U32 Reserved4[8]; /* 0x4C */ 140 U32 ReplyPostHostIndex; /* 0x6C */ 141 U32 Reserved5; /* 0x70 */ 142 U32 HCBSize; /* 0x74 */ 143 U32 HCBAddressLow; /* 0x78 */ 144 U32 HCBAddressHigh; /* 0x7C */ 145 U32 Reserved6[16]; /* 0x80 */ 146 U32 RequestDescriptorPostLow; /* 0xC0 */ 147 U32 RequestDescriptorPostHigh; /* 0xC4 */ 148 U32 Reserved7[14]; /* 0xC8 */ 149} MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS, 150 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t; 151 152/* 153 * Defines for working with the Doorbell register. 154 */ 155#define MPI2_DOORBELL_OFFSET (0x00000000) 156 157/* IOC --> System values */ 158#define MPI2_DOORBELL_USED (0x08000000) 159#define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000) 160#define MPI2_DOORBELL_WHO_INIT_SHIFT (24) 161#define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF) 162#define MPI2_DOORBELL_DATA_MASK (0x0000FFFF) 163 164/* System --> IOC values */ 165#define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000) 166#define MPI2_DOORBELL_FUNCTION_SHIFT (24) 167#define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 168#define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16) 169 170 171/* 172 * Defines for the WriteSequence register 173 */ 174#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 175#define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F) 176#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 177#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 178#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 179#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 180#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 181#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 182#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 183 184/* 185 * Defines for the HostDiagnostic register 186 */ 187#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) 188 189#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) 190#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) 191#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) 192 193#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 194#define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) 195#define MPI2_DIAG_HCB_MODE (0x00000100) 196#define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) 197#define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) 198#define MPI2_DIAG_RESET_HISTORY (0x00000020) 199#define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) 200#define MPI2_DIAG_RESET_ADAPTER (0x00000004) 201#define MPI2_DIAG_HOLD_IOC_RESET (0x00000002) 202 203/* 204 * Offsets for DiagRWData and address 205 */ 206#define MPI2_DIAG_RW_DATA_OFFSET (0x00000010) 207#define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014) 208#define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018) 209 210/* 211 * Defines for the HostInterruptStatus register 212 */ 213#define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 214#define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000) 215#define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS 216#define MPI2_HIS_RESET_IRQ_STATUS (0x40000000) 217#define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008) 218#define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001) 219#define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS 220 221/* 222 * Defines for the HostInterruptMask register 223 */ 224#define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 225#define MPI2_HIM_RESET_IRQ_MASK (0x40000000) 226#define MPI2_HIM_REPLY_INT_MASK (0x00000008) 227#define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK 228#define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001) 229#define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK 230 231/* 232 * Offsets for DCRData and address 233 */ 234#define MPI2_DCR_DATA_OFFSET (0x00000038) 235#define MPI2_DCR_ADDRESS_OFFSET (0x0000003C) 236 237/* 238 * Offset for the Reply Free Queue 239 */ 240#define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048) 241 242/* 243 * Defines for the Reply Descriptor Post Queue 244 */ 245#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 246#define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF) 247#define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000) 248#define MPI2_RPHI_MSIX_INDEX_SHIFT (24) 249 250/* 251 * Defines for the HCBSize and address 252 */ 253#define MPI2_HCB_SIZE_OFFSET (0x00000074) 254#define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) 255#define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) 256 257#define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) 258#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) 259 260/* 261 * Offsets for the Request Queue 262 */ 263#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) 264#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) 265 266 267/***************************************************************************** 268* 269* Message Descriptors 270* 271*****************************************************************************/ 272 273/* Request Descriptors */ 274 275/* Default Request Descriptor */ 276typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR 277{ 278 U8 RequestFlags; /* 0x00 */ 279 U8 MSIxIndex; /* 0x01 */ 280 U16 SMID; /* 0x02 */ 281 U16 LMID; /* 0x04 */ 282 U16 DescriptorTypeDependent; /* 0x06 */ 283} MPI2_DEFAULT_REQUEST_DESCRIPTOR, 284 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 285 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 286 287/* defines for the RequestFlags field */ 288#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 289#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 290#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 291#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 292#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 293#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 294 295#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 296 297 298/* High Priority Request Descriptor */ 299typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR 300{ 301 U8 RequestFlags; /* 0x00 */ 302 U8 MSIxIndex; /* 0x01 */ 303 U16 SMID; /* 0x02 */ 304 U16 LMID; /* 0x04 */ 305 U16 Reserved1; /* 0x06 */ 306} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 307 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 308 Mpi2HighPriorityRequestDescriptor_t, 309 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 310 311 312/* SCSI IO Request Descriptor */ 313typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR 314{ 315 U8 RequestFlags; /* 0x00 */ 316 U8 MSIxIndex; /* 0x01 */ 317 U16 SMID; /* 0x02 */ 318 U16 LMID; /* 0x04 */ 319 U16 DevHandle; /* 0x06 */ 320} MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 321 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 322 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 323 324 325/* SCSI Target Request Descriptor */ 326typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR 327{ 328 U8 RequestFlags; /* 0x00 */ 329 U8 MSIxIndex; /* 0x01 */ 330 U16 SMID; /* 0x02 */ 331 U16 LMID; /* 0x04 */ 332 U16 IoIndex; /* 0x06 */ 333} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 334 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 335 Mpi2SCSITargetRequestDescriptor_t, 336 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 337 338 339/* RAID Accelerator Request Descriptor */ 340typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { 341 U8 RequestFlags; /* 0x00 */ 342 U8 MSIxIndex; /* 0x01 */ 343 U16 SMID; /* 0x02 */ 344 U16 LMID; /* 0x04 */ 345 U16 Reserved; /* 0x06 */ 346} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 347 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 348 Mpi2RAIDAcceleratorRequestDescriptor_t, 349 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 350 351 352/* union of Request Descriptors */ 353typedef union _MPI2_REQUEST_DESCRIPTOR_UNION 354{ 355 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 356 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 357 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 358 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 359 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 360 U64 Words; 361} MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION, 362 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t; 363 364 365/* Reply Descriptors */ 366 367/* Default Reply Descriptor */ 368typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR 369{ 370 U8 ReplyFlags; /* 0x00 */ 371 U8 MSIxIndex; /* 0x01 */ 372 U16 DescriptorTypeDependent1; /* 0x02 */ 373 U32 DescriptorTypeDependent2; /* 0x04 */ 374} MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 375 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 376 377/* defines for the ReplyFlags field */ 378#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 379#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 380#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 381#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 382#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 383#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 384#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 385 386/* values for marking a reply descriptor as unused */ 387#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 388#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 389 390/* Address Reply Descriptor */ 391typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR 392{ 393 U8 ReplyFlags; /* 0x00 */ 394 U8 MSIxIndex; /* 0x01 */ 395 U16 SMID; /* 0x02 */ 396 U32 ReplyFrameAddress; /* 0x04 */ 397} MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 398 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 399 400#define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00) 401 402 403/* SCSI IO Success Reply Descriptor */ 404typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 405{ 406 U8 ReplyFlags; /* 0x00 */ 407 U8 MSIxIndex; /* 0x01 */ 408 U16 SMID; /* 0x02 */ 409 U16 TaskTag; /* 0x04 */ 410 U16 Reserved1; /* 0x06 */ 411} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 412 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 413 Mpi2SCSIIOSuccessReplyDescriptor_t, 414 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 415 416 417/* TargetAssist Success Reply Descriptor */ 418typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR 419{ 420 U8 ReplyFlags; /* 0x00 */ 421 U8 MSIxIndex; /* 0x01 */ 422 U16 SMID; /* 0x02 */ 423 U8 SequenceNumber; /* 0x04 */ 424 U8 Reserved1; /* 0x05 */ 425 U16 IoIndex; /* 0x06 */ 426} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 427 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 428 Mpi2TargetAssistSuccessReplyDescriptor_t, 429 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 430 431 432/* Target Command Buffer Reply Descriptor */ 433typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 434{ 435 U8 ReplyFlags; /* 0x00 */ 436 U8 MSIxIndex; /* 0x01 */ 437 U8 VP_ID; /* 0x02 */ 438 U8 Flags; /* 0x03 */ 439 U16 InitiatorDevHandle; /* 0x04 */ 440 U16 IoIndex; /* 0x06 */ 441} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 442 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 443 Mpi2TargetCommandBufferReplyDescriptor_t, 444 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 445 446/* defines for Flags field */ 447#define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F) 448 449 450/* RAID Accelerator Success Reply Descriptor */ 451typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { 452 U8 ReplyFlags; /* 0x00 */ 453 U8 MSIxIndex; /* 0x01 */ 454 U16 SMID; /* 0x02 */ 455 U32 Reserved; /* 0x04 */ 456} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 457 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 458 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 459 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 460 461 462/* union of Reply Descriptors */ 463typedef union _MPI2_REPLY_DESCRIPTORS_UNION 464{ 465 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 466 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 467 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 468 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 469 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 470 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 471 U64 Words; 472} MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 473 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 474 475 476 477/***************************************************************************** 478* 479* Message Functions 480* 481*****************************************************************************/ 482 483#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 484#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 485#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 486#define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 487#define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 488#define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 489#define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 490#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 491#define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 492#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 493#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 494#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 495#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 496#define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 497#define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 498#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 499#define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 500#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 501#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 502#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 503#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 504#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 505#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 506#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 507#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 508#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator*/ 509/* Host Based Discovery Action */ 510#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) 511/* Power Management Control */ 512#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) 513/* beginning of product-specific range */ 514#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) 515/* end of product-specific range */ 516#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) 517 518 519 520 521/* Doorbell functions */ 522#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 523#define MPI2_FUNCTION_HANDSHAKE (0x42) 524 525 526/***************************************************************************** 527* 528* IOC Status Values 529* 530*****************************************************************************/ 531 532/* mask for IOCStatus status value */ 533#define MPI2_IOCSTATUS_MASK (0x7FFF) 534 535/**************************************************************************** 536* Common IOCStatus values for all replies 537****************************************************************************/ 538 539#define MPI2_IOCSTATUS_SUCCESS (0x0000) 540#define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001) 541#define MPI2_IOCSTATUS_BUSY (0x0002) 542#define MPI2_IOCSTATUS_INVALID_SGL (0x0003) 543#define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) 544#define MPI2_IOCSTATUS_INVALID_VPID (0x0005) 545#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 546#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) 547#define MPI2_IOCSTATUS_INVALID_STATE (0x0008) 548#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 549 550/**************************************************************************** 551* Config IOCStatus values 552****************************************************************************/ 553 554#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 555#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 556#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 557#define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 558#define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 559#define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 560 561/**************************************************************************** 562* SCSI IO Reply 563****************************************************************************/ 564 565#define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 566#define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 567#define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 568#define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 569#define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 570#define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 571#define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 572#define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 573#define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 574#define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 575#define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 576#define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 577 578/**************************************************************************** 579* For use by SCSI Initiator and SCSI Target end-to-end data protection 580****************************************************************************/ 581 582#define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 583#define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 584#define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 585 586/**************************************************************************** 587* SCSI Target values 588****************************************************************************/ 589 590#define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 591#define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063) 592#define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 593#define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 594#define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 595#define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 596#define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 597#define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 598#define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 599#define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 600 601/**************************************************************************** 602* Serial Attached SCSI values 603****************************************************************************/ 604 605#define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 606#define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 607 608/**************************************************************************** 609* Diagnostic Buffer Post / Diagnostic Release values 610****************************************************************************/ 611 612#define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 613 614/**************************************************************************** 615* RAID Accelerator values 616****************************************************************************/ 617 618#define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0) 619 620/**************************************************************************** 621* IOCStatus flag to indicate that log info is available 622****************************************************************************/ 623 624#define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 625 626/**************************************************************************** 627* IOCLogInfo Types 628****************************************************************************/ 629 630#define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000) 631#define MPI2_IOCLOGINFO_TYPE_SHIFT (28) 632#define MPI2_IOCLOGINFO_TYPE_NONE (0x0) 633#define MPI2_IOCLOGINFO_TYPE_SCSI (0x1) 634#define MPI2_IOCLOGINFO_TYPE_FC (0x2) 635#define MPI2_IOCLOGINFO_TYPE_SAS (0x3) 636#define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4) 637#define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 638 639 640/***************************************************************************** 641* 642* Standard Message Structures 643* 644*****************************************************************************/ 645 646/**************************************************************************** 647* Request Message Header for all request messages 648****************************************************************************/ 649 650typedef struct _MPI2_REQUEST_HEADER 651{ 652 U16 FunctionDependent1; /* 0x00 */ 653 U8 ChainOffset; /* 0x02 */ 654 U8 Function; /* 0x03 */ 655 U16 FunctionDependent2; /* 0x04 */ 656 U8 FunctionDependent3; /* 0x06 */ 657 U8 MsgFlags; /* 0x07 */ 658 U8 VP_ID; /* 0x08 */ 659 U8 VF_ID; /* 0x09 */ 660 U16 Reserved1; /* 0x0A */ 661} MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER, 662 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t; 663 664 665/**************************************************************************** 666* Default Reply 667****************************************************************************/ 668 669typedef struct _MPI2_DEFAULT_REPLY 670{ 671 U16 FunctionDependent1; /* 0x00 */ 672 U8 MsgLength; /* 0x02 */ 673 U8 Function; /* 0x03 */ 674 U16 FunctionDependent2; /* 0x04 */ 675 U8 FunctionDependent3; /* 0x06 */ 676 U8 MsgFlags; /* 0x07 */ 677 U8 VP_ID; /* 0x08 */ 678 U8 VF_ID; /* 0x09 */ 679 U16 Reserved1; /* 0x0A */ 680 U16 FunctionDependent5; /* 0x0C */ 681 U16 IOCStatus; /* 0x0E */ 682 U32 IOCLogInfo; /* 0x10 */ 683} MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY, 684 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t; 685 686 687/* common version structure/union used in messages and configuration pages */ 688 689typedef struct _MPI2_VERSION_STRUCT 690{ 691 U8 Dev; /* 0x00 */ 692 U8 Unit; /* 0x01 */ 693 U8 Minor; /* 0x02 */ 694 U8 Major; /* 0x03 */ 695} MPI2_VERSION_STRUCT; 696 697typedef union _MPI2_VERSION_UNION 698{ 699 MPI2_VERSION_STRUCT Struct; 700 U32 Word; 701} MPI2_VERSION_UNION; 702 703 704/* LUN field defines, common to many structures */ 705#define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 706#define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 707#define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 708#define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 709#define MPI2_LUN_LEVEL_1_WORD (0xFF00) 710#define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00) 711 712 713/***************************************************************************** 714* 715* Fusion-MPT MPI Scatter Gather Elements 716* 717*****************************************************************************/ 718 719/**************************************************************************** 720* MPI Simple Element structures 721****************************************************************************/ 722 723typedef struct _MPI2_SGE_SIMPLE32 724{ 725 U32 FlagsLength; 726 U32 Address; 727} MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32, 728 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t; 729 730typedef struct _MPI2_SGE_SIMPLE64 731{ 732 U32 FlagsLength; 733 U64 Address; 734} MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64, 735 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t; 736 737typedef struct _MPI2_SGE_SIMPLE_UNION 738{ 739 U32 FlagsLength; 740 union 741 { 742 U32 Address32; 743 U64 Address64; 744 } u; 745} MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 746 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 747 748 749/**************************************************************************** 750* MPI Chain Element structures 751****************************************************************************/ 752 753typedef struct _MPI2_SGE_CHAIN32 754{ 755 U16 Length; 756 U8 NextChainOffset; 757 U8 Flags; 758 U32 Address; 759} MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32, 760 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t; 761 762typedef struct _MPI2_SGE_CHAIN64 763{ 764 U16 Length; 765 U8 NextChainOffset; 766 U8 Flags; 767 U64 Address; 768} MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64, 769 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t; 770 771typedef struct _MPI2_SGE_CHAIN_UNION 772{ 773 U16 Length; 774 U8 NextChainOffset; 775 U8 Flags; 776 union 777 { 778 U32 Address32; 779 U64 Address64; 780 } u; 781} MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 782 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 783 784 785/**************************************************************************** 786* MPI Transaction Context Element structures 787****************************************************************************/ 788 789typedef struct _MPI2_SGE_TRANSACTION32 790{ 791 U8 Reserved; 792 U8 ContextSize; 793 U8 DetailsLength; 794 U8 Flags; 795 U32 TransactionContext[1]; 796 U32 TransactionDetails[1]; 797} MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32, 798 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t; 799 800typedef struct _MPI2_SGE_TRANSACTION64 801{ 802 U8 Reserved; 803 U8 ContextSize; 804 U8 DetailsLength; 805 U8 Flags; 806 U32 TransactionContext[2]; 807 U32 TransactionDetails[1]; 808} MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64, 809 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t; 810 811typedef struct _MPI2_SGE_TRANSACTION96 812{ 813 U8 Reserved; 814 U8 ContextSize; 815 U8 DetailsLength; 816 U8 Flags; 817 U32 TransactionContext[3]; 818 U32 TransactionDetails[1]; 819} MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96, 820 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t; 821 822typedef struct _MPI2_SGE_TRANSACTION128 823{ 824 U8 Reserved; 825 U8 ContextSize; 826 U8 DetailsLength; 827 U8 Flags; 828 U32 TransactionContext[4]; 829 U32 TransactionDetails[1]; 830} MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128, 831 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128; 832 833typedef struct _MPI2_SGE_TRANSACTION_UNION 834{ 835 U8 Reserved; 836 U8 ContextSize; 837 U8 DetailsLength; 838 U8 Flags; 839 union 840 { 841 U32 TransactionContext32[1]; 842 U32 TransactionContext64[2]; 843 U32 TransactionContext96[3]; 844 U32 TransactionContext128[4]; 845 } u; 846 U32 TransactionDetails[1]; 847} MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION, 848 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t; 849 850 851/**************************************************************************** 852* MPI SGE union for IO SGL's 853****************************************************************************/ 854 855typedef struct _MPI2_MPI_SGE_IO_UNION 856{ 857 union 858 { 859 MPI2_SGE_SIMPLE_UNION Simple; 860 MPI2_SGE_CHAIN_UNION Chain; 861 } u; 862} MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION, 863 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t; 864 865 866/**************************************************************************** 867* MPI SGE union for SGL's with Simple and Transaction elements 868****************************************************************************/ 869 870typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION 871{ 872 union 873 { 874 MPI2_SGE_SIMPLE_UNION Simple; 875 MPI2_SGE_TRANSACTION_UNION Transaction; 876 } u; 877} MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION, 878 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t; 879 880 881/**************************************************************************** 882* All MPI SGE types union 883****************************************************************************/ 884 885typedef struct _MPI2_MPI_SGE_UNION 886{ 887 union 888 { 889 MPI2_SGE_SIMPLE_UNION Simple; 890 MPI2_SGE_CHAIN_UNION Chain; 891 MPI2_SGE_TRANSACTION_UNION Transaction; 892 } u; 893} MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION, 894 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t; 895 896 897/**************************************************************************** 898* MPI SGE field definition and masks 899****************************************************************************/ 900 901/* Flags field bit definitions */ 902 903#define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80) 904#define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40) 905#define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 906#define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08) 907#define MPI2_SGE_FLAGS_DIRECTION (0x04) 908#define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02) 909#define MPI2_SGE_FLAGS_END_OF_LIST (0x01) 910 911#define MPI2_SGE_FLAGS_SHIFT (24) 912 913#define MPI2_SGE_LENGTH_MASK (0x00FFFFFF) 914#define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 915 916/* Element Type */ 917 918#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) 919#define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 920#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) 921#define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30) 922 923/* Address location */ 924 925#define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 926 927/* Direction */ 928 929#define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00) 930#define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04) 931 932/* Address Size */ 933 934#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 935#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 936 937/* Context Size */ 938 939#define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00) 940#define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02) 941#define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04) 942#define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06) 943 944#define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 945#define MPI2_SGE_CHAIN_OFFSET_SHIFT (16) 946 947/**************************************************************************** 948* MPI SGE operation Macros 949****************************************************************************/ 950 951/* SIMPLE FlagsLength manipulations... */ 952#define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT) 953#define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT) 954#define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK) 955#define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK) 956 957#define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l)) 958 959#define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength) 960#define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength) 961#define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l) 962 963/* CAUTION - The following are READ-MODIFY-WRITE! */ 964#define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f) 965#define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l) 966 967#define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT) 968 969 970/***************************************************************************** 971* 972* Fusion-MPT IEEE Scatter Gather Elements 973* 974*****************************************************************************/ 975 976/**************************************************************************** 977* IEEE Simple Element structures 978****************************************************************************/ 979 980typedef struct _MPI2_IEEE_SGE_SIMPLE32 981{ 982 U32 Address; 983 U32 FlagsLength; 984} MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 985 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 986 987typedef struct _MPI2_IEEE_SGE_SIMPLE64 988{ 989 U64 Address; 990 U32 Length; 991 U16 Reserved1; 992 U8 Reserved2; 993 U8 Flags; 994} MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 995 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 996 997typedef union _MPI2_IEEE_SGE_SIMPLE_UNION 998{ 999 MPI2_IEEE_SGE_SIMPLE32 Simple32; 1000 MPI2_IEEE_SGE_SIMPLE64 Simple64; 1001} MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 1002 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 1003 1004 1005/**************************************************************************** 1006* IEEE Chain Element structures 1007****************************************************************************/ 1008 1009typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 1010 1011typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 1012 1013typedef union _MPI2_IEEE_SGE_CHAIN_UNION 1014{ 1015 MPI2_IEEE_SGE_CHAIN32 Chain32; 1016 MPI2_IEEE_SGE_CHAIN64 Chain64; 1017} MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 1018 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 1019 1020 1021/**************************************************************************** 1022* All IEEE SGE types union 1023****************************************************************************/ 1024 1025typedef struct _MPI2_IEEE_SGE_UNION 1026{ 1027 union 1028 { 1029 MPI2_IEEE_SGE_SIMPLE_UNION Simple; 1030 MPI2_IEEE_SGE_CHAIN_UNION Chain; 1031 } u; 1032} MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION, 1033 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t; 1034 1035 1036/**************************************************************************** 1037* IEEE SGE field definitions and masks 1038****************************************************************************/ 1039 1040/* Flags field bit definitions */ 1041 1042#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1043 1044#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1045 1046#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1047 1048/* Element Type */ 1049 1050#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1051#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1052 1053/* Data Location Address Space */ 1054 1055#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1056#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1057#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1058#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1059#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1060 1061 1062/**************************************************************************** 1063* IEEE SGE operation Macros 1064****************************************************************************/ 1065 1066/* SIMPLE FlagsLength manipulations... */ 1067#define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) 1068#define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT) 1069#define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) 1070 1071#define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l)) 1072 1073#define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength) 1074#define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength) 1075#define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l) 1076 1077/* CAUTION - The following are READ-MODIFY-WRITE! */ 1078#define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f) 1079#define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l) 1080 1081 1082 1083 1084/***************************************************************************** 1085* 1086* Fusion-MPT MPI/IEEE Scatter Gather Unions 1087* 1088*****************************************************************************/ 1089 1090typedef union _MPI2_SIMPLE_SGE_UNION 1091{ 1092 MPI2_SGE_SIMPLE_UNION MpiSimple; 1093 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1094} MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION, 1095 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t; 1096 1097 1098typedef union _MPI2_SGE_IO_UNION 1099{ 1100 MPI2_SGE_SIMPLE_UNION MpiSimple; 1101 MPI2_SGE_CHAIN_UNION MpiChain; 1102 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1103 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1104} MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 1105 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 1106 1107 1108/**************************************************************************** 1109* 1110* Values for SGLFlags field, used in many request messages with an SGL 1111* 1112****************************************************************************/ 1113 1114/* values for MPI SGL Data Location Address Space subfield */ 1115#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) 1116#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) 1117#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) 1118#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) 1119#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) 1120/* values for SGL Type subfield */ 1121#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) 1122#define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) 1123#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) 1124#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) 1125 1126 1127#endif 1128