1/* Modified by Broadcom Corp. Portions Copyright (c) Broadcom Corp, 2012. */ 2/* 3 * probe.c - PCI detection and setup code 4 */ 5 6#include <linux/kernel.h> 7#include <linux/delay.h> 8#include <linux/init.h> 9#include <linux/pci.h> 10#include <linux/slab.h> 11#include <linux/module.h> 12#include <linux/cpumask.h> 13#include <linux/pci-aspm.h> 14#include "pci.h" 15 16#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 17#define CARDBUS_RESERVE_BUSNR 3 18 19/* Ugh. Need to stop exporting this to modules. */ 20LIST_HEAD(pci_root_buses); 21EXPORT_SYMBOL(pci_root_buses); 22 23 24static int find_anything(struct device *dev, void *data) 25{ 26 return 1; 27} 28 29/* 30 * Some device drivers need know if pci is initiated. 31 * Basically, we think pci is not initiated when there 32 * is no device to be found on the pci_bus_type. 33 */ 34int no_pci_devices(void) 35{ 36 struct device *dev; 37 int no_devices; 38 39 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); 40 no_devices = (dev == NULL); 41 put_device(dev); 42 return no_devices; 43} 44EXPORT_SYMBOL(no_pci_devices); 45 46/* 47 * PCI Bus Class Devices 48 */ 49static ssize_t pci_bus_show_cpuaffinity(struct device *dev, 50 int type, 51 struct device_attribute *attr, 52 char *buf) 53{ 54 int ret; 55 const struct cpumask *cpumask; 56 57 cpumask = cpumask_of_pcibus(to_pci_bus(dev)); 58 ret = type? 59 cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask) : 60 cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask); 61 buf[ret++] = '\n'; 62 buf[ret] = '\0'; 63 return ret; 64} 65 66static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev, 67 struct device_attribute *attr, 68 char *buf) 69{ 70 return pci_bus_show_cpuaffinity(dev, 0, attr, buf); 71} 72 73static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev, 74 struct device_attribute *attr, 75 char *buf) 76{ 77 return pci_bus_show_cpuaffinity(dev, 1, attr, buf); 78} 79 80DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL); 81DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL); 82 83/* 84 * PCI Bus Class 85 */ 86static void release_pcibus_dev(struct device *dev) 87{ 88 struct pci_bus *pci_bus = to_pci_bus(dev); 89 90 if (pci_bus->bridge) 91 put_device(pci_bus->bridge); 92 pci_bus_remove_resources(pci_bus); 93 kfree(pci_bus); 94} 95 96static struct class pcibus_class = { 97 .name = "pci_bus", 98 .dev_release = &release_pcibus_dev, 99}; 100 101static int __init pcibus_class_init(void) 102{ 103 return class_register(&pcibus_class); 104} 105postcore_initcall(pcibus_class_init); 106 107/* 108 * Translate the low bits of the PCI base 109 * to the resource type 110 */ 111static inline unsigned int pci_calc_resource_flags(unsigned int flags) 112{ 113 if (flags & PCI_BASE_ADDRESS_SPACE_IO) 114 return IORESOURCE_IO; 115 116 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) 117 return IORESOURCE_MEM | IORESOURCE_PREFETCH; 118 119 return IORESOURCE_MEM; 120} 121 122static u64 pci_size(u64 base, u64 maxbase, u64 mask) 123{ 124 u64 size = mask & maxbase; /* Find the significant bits */ 125 if (!size) 126 return 0; 127 128 /* Get the lowest of them to find the decode size, and 129 from that the extent. */ 130 size = (size & ~(size-1)) - 1; 131 132 /* base == maxbase can be valid only if the BAR has 133 already been programmed with all 1s. */ 134 if (base == maxbase && ((base | size) & mask) != mask) 135 return 0; 136 137 return size; 138} 139 140static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar) 141{ 142 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 143 res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; 144 return pci_bar_io; 145 } 146 147 res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; 148 149 if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) 150 return pci_bar_mem64; 151 return pci_bar_mem32; 152} 153 154/** 155 * pci_read_base - read a PCI BAR 156 * @dev: the PCI device 157 * @type: type of the BAR 158 * @res: resource buffer to be filled in 159 * @pos: BAR position in the config space 160 * 161 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. 162 */ 163int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 164 struct resource *res, unsigned int pos) 165{ 166 u32 l, sz, mask; 167 u16 orig_cmd; 168 169 mask = type ? PCI_ROM_ADDRESS_MASK : ~0; 170 171 if (!dev->mmio_always_on) { 172 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); 173 pci_write_config_word(dev, PCI_COMMAND, 174 orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); 175 } 176 177 res->name = pci_name(dev); 178 179 pci_read_config_dword(dev, pos, &l); 180 pci_write_config_dword(dev, pos, l | mask); 181 pci_read_config_dword(dev, pos, &sz); 182 pci_write_config_dword(dev, pos, l); 183 184 if (!dev->mmio_always_on) 185 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); 186 187 /* 188 * All bits set in sz means the device isn't working properly. 189 * If the BAR isn't implemented, all bits must be 0. If it's a 190 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit 191 * 1 must be clear. 192 */ 193 if (!sz || sz == 0xffffffff) 194 goto fail; 195 196 /* 197 * I don't know how l can have all bits set. Copied from old code. 198 * Maybe it fixes a bug on some ancient platform. 199 */ 200 if (l == 0xffffffff) 201 l = 0; 202 203 if (type == pci_bar_unknown) { 204 type = decode_bar(res, l); 205 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; 206 if (type == pci_bar_io) { 207 l &= PCI_BASE_ADDRESS_IO_MASK; 208 mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT; 209 } else { 210 l &= PCI_BASE_ADDRESS_MEM_MASK; 211 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; 212 } 213 } else { 214 res->flags |= (l & IORESOURCE_ROM_ENABLE); 215 l &= PCI_ROM_ADDRESS_MASK; 216 mask = (u32)PCI_ROM_ADDRESS_MASK; 217 } 218 219 if (type == pci_bar_mem64) { 220 u64 l64 = l; 221 u64 sz64 = sz; 222 u64 mask64 = mask | (u64)~0 << 32; 223 224 pci_read_config_dword(dev, pos + 4, &l); 225 pci_write_config_dword(dev, pos + 4, ~0); 226 pci_read_config_dword(dev, pos + 4, &sz); 227 pci_write_config_dword(dev, pos + 4, l); 228 229 l64 |= ((u64)l << 32); 230 sz64 |= ((u64)sz << 32); 231 232 sz64 = pci_size(l64, sz64, mask64); 233 234 if (!sz64) 235 goto fail; 236 237 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) { 238 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n", 239 pos); 240 goto fail; 241 } 242 243 res->flags |= IORESOURCE_MEM_64; 244 if ((sizeof(resource_size_t) < 8) && l) { 245 /* Address above 32-bit boundary; disable the BAR */ 246 pci_write_config_dword(dev, pos, 0); 247 pci_write_config_dword(dev, pos + 4, 0); 248 res->start = 0; 249 res->end = sz64; 250 } else { 251 res->start = l64; 252 res->end = l64 + sz64; 253 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", 254 pos, res); 255 } 256 } else { 257 sz = pci_size(l, sz, mask); 258 259 if (!sz) 260 goto fail; 261 262 res->start = l; 263 res->end = l + sz; 264 265 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res); 266 } 267 268 out: 269 return (type == pci_bar_mem64) ? 1 : 0; 270 fail: 271 res->flags = 0; 272 goto out; 273} 274 275static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 276{ 277 unsigned int pos, reg; 278 279 for (pos = 0; pos < howmany; pos++) { 280 struct resource *res = &dev->resource[pos]; 281 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 282 pos += __pci_read_base(dev, pci_bar_unknown, res, reg); 283 } 284 285 if (rom) { 286 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; 287 dev->rom_base_reg = rom; 288 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 289 IORESOURCE_READONLY | IORESOURCE_CACHEABLE | 290 IORESOURCE_SIZEALIGN; 291 __pci_read_base(dev, pci_bar_mem32, res, rom); 292 } 293} 294 295static void __devinit pci_read_bridge_io(struct pci_bus *child) 296{ 297 struct pci_dev *dev = child->self; 298 u8 io_base_lo, io_limit_lo; 299 unsigned long base, limit; 300 struct resource *res; 301 302 res = child->resource[0]; 303 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 304 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 305 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; 306 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; 307 308 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 309 u16 io_base_hi, io_limit_hi; 310 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 311 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 312 base |= (io_base_hi << 16); 313 limit |= (io_limit_hi << 16); 314 } 315 316 if (base && base <= limit) { 317 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 318 if (!res->start) 319 res->start = base; 320 if (!res->end) 321 res->end = limit + 0xfff; 322 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); 323 } else { 324 dev_printk(KERN_DEBUG, &dev->dev, 325 " bridge window [io %#06lx-%#06lx] (disabled)\n", 326 base, limit); 327 } 328} 329 330static void __devinit pci_read_bridge_mmio(struct pci_bus *child) 331{ 332 struct pci_dev *dev = child->self; 333 u16 mem_base_lo, mem_limit_lo; 334 unsigned long base, limit; 335 struct resource *res; 336 337 res = child->resource[1]; 338 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 339 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 340 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 341 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 342 if (base && base <= limit) { 343 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 344 res->start = base; 345 res->end = limit + 0xfffff; 346 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); 347 } else { 348 dev_printk(KERN_DEBUG, &dev->dev, 349 " bridge window [mem %#010lx-%#010lx] (disabled)\n", 350 base, limit + 0xfffff); 351 } 352} 353 354static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child) 355{ 356 struct pci_dev *dev = child->self; 357 u16 mem_base_lo, mem_limit_lo; 358 unsigned long base, limit; 359 struct resource *res; 360 361 res = child->resource[2]; 362 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 363 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 364 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 365 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 366 367 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 368 u32 mem_base_hi, mem_limit_hi; 369 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 370 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 371 372 /* 373 * Some bridges set the base > limit by default, and some 374 * (broken) BIOSes do not initialize them. If we find 375 * this, just assume they are not being used. 376 */ 377 if (mem_base_hi <= mem_limit_hi) { 378#if BITS_PER_LONG == 64 379 base |= ((long) mem_base_hi) << 32; 380 limit |= ((long) mem_limit_hi) << 32; 381#else 382 if (mem_base_hi || mem_limit_hi) { 383 dev_err(&dev->dev, "can't handle 64-bit " 384 "address space for bridge\n"); 385 return; 386 } 387#endif 388 } 389 } 390 if (base && base <= limit) { 391 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | 392 IORESOURCE_MEM | IORESOURCE_PREFETCH; 393 if (res->flags & PCI_PREF_RANGE_TYPE_64) 394 res->flags |= IORESOURCE_MEM_64; 395 res->start = base; 396 res->end = limit + 0xfffff; 397 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); 398 } else { 399 dev_printk(KERN_DEBUG, &dev->dev, 400 " bridge window [mem %#010lx-%#010lx pref] (disabled)\n", 401 base, limit + 0xfffff); 402 } 403} 404 405void __devinit pci_read_bridge_bases(struct pci_bus *child) 406{ 407 struct pci_dev *dev = child->self; 408 struct resource *res; 409 int i; 410 411 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 412 return; 413 414 dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n", 415 child->secondary, child->subordinate, 416 dev->transparent ? " (subtractive decode)" : ""); 417 418 pci_bus_remove_resources(child); 419 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 420 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; 421 422 pci_read_bridge_io(child); 423 pci_read_bridge_mmio(child); 424 pci_read_bridge_mmio_pref(child); 425 426 if (dev->transparent) { 427 pci_bus_for_each_resource(child->parent, res, i) { 428 if (res) { 429 pci_bus_add_resource(child, res, 430 PCI_SUBTRACTIVE_DECODE); 431 dev_printk(KERN_DEBUG, &dev->dev, 432 " bridge window %pR (subtractive decode)\n", 433 res); 434 } 435 } 436 } 437} 438 439static struct pci_bus * pci_alloc_bus(void) 440{ 441 struct pci_bus *b; 442 443 b = kzalloc(sizeof(*b), GFP_KERNEL); 444 if (b) { 445 INIT_LIST_HEAD(&b->node); 446 INIT_LIST_HEAD(&b->children); 447 INIT_LIST_HEAD(&b->devices); 448 INIT_LIST_HEAD(&b->slots); 449 INIT_LIST_HEAD(&b->resources); 450 b->max_bus_speed = PCI_SPEED_UNKNOWN; 451 b->cur_bus_speed = PCI_SPEED_UNKNOWN; 452 } 453 return b; 454} 455 456static unsigned char pcix_bus_speed[] = { 457 PCI_SPEED_UNKNOWN, /* 0 */ 458 PCI_SPEED_66MHz_PCIX, /* 1 */ 459 PCI_SPEED_100MHz_PCIX, /* 2 */ 460 PCI_SPEED_133MHz_PCIX, /* 3 */ 461 PCI_SPEED_UNKNOWN, /* 4 */ 462 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ 463 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ 464 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ 465 PCI_SPEED_UNKNOWN, /* 8 */ 466 PCI_SPEED_66MHz_PCIX_266, /* 9 */ 467 PCI_SPEED_100MHz_PCIX_266, /* A */ 468 PCI_SPEED_133MHz_PCIX_266, /* B */ 469 PCI_SPEED_UNKNOWN, /* C */ 470 PCI_SPEED_66MHz_PCIX_533, /* D */ 471 PCI_SPEED_100MHz_PCIX_533, /* E */ 472 PCI_SPEED_133MHz_PCIX_533 /* F */ 473}; 474 475static unsigned char pcie_link_speed[] = { 476 PCI_SPEED_UNKNOWN, /* 0 */ 477 PCIE_SPEED_2_5GT, /* 1 */ 478 PCIE_SPEED_5_0GT, /* 2 */ 479 PCIE_SPEED_8_0GT, /* 3 */ 480 PCI_SPEED_UNKNOWN, /* 4 */ 481 PCI_SPEED_UNKNOWN, /* 5 */ 482 PCI_SPEED_UNKNOWN, /* 6 */ 483 PCI_SPEED_UNKNOWN, /* 7 */ 484 PCI_SPEED_UNKNOWN, /* 8 */ 485 PCI_SPEED_UNKNOWN, /* 9 */ 486 PCI_SPEED_UNKNOWN, /* A */ 487 PCI_SPEED_UNKNOWN, /* B */ 488 PCI_SPEED_UNKNOWN, /* C */ 489 PCI_SPEED_UNKNOWN, /* D */ 490 PCI_SPEED_UNKNOWN, /* E */ 491 PCI_SPEED_UNKNOWN /* F */ 492}; 493 494void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) 495{ 496 bus->cur_bus_speed = pcie_link_speed[linksta & 0xf]; 497} 498EXPORT_SYMBOL_GPL(pcie_update_link_speed); 499 500static unsigned char agp_speeds[] = { 501 AGP_UNKNOWN, 502 AGP_1X, 503 AGP_2X, 504 AGP_4X, 505 AGP_8X 506}; 507 508static enum pci_bus_speed agp_speed(int agp3, int agpstat) 509{ 510 int index = 0; 511 512 if (agpstat & 4) 513 index = 3; 514 else if (agpstat & 2) 515 index = 2; 516 else if (agpstat & 1) 517 index = 1; 518 else 519 goto out; 520 521 if (agp3) { 522 index += 2; 523 if (index == 5) 524 index = 0; 525 } 526 527 out: 528 return agp_speeds[index]; 529} 530 531 532static void pci_set_bus_speed(struct pci_bus *bus) 533{ 534 struct pci_dev *bridge = bus->self; 535 int pos; 536 537 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); 538 if (!pos) 539 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); 540 if (pos) { 541 u32 agpstat, agpcmd; 542 543 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); 544 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); 545 546 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); 547 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); 548 } 549 550 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 551 if (pos) { 552 u16 status; 553 enum pci_bus_speed max; 554 pci_read_config_word(bridge, pos + 2, &status); 555 556 if (status & 0x8000) { 557 max = PCI_SPEED_133MHz_PCIX_533; 558 } else if (status & 0x4000) { 559 max = PCI_SPEED_133MHz_PCIX_266; 560 } else if (status & 0x0002) { 561 if (((status >> 12) & 0x3) == 2) { 562 max = PCI_SPEED_133MHz_PCIX_ECC; 563 } else { 564 max = PCI_SPEED_133MHz_PCIX; 565 } 566 } else { 567 max = PCI_SPEED_66MHz_PCIX; 568 } 569 570 bus->max_bus_speed = max; 571 bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf]; 572 573 return; 574 } 575 576 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP); 577 if (pos) { 578 u32 linkcap; 579 u16 linksta; 580 581 pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap); 582 bus->max_bus_speed = pcie_link_speed[linkcap & 0xf]; 583 584 pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta); 585 pcie_update_link_speed(bus, linksta); 586 } 587} 588 589 590static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, 591 struct pci_dev *bridge, int busnr) 592{ 593 struct pci_bus *child; 594 int i; 595 596 /* 597 * Allocate a new bus, and inherit stuff from the parent.. 598 */ 599 child = pci_alloc_bus(); 600 if (!child) 601 return NULL; 602 603 child->parent = parent; 604 child->ops = parent->ops; 605 child->sysdata = parent->sysdata; 606 child->bus_flags = parent->bus_flags; 607 608 /* initialize some portions of the bus device, but don't register it 609 * now as the parent is not properly set up yet. This device will get 610 * registered later in pci_bus_add_devices() 611 */ 612 child->dev.class = &pcibus_class; 613 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); 614 615 /* 616 * Set up the primary, secondary and subordinate 617 * bus numbers. 618 */ 619 child->number = child->secondary = busnr; 620 child->primary = parent->secondary; 621 child->subordinate = 0xff; 622 623 if (!bridge) 624 return child; 625 626 child->self = bridge; 627 child->bridge = get_device(&bridge->dev); 628 629 pci_set_bus_speed(child); 630 631 /* Set up default resource pointers and names.. */ 632 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 633 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 634 child->resource[i]->name = child->name; 635 } 636 bridge->subordinate = child; 637 638 return child; 639} 640 641struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) 642{ 643 struct pci_bus *child; 644 645 child = pci_alloc_child_bus(parent, dev, busnr); 646 if (child) { 647 down_write(&pci_bus_sem); 648 list_add_tail(&child->node, &parent->children); 649 up_write(&pci_bus_sem); 650 } 651 return child; 652} 653 654static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max) 655{ 656 struct pci_bus *parent = child->parent; 657 658 /* Attempts to fix that up are really dangerous unless 659 we're going to re-assign all bus numbers. */ 660 if (!pcibios_assign_all_busses()) 661 return; 662 663 while (parent->parent && parent->subordinate < max) { 664 parent->subordinate = max; 665 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max); 666 parent = parent->parent; 667 } 668} 669 670/* 671 * If it's a bridge, configure it and scan the bus behind it. 672 * For CardBus bridges, we don't scan behind as the devices will 673 * be handled by the bridge driver itself. 674 * 675 * We need to process bridges in two passes -- first we scan those 676 * already configured by the BIOS and after we are done with all of 677 * them, we proceed to assigning numbers to the remaining buses in 678 * order to avoid overlaps between old and new bus numbers. 679 */ 680int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) 681{ 682 struct pci_bus *child; 683 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 684 u32 buses, i, j = 0; 685 u16 bctl; 686 u8 primary, secondary, subordinate; 687 int broken = 0; 688 689 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 690 primary = buses & 0xFF; 691 secondary = (buses >> 8) & 0xFF; 692 subordinate = (buses >> 16) & 0xFF; 693 694 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", 695 secondary, subordinate, pass); 696 697 /* Check if setup is sensible at all */ 698 if (!pass && 699 (primary != bus->number || secondary <= bus->number)) { 700 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n"); 701 broken = 1; 702 } 703 704 /* Disable MasterAbortMode during probing to avoid reporting 705 of bus errors (in some architectures) */ 706 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 707 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 708 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 709 710 if ((secondary || subordinate) && !pcibios_assign_all_busses() && 711 !is_cardbus && !broken) { 712 unsigned int cmax; 713 /* 714 * Bus already configured by firmware, process it in the first 715 * pass and just note the configuration. 716 */ 717 if (pass) 718 goto out; 719 720 /* 721 * If we already got to this bus through a different bridge, 722 * don't re-add it. This can happen with the i450NX chipset. 723 * 724 * However, we continue to descend down the hierarchy and 725 * scan remaining child buses. 726 */ 727 child = pci_find_bus(pci_domain_nr(bus), secondary); 728 if (!child) { 729 child = pci_add_new_bus(bus, dev, secondary); 730 if (!child) 731 goto out; 732 child->primary = primary; 733 child->subordinate = subordinate; 734 child->bridge_ctl = bctl; 735 } 736 737 cmax = pci_scan_child_bus(child); 738 if (cmax > max) 739 max = cmax; 740 if (child->subordinate > max) 741 max = child->subordinate; 742 } else { 743 /* 744 * We need to assign a number to this bus which we always 745 * do in the second pass. 746 */ 747 if (!pass) { 748 if (pcibios_assign_all_busses() || broken) 749 /* Temporarily disable forwarding of the 750 configuration cycles on all bridges in 751 this bus segment to avoid possible 752 conflicts in the second pass between two 753 bridges programmed with overlapping 754 bus ranges. */ 755 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 756 buses & ~0xffffff); 757 goto out; 758 } 759 760 /* Clear errors */ 761 pci_write_config_word(dev, PCI_STATUS, 0xffff); 762 763 /* Prevent assigning a bus number that already exists. 764 * This can happen when a bridge is hot-plugged */ 765 if (pci_find_bus(pci_domain_nr(bus), max+1)) 766 goto out; 767 child = pci_add_new_bus(bus, dev, ++max); 768 buses = (buses & 0xff000000) 769 | ((unsigned int)(child->primary) << 0) 770 | ((unsigned int)(child->secondary) << 8) 771 | ((unsigned int)(child->subordinate) << 16); 772 773 /* 774 * yenta.c forces a secondary latency timer of 176. 775 * Copy that behaviour here. 776 */ 777 if (is_cardbus) { 778 buses &= ~0xff000000; 779 buses |= CARDBUS_LATENCY_TIMER << 24; 780 } 781 782 /* 783 * We need to blast all three values with a single write. 784 */ 785 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 786 787 if (!is_cardbus) { 788 child->bridge_ctl = bctl; 789 /* 790 * Adjust subordinate busnr in parent buses. 791 * We do this before scanning for children because 792 * some devices may not be detected if the bios 793 * was lazy. 794 */ 795 pci_fixup_parent_subordinate_busnr(child, max); 796 /* Now we can scan all subordinate buses... */ 797 max = pci_scan_child_bus(child); 798 /* 799 * now fix it up again since we have found 800 * the real value of max. 801 */ 802 pci_fixup_parent_subordinate_busnr(child, max); 803 } else { 804 /* 805 * For CardBus bridges, we leave 4 bus numbers 806 * as cards with a PCI-to-PCI bridge can be 807 * inserted later. 808 */ 809 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) { 810 struct pci_bus *parent = bus; 811 if (pci_find_bus(pci_domain_nr(bus), 812 max+i+1)) 813 break; 814 while (parent->parent) { 815 if ((!pcibios_assign_all_busses()) && 816 (parent->subordinate > max) && 817 (parent->subordinate <= max+i)) { 818 j = 1; 819 } 820 parent = parent->parent; 821 } 822 if (j) { 823 /* 824 * Often, there are two cardbus bridges 825 * -- try to leave one valid bus number 826 * for each one. 827 */ 828 i /= 2; 829 break; 830 } 831 } 832 max += i; 833 pci_fixup_parent_subordinate_busnr(child, max); 834 } 835 /* 836 * Set the subordinate bus number to its real value. 837 */ 838 child->subordinate = max; 839 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 840 } 841 842 sprintf(child->name, 843 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), 844 pci_domain_nr(bus), child->number); 845 846 /* Has only triggered on CardBus, fixup is in yenta_socket */ 847 while (bus->parent) { 848 if ((child->subordinate > bus->subordinate) || 849 (child->number > bus->subordinate) || 850 (child->number < bus->number) || 851 (child->subordinate < bus->number)) { 852 dev_info(&child->dev, "[bus %02x-%02x] %s " 853 "hidden behind%s bridge %s [bus %02x-%02x]\n", 854 child->number, child->subordinate, 855 (bus->number > child->subordinate && 856 bus->subordinate < child->number) ? 857 "wholly" : "partially", 858 bus->self->transparent ? " transparent" : "", 859 dev_name(&bus->dev), 860 bus->number, bus->subordinate); 861 } 862 bus = bus->parent; 863 } 864 865out: 866 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); 867 868 return max; 869} 870 871/* 872 * Read interrupt line and base address registers. 873 * The architecture-dependent code can tweak these, of course. 874 */ 875static void pci_read_irq(struct pci_dev *dev) 876{ 877 unsigned char irq; 878 879 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); 880 dev->pin = irq; 881 if (irq) 882 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 883 dev->irq = irq; 884} 885 886void set_pcie_port_type(struct pci_dev *pdev) 887{ 888 int pos; 889 u16 reg16; 890 891 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 892 if (!pos) 893 return; 894 pdev->is_pcie = 1; 895 pdev->pcie_cap = pos; 896 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 897 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; 898} 899 900void set_pcie_hotplug_bridge(struct pci_dev *pdev) 901{ 902 int pos; 903 u16 reg16; 904 u32 reg32; 905 906 pos = pci_pcie_cap(pdev); 907 if (!pos) 908 return; 909 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 910 if (!(reg16 & PCI_EXP_FLAGS_SLOT)) 911 return; 912 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32); 913 if (reg32 & PCI_EXP_SLTCAP_HPC) 914 pdev->is_hotplug_bridge = 1; 915} 916 917#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 918 919/** 920 * pci_setup_device - fill in class and map information of a device 921 * @dev: the device structure to fill 922 * 923 * Initialize the device structure with information about the device's 924 * vendor,class,memory and IO-space addresses,IRQ lines etc. 925 * Called at initialisation of the PCI subsystem and by CardBus services. 926 * Returns 0 on success and negative if unknown type of device (not normal, 927 * bridge or CardBus). 928 */ 929int pci_setup_device(struct pci_dev *dev) 930{ 931 u32 class; 932 u8 hdr_type; 933 struct pci_slot *slot; 934 int pos = 0; 935 936 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type)) 937 return -EIO; 938 939 dev->sysdata = dev->bus->sysdata; 940 dev->dev.parent = dev->bus->bridge; 941 dev->dev.bus = &pci_bus_type; 942 dev->hdr_type = hdr_type & 0x7f; 943 dev->multifunction = !!(hdr_type & 0x80); 944 dev->error_state = pci_channel_io_normal; 945 set_pcie_port_type(dev); 946 947 list_for_each_entry(slot, &dev->bus->slots, list) 948 if (PCI_SLOT(dev->devfn) == slot->number) 949 dev->slot = slot; 950 951 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 952 set this higher, assuming the system even supports it. */ 953 dev->dma_mask = 0xffffffff; 954 955 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 956 dev->bus->number, PCI_SLOT(dev->devfn), 957 PCI_FUNC(dev->devfn)); 958 959 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 960 dev->revision = class & 0xff; 961 class >>= 8; /* upper 3 bytes */ 962 dev->class = class; 963 class >>= 8; 964 965 dev_dbg(&dev->dev, "found [%04x:%04x] class %06x header type %02x\n", 966 dev->vendor, dev->device, class, dev->hdr_type); 967 968 /* need to have dev->class ready */ 969 dev->cfg_size = pci_cfg_space_size(dev); 970 971 /* "Unknown power state" */ 972 dev->current_state = PCI_UNKNOWN; 973 974 /* Early fixups, before probing the BARs */ 975 pci_fixup_device(pci_fixup_early, dev); 976 /* device class may be changed after fixup */ 977 class = dev->class >> 8; 978 979 switch (dev->hdr_type) { /* header type */ 980 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 981 if (class == PCI_CLASS_BRIDGE_PCI) 982 goto bad; 983 pci_read_irq(dev); 984 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 985 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 986 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); 987 988 /* 989 * Do the ugly legacy mode stuff here rather than broken chip 990 * quirk code. Legacy mode ATA controllers have fixed 991 * addresses. These are not always echoed in BAR0-3, and 992 * BAR0-3 in a few cases contain junk! 993 */ 994 if (class == PCI_CLASS_STORAGE_IDE) { 995 u8 progif; 996 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 997 if ((progif & 1) == 0) { 998 dev->resource[0].start = 0x1F0; 999 dev->resource[0].end = 0x1F7; 1000 dev->resource[0].flags = LEGACY_IO_RESOURCE; 1001 dev->resource[1].start = 0x3F6; 1002 dev->resource[1].end = 0x3F6; 1003 dev->resource[1].flags = LEGACY_IO_RESOURCE; 1004 } 1005 if ((progif & 4) == 0) { 1006 dev->resource[2].start = 0x170; 1007 dev->resource[2].end = 0x177; 1008 dev->resource[2].flags = LEGACY_IO_RESOURCE; 1009 dev->resource[3].start = 0x376; 1010 dev->resource[3].end = 0x376; 1011 dev->resource[3].flags = LEGACY_IO_RESOURCE; 1012 } 1013 } 1014 break; 1015 1016 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 1017 if (class != PCI_CLASS_BRIDGE_PCI) 1018 goto bad; 1019 /* The PCI-to-PCI bridge spec requires that subtractive 1020 decoding (i.e. transparent) bridge must have programming 1021 interface code of 0x01. */ 1022 pci_read_irq(dev); 1023 dev->transparent = ((dev->class & 0xff) == 1); 1024 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 1025 set_pcie_hotplug_bridge(dev); 1026 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); 1027 if (pos) { 1028 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); 1029 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); 1030 } 1031 break; 1032 1033 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 1034 if (class != PCI_CLASS_BRIDGE_CARDBUS) 1035 goto bad; 1036 pci_read_irq(dev); 1037 pci_read_bases(dev, 1, 0); 1038 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 1039 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 1040 break; 1041 1042 default: /* unknown header */ 1043 dev_err(&dev->dev, "unknown header type %02x, " 1044 "ignoring device\n", dev->hdr_type); 1045 return -EIO; 1046 1047 bad: 1048 dev_err(&dev->dev, "ignoring class %02x (doesn't match header " 1049 "type %02x)\n", class, dev->hdr_type); 1050 dev->class = PCI_CLASS_NOT_DEFINED; 1051 } 1052 1053 /* We found a fine healthy device, go go go... */ 1054 return 0; 1055} 1056 1057static void pci_release_capabilities(struct pci_dev *dev) 1058{ 1059 pci_vpd_release(dev); 1060 pci_iov_release(dev); 1061} 1062 1063/** 1064 * pci_release_dev - free a pci device structure when all users of it are finished. 1065 * @dev: device that's been disconnected 1066 * 1067 * Will be called only by the device core when all users of this pci device are 1068 * done. 1069 */ 1070static void pci_release_dev(struct device *dev) 1071{ 1072 struct pci_dev *pci_dev; 1073 1074 pci_dev = to_pci_dev(dev); 1075 pci_release_capabilities(pci_dev); 1076 kfree(pci_dev); 1077} 1078 1079/** 1080 * pci_cfg_space_size - get the configuration space size of the PCI device. 1081 * @dev: PCI device 1082 * 1083 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 1084 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 1085 * access it. Maybe we don't have a way to generate extended config space 1086 * accesses, or the device is behind a reverse Express bridge. So we try 1087 * reading the dword at 0x100 which must either be 0 or a valid extended 1088 * capability header. 1089 */ 1090int pci_cfg_space_size_ext(struct pci_dev *dev) 1091{ 1092 u32 status; 1093 int pos = PCI_CFG_SPACE_SIZE; 1094 1095 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) 1096 goto fail; 1097 if (status == 0xffffffff) 1098 goto fail; 1099 1100 return PCI_CFG_SPACE_EXP_SIZE; 1101 1102 fail: 1103 return PCI_CFG_SPACE_SIZE; 1104} 1105 1106int pci_cfg_space_size(struct pci_dev *dev) 1107{ 1108 int pos; 1109 u32 status; 1110 u16 class; 1111 1112 class = dev->class >> 8; 1113 if (class == PCI_CLASS_BRIDGE_HOST) 1114 return pci_cfg_space_size_ext(dev); 1115 1116 pos = pci_pcie_cap(dev); 1117 if (!pos) { 1118 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1119 if (!pos) 1120 goto fail; 1121 1122 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); 1123 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))) 1124 goto fail; 1125 } 1126 1127 return pci_cfg_space_size_ext(dev); 1128 1129 fail: 1130 return PCI_CFG_SPACE_SIZE; 1131} 1132 1133static void pci_release_bus_bridge_dev(struct device *dev) 1134{ 1135 kfree(dev); 1136} 1137 1138struct pci_dev *alloc_pci_dev(void) 1139{ 1140 struct pci_dev *dev; 1141 1142 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 1143 if (!dev) 1144 return NULL; 1145 1146 INIT_LIST_HEAD(&dev->bus_list); 1147 1148 return dev; 1149} 1150EXPORT_SYMBOL(alloc_pci_dev); 1151 1152/* 1153 * Read the config data for a PCI device, sanity-check it 1154 * and fill in the dev structure... 1155 */ 1156static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 1157{ 1158 struct pci_dev *dev; 1159 u32 l; 1160 int delay = 1; 1161 1162 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) 1163 return NULL; 1164 1165 /* some broken boards return 0 or ~0 if a slot is empty: */ 1166 if (l == 0xffffffff || l == 0x00000000 || 1167 l == 0x0000ffff || l == 0xffff0000) 1168 return NULL; 1169 1170 /* Configuration request Retry Status */ 1171 while (l == 0xffff0001) { 1172 msleep(delay); 1173 delay *= 2; 1174 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) 1175 return NULL; 1176 /* Card hasn't responded in 60 seconds? Must be stuck. */ 1177 if (delay > 60 * 1000) { 1178 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not " 1179 "responding\n", pci_domain_nr(bus), 1180 bus->number, PCI_SLOT(devfn), 1181 PCI_FUNC(devfn)); 1182 return NULL; 1183 } 1184 } 1185 1186 dev = alloc_pci_dev(); 1187 if (!dev) 1188 return NULL; 1189 1190 dev->bus = bus; 1191 dev->devfn = devfn; 1192 dev->vendor = l & 0xffff; 1193 dev->device = (l >> 16) & 0xffff; 1194 1195 if (pci_setup_device(dev)) { 1196 kfree(dev); 1197 return NULL; 1198 } 1199 1200 return dev; 1201} 1202 1203static void pci_init_capabilities(struct pci_dev *dev) 1204{ 1205 /* MSI/MSI-X list */ 1206 pci_msi_init_pci_dev(dev); 1207 1208 /* Buffers for saving PCIe and PCI-X capabilities */ 1209 pci_allocate_cap_save_buffers(dev); 1210 1211 /* Power Management */ 1212 pci_pm_init(dev); 1213 platform_pci_wakeup_init(dev); 1214 1215 /* Vital Product Data */ 1216 pci_vpd_pci22_init(dev); 1217 1218 /* Alternative Routing-ID Forwarding */ 1219 pci_enable_ari(dev); 1220 1221 /* Single Root I/O Virtualization */ 1222 pci_iov_init(dev); 1223 1224 /* Enable ACS P2P upstream forwarding */ 1225 pci_enable_acs(dev); 1226} 1227 1228void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 1229{ 1230 device_initialize(&dev->dev); 1231 dev->dev.release = pci_release_dev; 1232 pci_dev_get(dev); 1233 1234 dev->dev.dma_mask = &dev->dma_mask; 1235 dev->dev.dma_parms = &dev->dma_parms; 1236 dev->dev.coherent_dma_mask = 0xffffffffull; 1237 1238 pci_set_dma_max_seg_size(dev, 65536); 1239 pci_set_dma_seg_boundary(dev, 0xffffffff); 1240 1241 /* Fix up broken headers */ 1242 pci_fixup_device(pci_fixup_header, dev); 1243 1244 /* Clear the state_saved flag. */ 1245 dev->state_saved = false; 1246 1247 /* Initialize various capabilities */ 1248 pci_init_capabilities(dev); 1249 1250 /* 1251 * Add the device to our list of discovered devices 1252 * and the bus list for fixup functions, etc. 1253 */ 1254 down_write(&pci_bus_sem); 1255 list_add_tail(&dev->bus_list, &bus->devices); 1256 up_write(&pci_bus_sem); 1257} 1258 1259struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn) 1260{ 1261 struct pci_dev *dev; 1262 1263 dev = pci_get_slot(bus, devfn); 1264 if (dev) { 1265 pci_dev_put(dev); 1266 return dev; 1267 } 1268 1269 dev = pci_scan_device(bus, devfn); 1270 if (!dev) 1271 return NULL; 1272 1273 pci_device_add(dev, bus); 1274 1275 return dev; 1276} 1277EXPORT_SYMBOL(pci_scan_single_device); 1278 1279static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn) 1280{ 1281 u16 cap; 1282 unsigned pos, next_fn; 1283 1284 if (!dev) 1285 return 0; 1286 1287 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 1288 if (!pos) 1289 return 0; 1290 pci_read_config_word(dev, pos + 4, &cap); 1291 next_fn = cap >> 8; 1292 if (next_fn <= fn) 1293 return 0; 1294 return next_fn; 1295} 1296 1297static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn) 1298{ 1299 return (fn + 1) % 8; 1300} 1301 1302static unsigned no_next_fn(struct pci_dev *dev, unsigned fn) 1303{ 1304 return 0; 1305} 1306 1307static int only_one_child(struct pci_bus *bus) 1308{ 1309 struct pci_dev *parent = bus->self; 1310 if (!parent || !pci_is_pcie(parent)) 1311 return 0; 1312 if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT || 1313 parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) 1314 return 1; 1315 return 0; 1316} 1317 1318/** 1319 * pci_scan_slot - scan a PCI slot on a bus for devices. 1320 * @bus: PCI bus to scan 1321 * @devfn: slot number to scan (must have zero function.) 1322 * 1323 * Scan a PCI slot on the specified PCI bus for devices, adding 1324 * discovered devices to the @bus->devices list. New devices 1325 * will not have is_added set. 1326 * 1327 * Returns the number of new devices found. 1328 */ 1329int pci_scan_slot(struct pci_bus *bus, int devfn) 1330{ 1331 unsigned fn, nr = 0; 1332 struct pci_dev *dev; 1333 unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn; 1334 1335 if (only_one_child(bus) && (devfn > 0)) 1336 return 0; /* Already scanned the entire slot */ 1337 1338 dev = pci_scan_single_device(bus, devfn); 1339 if (!dev) 1340 return 0; 1341 if (!dev->is_added) 1342 nr++; 1343 1344 if (pci_ari_enabled(bus)) 1345 next_fn = next_ari_fn; 1346 else if (dev->multifunction) 1347 next_fn = next_trad_fn; 1348 1349 for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) { 1350 dev = pci_scan_single_device(bus, devfn + fn); 1351 if (dev) { 1352 if (!dev->is_added) 1353 nr++; 1354 dev->multifunction = 1; 1355 } 1356 } 1357 1358 /* only one slot has pcie device */ 1359 if (bus->self && nr) 1360 pcie_aspm_init_link_state(bus->self); 1361 1362 return nr; 1363} 1364 1365unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) 1366{ 1367 unsigned int devfn, pass, max = bus->secondary; 1368 struct pci_dev *dev; 1369 1370 dev_dbg(&bus->dev, "scanning bus\n"); 1371 1372 /* Go find them, Rover! */ 1373 for (devfn = 0; devfn < 0x100; devfn += 8) 1374 pci_scan_slot(bus, devfn); 1375 1376 /* Reserve buses for SR-IOV capability. */ 1377 max += pci_iov_bus_range(bus); 1378 1379#ifdef CONFIG_BCM47XX 1380 if (pci_domain_nr(bus) && pci_is_root_bus(bus)) 1381 max += pci_domain_nr(bus) - 1; 1382#endif 1383 1384 /* 1385 * After performing arch-dependent fixup of the bus, look behind 1386 * all PCI-to-PCI bridges on this bus. 1387 */ 1388 if (!bus->is_added) { 1389 dev_dbg(&bus->dev, "fixups for bus\n"); 1390 pcibios_fixup_bus(bus); 1391 if (pci_is_root_bus(bus)) 1392 bus->is_added = 1; 1393 } 1394 1395 for (pass=0; pass < 2; pass++) 1396 list_for_each_entry(dev, &bus->devices, bus_list) { 1397 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 1398 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) 1399 max = pci_scan_bridge(bus, dev, max, pass); 1400 } 1401 1402 /* 1403 * We've scanned the bus and so we know all about what's on 1404 * the other side of any bridges that may be on this bus plus 1405 * any devices. 1406 * 1407 * Return how far we've got finding sub-buses. 1408 */ 1409 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); 1410 return max; 1411} 1412 1413struct pci_bus * pci_create_bus(struct device *parent, 1414 int bus, struct pci_ops *ops, void *sysdata) 1415{ 1416 int error; 1417 struct pci_bus *b, *b2; 1418 struct device *dev; 1419 1420 b = pci_alloc_bus(); 1421 if (!b) 1422 return NULL; 1423 1424 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1425 if (!dev){ 1426 kfree(b); 1427 return NULL; 1428 } 1429 1430 b->sysdata = sysdata; 1431 b->ops = ops; 1432 1433 b2 = pci_find_bus(pci_domain_nr(b), bus); 1434 if (b2) { 1435 /* If we already got to this bus through a different bridge, ignore it */ 1436 dev_dbg(&b2->dev, "bus already known\n"); 1437 goto err_out; 1438 } 1439 1440 down_write(&pci_bus_sem); 1441 list_add_tail(&b->node, &pci_root_buses); 1442 up_write(&pci_bus_sem); 1443 1444 dev->parent = parent; 1445 dev->release = pci_release_bus_bridge_dev; 1446 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus); 1447 error = device_register(dev); 1448 if (error) 1449 goto dev_reg_err; 1450 b->bridge = get_device(dev); 1451 device_enable_async_suspend(b->bridge); 1452 1453 if (!parent) 1454 set_dev_node(b->bridge, pcibus_to_node(b)); 1455 1456 b->dev.class = &pcibus_class; 1457 b->dev.parent = b->bridge; 1458 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus); 1459 error = device_register(&b->dev); 1460 if (error) 1461 goto class_dev_reg_err; 1462 error = device_create_file(&b->dev, &dev_attr_cpuaffinity); 1463 if (error) 1464 goto dev_create_file_err; 1465 1466 /* Create legacy_io and legacy_mem files for this bus */ 1467 pci_create_legacy_files(b); 1468 1469 b->number = b->secondary = bus; 1470 b->resource[0] = &ioport_resource; 1471 b->resource[1] = &iomem_resource; 1472 1473 return b; 1474 1475dev_create_file_err: 1476 device_unregister(&b->dev); 1477class_dev_reg_err: 1478 device_unregister(dev); 1479dev_reg_err: 1480 down_write(&pci_bus_sem); 1481 list_del(&b->node); 1482 up_write(&pci_bus_sem); 1483err_out: 1484 kfree(dev); 1485 kfree(b); 1486 return NULL; 1487} 1488 1489struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, 1490 int bus, struct pci_ops *ops, void *sysdata) 1491{ 1492 struct pci_bus *b; 1493 1494 b = pci_create_bus(parent, bus, ops, sysdata); 1495 if (b) 1496 b->subordinate = pci_scan_child_bus(b); 1497 return b; 1498} 1499EXPORT_SYMBOL(pci_scan_bus_parented); 1500 1501#ifdef CONFIG_HOTPLUG 1502/** 1503 * pci_rescan_bus - scan a PCI bus for devices. 1504 * @bus: PCI bus to scan 1505 * 1506 * Scan a PCI bus and child buses for new devices, adds them, 1507 * and enables them. 1508 * 1509 * Returns the max number of subordinate bus discovered. 1510 */ 1511unsigned int __ref pci_rescan_bus(struct pci_bus *bus) 1512{ 1513 unsigned int max; 1514 struct pci_dev *dev; 1515 1516 max = pci_scan_child_bus(bus); 1517 1518 down_read(&pci_bus_sem); 1519 list_for_each_entry(dev, &bus->devices, bus_list) 1520 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 1521 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) 1522 if (dev->subordinate) 1523 pci_bus_size_bridges(dev->subordinate); 1524 up_read(&pci_bus_sem); 1525 1526 pci_bus_assign_resources(bus); 1527 pci_enable_bridges(bus); 1528 pci_bus_add_devices(bus); 1529 1530 return max; 1531} 1532EXPORT_SYMBOL_GPL(pci_rescan_bus); 1533 1534EXPORT_SYMBOL(pci_add_new_bus); 1535EXPORT_SYMBOL(pci_scan_slot); 1536EXPORT_SYMBOL(pci_scan_bridge); 1537EXPORT_SYMBOL_GPL(pci_scan_child_bus); 1538#endif 1539 1540static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b) 1541{ 1542 const struct pci_dev *a = to_pci_dev(d_a); 1543 const struct pci_dev *b = to_pci_dev(d_b); 1544 1545 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; 1546 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; 1547 1548 if (a->bus->number < b->bus->number) return -1; 1549 else if (a->bus->number > b->bus->number) return 1; 1550 1551 if (a->devfn < b->devfn) return -1; 1552 else if (a->devfn > b->devfn) return 1; 1553 1554 return 0; 1555} 1556 1557void __init pci_sort_breadthfirst(void) 1558{ 1559 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); 1560} 1561