1/* 2 * eisa.c - provide support for EISA adapters in PA-RISC machines 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 * 9 * Copyright (c) 2001 Matthew Wilcox for Hewlett Packard 10 * Copyright (c) 2001 Daniel Engstrom <5116@telia.com> 11 * 12 * There are two distinct EISA adapters. Mongoose is found in machines 13 * before the 712; then the Wax ASIC is used. To complicate matters, the 14 * Wax ASIC also includes a PS/2 and RS-232 controller, but those are 15 * dealt with elsewhere; this file is concerned only with the EISA portions 16 * of Wax. 17 * 18 * 19 * HINT: 20 * ----- 21 * To allow an ISA card to work properly in the EISA slot you need to 22 * set an edge trigger level. This may be done on the palo command line 23 * by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with 24 * n and n2 as the irq levels you want to use. 25 * 26 * Example: "eisa_irq_edge=10,11" allows ISA cards to operate at 27 * irq levels 10 and 11. 28 */ 29 30#include <linux/init.h> 31#include <linux/ioport.h> 32#include <linux/interrupt.h> 33#include <linux/kernel.h> 34#include <linux/module.h> 35#include <linux/pci.h> 36#include <linux/spinlock.h> 37#include <linux/eisa.h> 38 39#include <asm/byteorder.h> 40#include <asm/io.h> 41#include <asm/hardware.h> 42#include <asm/processor.h> 43#include <asm/parisc-device.h> 44#include <asm/delay.h> 45#include <asm/eisa_bus.h> 46#include <asm/eisa_eeprom.h> 47 48#define EISA_DBG(msg, arg... ) 49 50#define SNAKES_EEPROM_BASE_ADDR 0xF0810400 51#define MIRAGE_EEPROM_BASE_ADDR 0xF00C0400 52 53static DEFINE_SPINLOCK(eisa_irq_lock); 54 55void __iomem *eisa_eeprom_addr __read_mostly; 56 57/* We can only have one EISA adapter in the system because neither 58 * implementation can be flexed. 59 */ 60static struct eisa_ba { 61 struct pci_hba_data hba; 62 unsigned long eeprom_addr; 63 struct eisa_root_device root; 64} eisa_dev; 65 66/* Port ops */ 67 68static inline unsigned long eisa_permute(unsigned short port) 69{ 70 if (port & 0x300) { 71 return 0xfc000000 | ((port & 0xfc00) >> 6) 72 | ((port & 0x3f8) << 9) | (port & 7); 73 } else { 74 return 0xfc000000 | port; 75 } 76} 77 78unsigned char eisa_in8(unsigned short port) 79{ 80 if (EISA_bus) 81 return gsc_readb(eisa_permute(port)); 82 return 0xff; 83} 84 85unsigned short eisa_in16(unsigned short port) 86{ 87 if (EISA_bus) 88 return le16_to_cpu(gsc_readw(eisa_permute(port))); 89 return 0xffff; 90} 91 92unsigned int eisa_in32(unsigned short port) 93{ 94 if (EISA_bus) 95 return le32_to_cpu(gsc_readl(eisa_permute(port))); 96 return 0xffffffff; 97} 98 99void eisa_out8(unsigned char data, unsigned short port) 100{ 101 if (EISA_bus) 102 gsc_writeb(data, eisa_permute(port)); 103} 104 105void eisa_out16(unsigned short data, unsigned short port) 106{ 107 if (EISA_bus) 108 gsc_writew(cpu_to_le16(data), eisa_permute(port)); 109} 110 111void eisa_out32(unsigned int data, unsigned short port) 112{ 113 if (EISA_bus) 114 gsc_writel(cpu_to_le32(data), eisa_permute(port)); 115} 116 117#ifndef CONFIG_PCI 118/* We call these directly without PCI. See asm/io.h. */ 119EXPORT_SYMBOL(eisa_in8); 120EXPORT_SYMBOL(eisa_in16); 121EXPORT_SYMBOL(eisa_in32); 122EXPORT_SYMBOL(eisa_out8); 123EXPORT_SYMBOL(eisa_out16); 124EXPORT_SYMBOL(eisa_out32); 125#endif 126 127/* Interrupt handling */ 128 129/* cached interrupt mask registers */ 130static int master_mask; 131static int slave_mask; 132 133/* the trig level can be set with the 134 * eisa_irq_edge=n,n,n commandline parameter 135 * We should really read this from the EEPROM 136 * in the furure. 137 */ 138/* irq 13,8,2,1,0 must be edge */ 139static unsigned int eisa_irq_level __read_mostly; /* default to edge triggered */ 140 141 142/* called by free irq */ 143static void eisa_disable_irq(unsigned int irq) 144{ 145 unsigned long flags; 146 147 EISA_DBG("disable irq %d\n", irq); 148 /* just mask for now */ 149 spin_lock_irqsave(&eisa_irq_lock, flags); 150 if (irq & 8) { 151 slave_mask |= (1 << (irq&7)); 152 eisa_out8(slave_mask, 0xa1); 153 } else { 154 master_mask |= (1 << (irq&7)); 155 eisa_out8(master_mask, 0x21); 156 } 157 spin_unlock_irqrestore(&eisa_irq_lock, flags); 158 EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21)); 159 EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1)); 160} 161 162/* called by request irq */ 163static void eisa_enable_irq(unsigned int irq) 164{ 165 unsigned long flags; 166 EISA_DBG("enable irq %d\n", irq); 167 168 spin_lock_irqsave(&eisa_irq_lock, flags); 169 if (irq & 8) { 170 slave_mask &= ~(1 << (irq&7)); 171 eisa_out8(slave_mask, 0xa1); 172 } else { 173 master_mask &= ~(1 << (irq&7)); 174 eisa_out8(master_mask, 0x21); 175 } 176 spin_unlock_irqrestore(&eisa_irq_lock, flags); 177 EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21)); 178 EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1)); 179} 180 181static unsigned int eisa_startup_irq(unsigned int irq) 182{ 183 eisa_enable_irq(irq); 184 return 0; 185} 186 187static struct irq_chip eisa_interrupt_type = { 188 .name = "EISA", 189 .startup = eisa_startup_irq, 190 .shutdown = eisa_disable_irq, 191 .enable = eisa_enable_irq, 192 .disable = eisa_disable_irq, 193 .ack = no_ack_irq, 194 .end = no_end_irq, 195}; 196 197static irqreturn_t eisa_irq(int wax_irq, void *intr_dev) 198{ 199 int irq = gsc_readb(0xfc01f000); /* EISA supports 16 irqs */ 200 unsigned long flags; 201 202 spin_lock_irqsave(&eisa_irq_lock, flags); 203 /* read IRR command */ 204 eisa_out8(0x0a, 0x20); 205 eisa_out8(0x0a, 0xa0); 206 207 EISA_DBG("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n", 208 irq, eisa_in8(0x20), eisa_in8(0xa0)); 209 210 /* read ISR command */ 211 eisa_out8(0x0a, 0x20); 212 eisa_out8(0x0a, 0xa0); 213 EISA_DBG("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n", 214 eisa_in8(0x20), eisa_in8(0x21), eisa_in8(0xa0), eisa_in8(0xa1)); 215 216 irq &= 0xf; 217 218 /* mask irq and write eoi */ 219 if (irq & 8) { 220 slave_mask |= (1 << (irq&7)); 221 eisa_out8(slave_mask, 0xa1); 222 eisa_out8(0x60 | (irq&7),0xa0);/* 'Specific EOI' to slave */ 223 eisa_out8(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */ 224 225 } else { 226 master_mask |= (1 << (irq&7)); 227 eisa_out8(master_mask, 0x21); 228 eisa_out8(0x60|irq,0x20); /* 'Specific EOI' to master */ 229 } 230 spin_unlock_irqrestore(&eisa_irq_lock, flags); 231 232 __do_IRQ(irq); 233 234 spin_lock_irqsave(&eisa_irq_lock, flags); 235 /* unmask */ 236 if (irq & 8) { 237 slave_mask &= ~(1 << (irq&7)); 238 eisa_out8(slave_mask, 0xa1); 239 } else { 240 master_mask &= ~(1 << (irq&7)); 241 eisa_out8(master_mask, 0x21); 242 } 243 spin_unlock_irqrestore(&eisa_irq_lock, flags); 244 return IRQ_HANDLED; 245} 246 247static irqreturn_t dummy_irq2_handler(int _, void *dev) 248{ 249 printk(KERN_ALERT "eisa: uhh, irq2?\n"); 250 return IRQ_HANDLED; 251} 252 253static struct irqaction irq2_action = { 254 .handler = dummy_irq2_handler, 255 .name = "cascade", 256}; 257 258static void init_eisa_pic(void) 259{ 260 unsigned long flags; 261 262 spin_lock_irqsave(&eisa_irq_lock, flags); 263 264 eisa_out8(0xff, 0x21); /* mask during init */ 265 eisa_out8(0xff, 0xa1); /* mask during init */ 266 267 /* master pic */ 268 eisa_out8(0x11,0x20); /* ICW1 */ 269 eisa_out8(0x00,0x21); /* ICW2 */ 270 eisa_out8(0x04,0x21); /* ICW3 */ 271 eisa_out8(0x01,0x21); /* ICW4 */ 272 eisa_out8(0x40,0x20); /* OCW2 */ 273 274 /* slave pic */ 275 eisa_out8(0x11,0xa0); /* ICW1 */ 276 eisa_out8(0x08,0xa1); /* ICW2 */ 277 eisa_out8(0x02,0xa1); /* ICW3 */ 278 eisa_out8(0x01,0xa1); /* ICW4 */ 279 eisa_out8(0x40,0xa0); /* OCW2 */ 280 281 udelay(100); 282 283 slave_mask = 0xff; 284 master_mask = 0xfb; 285 eisa_out8(slave_mask, 0xa1); /* OCW1 */ 286 eisa_out8(master_mask, 0x21); /* OCW1 */ 287 288 /* setup trig level */ 289 EISA_DBG("EISA edge/level %04x\n", eisa_irq_level); 290 291 eisa_out8(eisa_irq_level&0xff, 0x4d0); /* Set all irq's to edge */ 292 eisa_out8((eisa_irq_level >> 8) & 0xff, 0x4d1); 293 294 EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21)); 295 EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1)); 296 EISA_DBG("pic0 edge/level %02x\n", eisa_in8(0x4d0)); 297 EISA_DBG("pic1 edge/level %02x\n", eisa_in8(0x4d1)); 298 299 spin_unlock_irqrestore(&eisa_irq_lock, flags); 300} 301 302/* Device initialisation */ 303 304#define is_mongoose(dev) (dev->id.sversion == 0x00076) 305 306static int __init eisa_probe(struct parisc_device *dev) 307{ 308 int i, result; 309 310 char *name = is_mongoose(dev) ? "Mongoose" : "Wax"; 311 312 printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n", 313 name, (unsigned long)dev->hpa.start); 314 315 eisa_dev.hba.dev = dev; 316 eisa_dev.hba.iommu = ccio_get_iommu(dev); 317 318 eisa_dev.hba.lmmio_space.name = "EISA"; 319 eisa_dev.hba.lmmio_space.start = F_EXTEND(0xfc000000); 320 eisa_dev.hba.lmmio_space.end = F_EXTEND(0xffbfffff); 321 eisa_dev.hba.lmmio_space.flags = IORESOURCE_MEM; 322 result = ccio_request_resource(dev, &eisa_dev.hba.lmmio_space); 323 if (result < 0) { 324 printk(KERN_ERR "EISA: failed to claim EISA Bus address space!\n"); 325 return result; 326 } 327 eisa_dev.hba.io_space.name = "EISA"; 328 eisa_dev.hba.io_space.start = 0; 329 eisa_dev.hba.io_space.end = 0xffff; 330 eisa_dev.hba.lmmio_space.flags = IORESOURCE_IO; 331 result = request_resource(&ioport_resource, &eisa_dev.hba.io_space); 332 if (result < 0) { 333 printk(KERN_ERR "EISA: failed to claim EISA Bus port space!\n"); 334 return result; 335 } 336 pcibios_register_hba(&eisa_dev.hba); 337 338 result = request_irq(dev->irq, eisa_irq, IRQF_SHARED, "EISA", &eisa_dev); 339 if (result) { 340 printk(KERN_ERR "EISA: request_irq failed!\n"); 341 return result; 342 } 343 344 /* Reserve IRQ2 */ 345 irq_to_desc(2)->action = &irq2_action; 346 347 for (i = 0; i < 16; i++) { 348 irq_to_desc(i)->chip = &eisa_interrupt_type; 349 } 350 351 EISA_bus = 1; 352 353 if (dev->num_addrs) { 354 /* newer firmware hand out the eeprom address */ 355 eisa_dev.eeprom_addr = dev->addr[0]; 356 } else { 357 /* old firmware, need to figure out the box */ 358 if (is_mongoose(dev)) { 359 eisa_dev.eeprom_addr = SNAKES_EEPROM_BASE_ADDR; 360 } else { 361 eisa_dev.eeprom_addr = MIRAGE_EEPROM_BASE_ADDR; 362 } 363 } 364 eisa_eeprom_addr = ioremap_nocache(eisa_dev.eeprom_addr, HPEE_MAX_LENGTH); 365 result = eisa_enumerator(eisa_dev.eeprom_addr, &eisa_dev.hba.io_space, 366 &eisa_dev.hba.lmmio_space); 367 init_eisa_pic(); 368 369 if (result >= 0) { 370 eisa_dev.root.dev = &dev->dev; 371 dev_set_drvdata(&dev->dev, &eisa_dev.root); 372 eisa_dev.root.bus_base_addr = 0; 373 eisa_dev.root.res = &eisa_dev.hba.io_space; 374 eisa_dev.root.slots = result; 375 eisa_dev.root.dma_mask = 0xffffffff; /* wild guess */ 376 if (eisa_root_register (&eisa_dev.root)) { 377 printk(KERN_ERR "EISA: Failed to register EISA root\n"); 378 return -1; 379 } 380 } 381 382 return 0; 383} 384 385static const struct parisc_device_id eisa_tbl[] = { 386 { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00076 }, /* Mongoose */ 387 { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00090 }, /* Wax EISA */ 388 { 0, } 389}; 390 391MODULE_DEVICE_TABLE(parisc, eisa_tbl); 392 393static struct parisc_driver eisa_driver = { 394 .name = "eisa_ba", 395 .id_table = eisa_tbl, 396 .probe = eisa_probe, 397}; 398 399void __init eisa_init(void) 400{ 401 register_parisc_driver(&eisa_driver); 402} 403 404 405static unsigned int eisa_irq_configured; 406void eisa_make_irq_level(int num) 407{ 408 if (eisa_irq_configured& (1<<num)) { 409 printk(KERN_WARNING 410 "IRQ %d polarity configured twice (last to level)\n", 411 num); 412 } 413 eisa_irq_level |= (1<<num); /* set the corresponding bit */ 414 eisa_irq_configured |= (1<<num); /* set the corresponding bit */ 415} 416 417void eisa_make_irq_edge(int num) 418{ 419 if (eisa_irq_configured& (1<<num)) { 420 printk(KERN_WARNING 421 "IRQ %d polarity configured twice (last to edge)\n", 422 num); 423 } 424 eisa_irq_level &= ~(1<<num); /* clear the corresponding bit */ 425 eisa_irq_configured |= (1<<num); /* set the corresponding bit */ 426} 427 428static int __init eisa_irq_setup(char *str) 429{ 430 char *cur = str; 431 int val; 432 433 EISA_DBG("IRQ setup\n"); 434 while (cur != NULL) { 435 char *pe; 436 437 val = (int) simple_strtoul(cur, &pe, 0); 438 if (val > 15 || val < 0) { 439 printk(KERN_ERR "eisa: EISA irq value are 0-15\n"); 440 continue; 441 } 442 if (val == 2) { 443 val = 9; 444 } 445 eisa_make_irq_edge(val); /* clear the corresponding bit */ 446 EISA_DBG("setting IRQ %d to edge-triggered mode\n", val); 447 448 if ((cur = strchr(cur, ','))) { 449 cur++; 450 } else { 451 break; 452 } 453 } 454 return 1; 455} 456 457__setup("eisa_irq_edge=", eisa_irq_setup); 458