1/* 2** DINO manager 3** 4** (c) Copyright 1999 Red Hat Software 5** (c) Copyright 1999 SuSE GmbH 6** (c) Copyright 1999,2000 Hewlett-Packard Company 7** (c) Copyright 2000 Grant Grundler 8** (c) Copyright 2006 Helge Deller 9** 10** This program is free software; you can redistribute it and/or modify 11** it under the terms of the GNU General Public License as published by 12** the Free Software Foundation; either version 2 of the License, or 13** (at your option) any later version. 14** 15** This module provides access to Dino PCI bus (config/IOport spaces) 16** and helps manage Dino IRQ lines. 17** 18** Dino interrupt handling is a bit complicated. 19** Dino always writes to the broadcast EIR via irr0 for now. 20** (BIG WARNING: using broadcast EIR is a really bad thing for SMP!) 21** Only one processor interrupt is used for the 11 IRQ line 22** inputs to dino. 23** 24** The different between Built-in Dino and Card-Mode 25** dino is in chip initialization and pci device initialization. 26** 27** Linux drivers can only use Card-Mode Dino if pci devices I/O port 28** BARs are configured and used by the driver. Programming MMIO address 29** requires substantial knowledge of available Host I/O address ranges 30** is currently not supported. Port/Config accessor functions are the 31** same. "BIOS" differences are handled within the existing routines. 32*/ 33 34/* Changes : 35** 2001-06-14 : Clement Moyroud (moyroudc@esiee.fr) 36** - added support for the integrated RS232. 37*/ 38 39/* 40** TODO: create a virtual address for each Dino HPA. 41** GSC code might be able to do this since IODC data tells us 42** how many pages are used. PCI subsystem could (must?) do this 43** for PCI drivers devices which implement/use MMIO registers. 44*/ 45 46#include <linux/delay.h> 47#include <linux/types.h> 48#include <linux/kernel.h> 49#include <linux/pci.h> 50#include <linux/init.h> 51#include <linux/ioport.h> 52#include <linux/slab.h> 53#include <linux/interrupt.h> /* for struct irqaction */ 54#include <linux/spinlock.h> /* for spinlock_t and prototypes */ 55 56#include <asm/pdc.h> 57#include <asm/page.h> 58#include <asm/system.h> 59#include <asm/io.h> 60#include <asm/hardware.h> 61 62#include "gsc.h" 63 64#undef DINO_DEBUG 65 66#ifdef DINO_DEBUG 67#define DBG(x...) printk(x) 68#else 69#define DBG(x...) 70#endif 71 72/* 73** Config accessor functions only pass in the 8-bit bus number 74** and not the 8-bit "PCI Segment" number. Each Dino will be 75** assigned a PCI bus number based on "when" it's discovered. 76** 77** The "secondary" bus number is set to this before calling 78** pci_scan_bus(). If any PPB's are present, the scan will 79** discover them and update the "secondary" and "subordinate" 80** fields in Dino's pci_bus structure. 81** 82** Changes in the configuration *will* result in a different 83** bus number for each dino. 84*/ 85 86#define is_card_dino(id) ((id)->hw_type == HPHW_A_DMA) 87#define is_cujo(id) ((id)->hversion == 0x682) 88 89#define DINO_IAR0 0x004 90#define DINO_IODC_ADDR 0x008 91#define DINO_IODC_DATA_0 0x008 92#define DINO_IODC_DATA_1 0x008 93#define DINO_IRR0 0x00C 94#define DINO_IAR1 0x010 95#define DINO_IRR1 0x014 96#define DINO_IMR 0x018 97#define DINO_IPR 0x01C 98#define DINO_TOC_ADDR 0x020 99#define DINO_ICR 0x024 100#define DINO_ILR 0x028 101#define DINO_IO_COMMAND 0x030 102#define DINO_IO_STATUS 0x034 103#define DINO_IO_CONTROL 0x038 104#define DINO_IO_GSC_ERR_RESP 0x040 105#define DINO_IO_ERR_INFO 0x044 106#define DINO_IO_PCI_ERR_RESP 0x048 107#define DINO_IO_FBB_EN 0x05c 108#define DINO_IO_ADDR_EN 0x060 109#define DINO_PCI_ADDR 0x064 110#define DINO_CONFIG_DATA 0x068 111#define DINO_IO_DATA 0x06c 112#define DINO_MEM_DATA 0x070 /* Dino 3.x only */ 113#define DINO_GSC2X_CONFIG 0x7b4 114#define DINO_GMASK 0x800 115#define DINO_PAMR 0x804 116#define DINO_PAPR 0x808 117#define DINO_DAMODE 0x80c 118#define DINO_PCICMD 0x810 119#define DINO_PCISTS 0x814 120#define DINO_MLTIM 0x81c 121#define DINO_BRDG_FEAT 0x820 122#define DINO_PCIROR 0x824 123#define DINO_PCIWOR 0x828 124#define DINO_TLTIM 0x830 125 126#define DINO_IRQS 11 /* bits 0-10 are architected */ 127#define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */ 128#define DINO_LOCAL_IRQS (DINO_IRQS+1) 129 130#define DINO_MASK_IRQ(x) (1<<(x)) 131 132#define PCIINTA 0x001 133#define PCIINTB 0x002 134#define PCIINTC 0x004 135#define PCIINTD 0x008 136#define PCIINTE 0x010 137#define PCIINTF 0x020 138#define GSCEXTINT 0x040 139#define RS232INT 0x400 140 141struct dino_device 142{ 143 struct pci_hba_data hba; /* 'C' inheritance - must be first */ 144 spinlock_t dinosaur_pen; 145 unsigned long txn_addr; /* EIR addr to generate interrupt */ 146 u32 txn_data; /* EIR data assign to each dino */ 147 u32 imr; /* IRQ's which are enabled */ 148 int global_irq[DINO_LOCAL_IRQS]; /* map IMR bit to global irq */ 149#ifdef DINO_DEBUG 150 unsigned int dino_irr0; /* save most recent IRQ line stat */ 151#endif 152}; 153 154/* Looks nice and keeps the compiler happy */ 155#define DINO_DEV(d) ((struct dino_device *) d) 156 157 158/* 159 * Dino Configuration Space Accessor Functions 160 */ 161 162#define DINO_CFG_TOK(bus,dfn,pos) ((u32) ((bus)<<16 | (dfn)<<8 | (pos))) 163 164/* 165 * keep the current highest bus count to assist in allocating busses. This 166 * tries to keep a global bus count total so that when we discover an 167 * entirely new bus, it can be given a unique bus number. 168 */ 169static int dino_current_bus = 0; 170 171static int dino_cfg_read(struct pci_bus *bus, unsigned int devfn, int where, 172 int size, u32 *val) 173{ 174 struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge)); 175 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 176 u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3); 177 void __iomem *base_addr = d->hba.base_addr; 178 unsigned long flags; 179 180 DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where, 181 size); 182 spin_lock_irqsave(&d->dinosaur_pen, flags); 183 184 /* tell HW which CFG address */ 185 __raw_writel(v, base_addr + DINO_PCI_ADDR); 186 187 /* generate cfg read cycle */ 188 if (size == 1) { 189 *val = readb(base_addr + DINO_CONFIG_DATA + (where & 3)); 190 } else if (size == 2) { 191 *val = readw(base_addr + DINO_CONFIG_DATA + (where & 2)); 192 } else if (size == 4) { 193 *val = readl(base_addr + DINO_CONFIG_DATA); 194 } 195 196 spin_unlock_irqrestore(&d->dinosaur_pen, flags); 197 return 0; 198} 199 200/* 201 * Dino address stepping "feature": 202 * When address stepping, Dino attempts to drive the bus one cycle too soon 203 * even though the type of cycle (config vs. MMIO) might be different. 204 * The read of Ven/Prod ID is harmless and avoids Dino's address stepping. 205 */ 206static int dino_cfg_write(struct pci_bus *bus, unsigned int devfn, int where, 207 int size, u32 val) 208{ 209 struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge)); 210 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 211 u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3); 212 void __iomem *base_addr = d->hba.base_addr; 213 unsigned long flags; 214 215 DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where, 216 size); 217 spin_lock_irqsave(&d->dinosaur_pen, flags); 218 219 /* avoid address stepping feature */ 220 __raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR); 221 __raw_readl(base_addr + DINO_CONFIG_DATA); 222 223 /* tell HW which CFG address */ 224 __raw_writel(v, base_addr + DINO_PCI_ADDR); 225 /* generate cfg read cycle */ 226 if (size == 1) { 227 writeb(val, base_addr + DINO_CONFIG_DATA + (where & 3)); 228 } else if (size == 2) { 229 writew(val, base_addr + DINO_CONFIG_DATA + (where & 2)); 230 } else if (size == 4) { 231 writel(val, base_addr + DINO_CONFIG_DATA); 232 } 233 234 spin_unlock_irqrestore(&d->dinosaur_pen, flags); 235 return 0; 236} 237 238static struct pci_ops dino_cfg_ops = { 239 .read = dino_cfg_read, 240 .write = dino_cfg_write, 241}; 242 243 244/* 245 * Dino "I/O Port" Space Accessor Functions 246 * 247 * Many PCI devices don't require use of I/O port space (eg Tulip, 248 * NCR720) since they export the same registers to both MMIO and 249 * I/O port space. Performance is going to stink if drivers use 250 * I/O port instead of MMIO. 251 */ 252 253#define DINO_PORT_IN(type, size, mask) \ 254static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \ 255{ \ 256 u##size v; \ 257 unsigned long flags; \ 258 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \ 259 /* tell HW which IO Port address */ \ 260 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \ 261 /* generate I/O PORT read cycle */ \ 262 v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \ 263 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \ 264 return v; \ 265} 266 267DINO_PORT_IN(b, 8, 3) 268DINO_PORT_IN(w, 16, 2) 269DINO_PORT_IN(l, 32, 0) 270 271#define DINO_PORT_OUT(type, size, mask) \ 272static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \ 273{ \ 274 unsigned long flags; \ 275 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \ 276 /* tell HW which IO port address */ \ 277 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \ 278 /* generate cfg write cycle */ \ 279 write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \ 280 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \ 281} 282 283DINO_PORT_OUT(b, 8, 3) 284DINO_PORT_OUT(w, 16, 2) 285DINO_PORT_OUT(l, 32, 0) 286 287static struct pci_port_ops dino_port_ops = { 288 .inb = dino_in8, 289 .inw = dino_in16, 290 .inl = dino_in32, 291 .outb = dino_out8, 292 .outw = dino_out16, 293 .outl = dino_out32 294}; 295 296static void dino_disable_irq(unsigned int irq) 297{ 298 struct irq_desc *desc = irq_to_desc(irq); 299 struct dino_device *dino_dev = desc->chip_data; 300 int local_irq = gsc_find_local_irq(irq, dino_dev->global_irq, DINO_LOCAL_IRQS); 301 302 DBG(KERN_WARNING "%s(0x%p, %d)\n", __func__, dino_dev, irq); 303 304 /* Clear the matching bit in the IMR register */ 305 dino_dev->imr &= ~(DINO_MASK_IRQ(local_irq)); 306 __raw_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR); 307} 308 309static void dino_enable_irq(unsigned int irq) 310{ 311 struct irq_desc *desc = irq_to_desc(irq); 312 struct dino_device *dino_dev = desc->chip_data; 313 int local_irq = gsc_find_local_irq(irq, dino_dev->global_irq, DINO_LOCAL_IRQS); 314 u32 tmp; 315 316 DBG(KERN_WARNING "%s(0x%p, %d)\n", __func__, dino_dev, irq); 317 318 /* 319 ** clear pending IRQ bits 320 ** 321 ** This does NOT change ILR state! 322 ** See comment below for ILR usage. 323 */ 324 __raw_readl(dino_dev->hba.base_addr+DINO_IPR); 325 326 /* set the matching bit in the IMR register */ 327 dino_dev->imr |= DINO_MASK_IRQ(local_irq); /* used in dino_isr() */ 328 __raw_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR); 329 330 /* Emulate "Level Triggered" Interrupt 331 ** Basically, a driver is blowing it if the IRQ line is asserted 332 ** while the IRQ is disabled. But tulip.c seems to do that.... 333 ** Give 'em a kluge award and a nice round of applause! 334 ** 335 ** The gsc_write will generate an interrupt which invokes dino_isr(). 336 ** dino_isr() will read IPR and find nothing. But then catch this 337 ** when it also checks ILR. 338 */ 339 tmp = __raw_readl(dino_dev->hba.base_addr+DINO_ILR); 340 if (tmp & DINO_MASK_IRQ(local_irq)) { 341 DBG(KERN_WARNING "%s(): IRQ asserted! (ILR 0x%x)\n", 342 __func__, tmp); 343 gsc_writel(dino_dev->txn_data, dino_dev->txn_addr); 344 } 345} 346 347static unsigned int dino_startup_irq(unsigned int irq) 348{ 349 dino_enable_irq(irq); 350 return 0; 351} 352 353static struct irq_chip dino_interrupt_type = { 354 .name = "GSC-PCI", 355 .startup = dino_startup_irq, 356 .shutdown = dino_disable_irq, 357 .enable = dino_enable_irq, 358 .disable = dino_disable_irq, 359 .ack = no_ack_irq, 360 .end = no_end_irq, 361}; 362 363 364/* 365 * Handle a Processor interrupt generated by Dino. 366 * 367 * ilr_loop counter is a kluge to prevent a "stuck" IRQ line from 368 * wedging the CPU. Could be removed or made optional at some point. 369 */ 370static irqreturn_t dino_isr(int irq, void *intr_dev) 371{ 372 struct dino_device *dino_dev = intr_dev; 373 u32 mask; 374 int ilr_loop = 100; 375 376 /* read and acknowledge pending interrupts */ 377#ifdef DINO_DEBUG 378 dino_dev->dino_irr0 = 379#endif 380 mask = __raw_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK; 381 382 if (mask == 0) 383 return IRQ_NONE; 384 385ilr_again: 386 do { 387 int local_irq = __ffs(mask); 388 int irq = dino_dev->global_irq[local_irq]; 389 DBG(KERN_DEBUG "%s(%d, %p) mask 0x%x\n", 390 __func__, irq, intr_dev, mask); 391 __do_IRQ(irq); 392 mask &= ~(1 << local_irq); 393 } while (mask); 394 395 /* Support for level triggered IRQ lines. 396 ** 397 ** Dropping this support would make this routine *much* faster. 398 ** But since PCI requires level triggered IRQ line to share lines... 399 ** device drivers may assume lines are level triggered (and not 400 ** edge triggered like EISA/ISA can be). 401 */ 402 mask = __raw_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr; 403 if (mask) { 404 if (--ilr_loop > 0) 405 goto ilr_again; 406 printk(KERN_ERR "Dino 0x%p: stuck interrupt %d\n", 407 dino_dev->hba.base_addr, mask); 408 return IRQ_NONE; 409 } 410 return IRQ_HANDLED; 411} 412 413static void dino_assign_irq(struct dino_device *dino, int local_irq, int *irqp) 414{ 415 int irq = gsc_assign_irq(&dino_interrupt_type, dino); 416 if (irq == NO_IRQ) 417 return; 418 419 *irqp = irq; 420 dino->global_irq[local_irq] = irq; 421} 422 423static void dino_choose_irq(struct parisc_device *dev, void *ctrl) 424{ 425 int irq; 426 struct dino_device *dino = ctrl; 427 428 switch (dev->id.sversion) { 429 case 0x00084: irq = 8; break; /* PS/2 */ 430 case 0x0008c: irq = 10; break; /* RS232 */ 431 case 0x00096: irq = 8; break; /* PS/2 */ 432 default: return; /* Unknown */ 433 } 434 435 dino_assign_irq(dino, irq, &dev->irq); 436} 437 438 439/* 440 * Cirrus 6832 Cardbus reports wrong irq on RDI Tadpole PARISC Laptop (deller@gmx.de) 441 * (the irqs are off-by-one, not sure yet if this is a cirrus, dino-hardware or dino-driver problem...) 442 */ 443static void __devinit quirk_cirrus_cardbus(struct pci_dev *dev) 444{ 445 u8 new_irq = dev->irq - 1; 446 printk(KERN_INFO "PCI: Cirrus Cardbus IRQ fixup for %s, from %d to %d\n", 447 pci_name(dev), dev->irq, new_irq); 448 dev->irq = new_irq; 449} 450DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6832, quirk_cirrus_cardbus ); 451 452 453static void __init 454dino_bios_init(void) 455{ 456 DBG("dino_bios_init\n"); 457} 458 459/* 460 * dino_card_setup - Set up the memory space for a Dino in card mode. 461 * @bus: the bus under this dino 462 * 463 * Claim an 8MB chunk of unused IO space and call the generic PCI routines 464 * to set up the addresses of the devices on this bus. 465 */ 466#define _8MB 0x00800000UL 467static void __init 468dino_card_setup(struct pci_bus *bus, void __iomem *base_addr) 469{ 470 int i; 471 struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge)); 472 struct resource *res; 473 char name[128]; 474 int size; 475 476 res = &dino_dev->hba.lmmio_space; 477 res->flags = IORESOURCE_MEM; 478 size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)", 479 dev_name(bus->bridge)); 480 res->name = kmalloc(size+1, GFP_KERNEL); 481 if(res->name) 482 strcpy((char *)res->name, name); 483 else 484 res->name = dino_dev->hba.lmmio_space.name; 485 486 487 if (ccio_allocate_resource(dino_dev->hba.dev, res, _8MB, 488 F_EXTEND(0xf0000000UL) | _8MB, 489 F_EXTEND(0xffffffffUL) &~ _8MB, _8MB) < 0) { 490 struct list_head *ln, *tmp_ln; 491 492 printk(KERN_ERR "Dino: cannot attach bus %s\n", 493 dev_name(bus->bridge)); 494 /* kill the bus, we can't do anything with it */ 495 list_for_each_safe(ln, tmp_ln, &bus->devices) { 496 struct pci_dev *dev = pci_dev_b(ln); 497 498 list_del(&dev->bus_list); 499 } 500 501 return; 502 } 503 bus->resource[1] = res; 504 bus->resource[0] = &(dino_dev->hba.io_space); 505 506 /* Now tell dino what range it has */ 507 for (i = 1; i < 31; i++) { 508 if (res->start == F_EXTEND(0xf0000000UL | (i * _8MB))) 509 break; 510 } 511 DBG("DINO GSC WRITE i=%d, start=%lx, dino addr = %p\n", 512 i, res->start, base_addr + DINO_IO_ADDR_EN); 513 __raw_writel(1 << i, base_addr + DINO_IO_ADDR_EN); 514} 515 516static void __init 517dino_card_fixup(struct pci_dev *dev) 518{ 519 u32 irq_pin; 520 521 /* 522 ** REVISIT: card-mode PCI-PCI expansion chassis do exist. 523 ** Not sure they were ever productized. 524 ** Die here since we'll die later in dino_inb() anyway. 525 */ 526 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 527 panic("Card-Mode Dino: PCI-PCI Bridge not supported\n"); 528 } 529 530 /* 531 ** Set Latency Timer to 0xff (not a shared bus) 532 ** Set CACHELINE_SIZE. 533 */ 534 dino_cfg_write(dev->bus, dev->devfn, 535 PCI_CACHE_LINE_SIZE, 2, 0xff00 | L1_CACHE_BYTES/4); 536 537 /* 538 ** Program INT_LINE for card-mode devices. 539 ** The cards are hardwired according to this algorithm. 540 ** And it doesn't matter if PPB's are present or not since 541 ** the IRQ lines bypass the PPB. 542 ** 543 ** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range. 544 ** The additional "-1" adjusts for skewing the IRQ<->slot. 545 */ 546 dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 1, &irq_pin); 547 dev->irq = pci_swizzle_interrupt_pin(dev, irq_pin) - 1; 548 549 /* Shouldn't really need to do this but it's in case someone tries 550 ** to bypass PCI services and look at the card themselves. 551 */ 552 dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 1, dev->irq); 553} 554 555/* The alignment contraints for PCI bridges under dino */ 556#define DINO_BRIDGE_ALIGN 0x100000 557 558 559static void __init 560dino_fixup_bus(struct pci_bus *bus) 561{ 562 struct list_head *ln; 563 struct pci_dev *dev; 564 struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge)); 565 int port_base = HBA_PORT_BASE(dino_dev->hba.hba_num); 566 567 DBG(KERN_WARNING "%s(0x%p) bus %d platform_data 0x%p\n", 568 __func__, bus, bus->secondary, 569 bus->bridge->platform_data); 570 571 /* Firmware doesn't set up card-mode dino, so we have to */ 572 if (is_card_dino(&dino_dev->hba.dev->id)) { 573 dino_card_setup(bus, dino_dev->hba.base_addr); 574 } else if(bus->parent == NULL) { 575 /* must have a dino above it, reparent the resources 576 * into the dino window */ 577 int i; 578 struct resource *res = &dino_dev->hba.lmmio_space; 579 580 bus->resource[0] = &(dino_dev->hba.io_space); 581 for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) { 582 if(res[i].flags == 0) 583 break; 584 bus->resource[i+1] = &res[i]; 585 } 586 587 } else if (bus->parent) { 588 int i; 589 590 pci_read_bridge_bases(bus); 591 592 593 for(i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { 594 if((bus->self->resource[i].flags & 595 (IORESOURCE_IO | IORESOURCE_MEM)) == 0) 596 continue; 597 598 if(bus->self->resource[i].flags & IORESOURCE_MEM) { 599 /* There's a quirk to alignment of 600 * bridge memory resources: the start 601 * is the alignment and start-end is 602 * the size. However, firmware will 603 * have assigned start and end, so we 604 * need to take this into account */ 605 bus->self->resource[i].end = bus->self->resource[i].end - bus->self->resource[i].start + DINO_BRIDGE_ALIGN; 606 bus->self->resource[i].start = DINO_BRIDGE_ALIGN; 607 608 } 609 610 DBG("DEBUG %s assigning %d [0x%lx,0x%lx]\n", 611 dev_name(&bus->self->dev), i, 612 bus->self->resource[i].start, 613 bus->self->resource[i].end); 614 WARN_ON(pci_assign_resource(bus->self, i)); 615 DBG("DEBUG %s after assign %d [0x%lx,0x%lx]\n", 616 dev_name(&bus->self->dev), i, 617 bus->self->resource[i].start, 618 bus->self->resource[i].end); 619 } 620 } 621 622 623 list_for_each(ln, &bus->devices) { 624 int i; 625 626 dev = pci_dev_b(ln); 627 if (is_card_dino(&dino_dev->hba.dev->id)) 628 dino_card_fixup(dev); 629 630 /* 631 ** P2PB's only have 2 BARs, no IRQs. 632 ** I'd like to just ignore them for now. 633 */ 634 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) 635 continue; 636 637 /* Adjust the I/O Port space addresses */ 638 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 639 struct resource *res = &dev->resource[i]; 640 if (res->flags & IORESOURCE_IO) { 641 res->start |= port_base; 642 res->end |= port_base; 643 } 644#ifdef __LP64__ 645 /* Sign Extend MMIO addresses */ 646 else if (res->flags & IORESOURCE_MEM) { 647 res->start |= F_EXTEND(0UL); 648 res->end |= F_EXTEND(0UL); 649 } 650#endif 651 } 652 /* null out the ROM resource if there is one (we don't 653 * care about an expansion rom on parisc, since it 654 * usually contains (x86) bios code) */ 655 dev->resource[PCI_ROM_RESOURCE].flags = 0; 656 657 if(dev->irq == 255) { 658 659#define DINO_FIX_UNASSIGNED_INTERRUPTS 660#ifdef DINO_FIX_UNASSIGNED_INTERRUPTS 661 662 /* This code tries to assign an unassigned 663 * interrupt. Leave it disabled unless you 664 * *really* know what you're doing since the 665 * pin<->interrupt line mapping varies by bus 666 * and machine */ 667 668 u32 irq_pin; 669 670 dino_cfg_read(dev->bus, dev->devfn, 671 PCI_INTERRUPT_PIN, 1, &irq_pin); 672 irq_pin = pci_swizzle_interrupt_pin(dev, irq_pin) - 1; 673 printk(KERN_WARNING "Device %s has undefined IRQ, " 674 "setting to %d\n", pci_name(dev), irq_pin); 675 dino_cfg_write(dev->bus, dev->devfn, 676 PCI_INTERRUPT_LINE, 1, irq_pin); 677 dino_assign_irq(dino_dev, irq_pin, &dev->irq); 678#else 679 dev->irq = 65535; 680 printk(KERN_WARNING "Device %s has unassigned IRQ\n", pci_name(dev)); 681#endif 682 } else { 683 /* Adjust INT_LINE for that busses region */ 684 dino_assign_irq(dino_dev, dev->irq, &dev->irq); 685 } 686 } 687} 688 689 690static struct pci_bios_ops dino_bios_ops = { 691 .init = dino_bios_init, 692 .fixup_bus = dino_fixup_bus 693}; 694 695 696/* 697 * Initialise a DINO controller chip 698 */ 699static void __init 700dino_card_init(struct dino_device *dino_dev) 701{ 702 u32 brdg_feat = 0x00784e05; 703 unsigned long status; 704 705 status = __raw_readl(dino_dev->hba.base_addr+DINO_IO_STATUS); 706 if (status & 0x0000ff80) { 707 __raw_writel(0x00000005, 708 dino_dev->hba.base_addr+DINO_IO_COMMAND); 709 udelay(1); 710 } 711 712 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK); 713 __raw_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN); 714 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR); 715 716/* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */ 717 /* 718 ** PCX-L processors don't support XQL like Dino wants it. 719 ** PCX-L2 ignore XQL signal and it doesn't matter. 720 */ 721 brdg_feat &= ~0x4; /* UXQL */ 722 __raw_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT); 723 724 /* 725 ** Don't enable address decoding until we know which I/O range 726 ** currently is available from the host. Only affects MMIO 727 ** and not I/O port space. 728 */ 729 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN); 730 731 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE); 732 __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR); 733 __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR); 734 735 __raw_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM); 736 __raw_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL); 737 __raw_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM); 738 739 /* Disable PAMR before writing PAPR */ 740 __raw_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR); 741 __raw_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR); 742 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR); 743 744 /* 745 ** Dino ERS encourages enabling FBB (0x6f). 746 ** We can't until we know *all* devices below us can support it. 747 ** (Something in device configuration header tells us). 748 */ 749 __raw_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD); 750 751 /* Somewhere, the PCI spec says give devices 1 second 752 ** to recover from the #RESET being de-asserted. 753 ** Experience shows most devices only need 10ms. 754 ** This short-cut speeds up booting significantly. 755 */ 756 mdelay(pci_post_reset_delay); 757} 758 759static int __init 760dino_bridge_init(struct dino_device *dino_dev, const char *name) 761{ 762 unsigned long io_addr; 763 int result, i, count=0; 764 struct resource *res, *prevres = NULL; 765 /* 766 * Decoding IO_ADDR_EN only works for Built-in Dino 767 * since PDC has already initialized this. 768 */ 769 770 io_addr = __raw_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN); 771 if (io_addr == 0) { 772 printk(KERN_WARNING "%s: No PCI devices enabled.\n", name); 773 return -ENODEV; 774 } 775 776 res = &dino_dev->hba.lmmio_space; 777 for (i = 0; i < 32; i++) { 778 unsigned long start, end; 779 780 if((io_addr & (1 << i)) == 0) 781 continue; 782 783 start = F_EXTEND(0xf0000000UL) | (i << 23); 784 end = start + 8 * 1024 * 1024 - 1; 785 786 DBG("DINO RANGE %d is at 0x%lx-0x%lx\n", count, 787 start, end); 788 789 if(prevres && prevres->end + 1 == start) { 790 prevres->end = end; 791 } else { 792 if(count >= DINO_MAX_LMMIO_RESOURCES) { 793 printk(KERN_ERR "%s is out of resource windows for range %d (0x%lx-0x%lx)\n", name, count, start, end); 794 break; 795 } 796 prevres = res; 797 res->start = start; 798 res->end = end; 799 res->flags = IORESOURCE_MEM; 800 res->name = kmalloc(64, GFP_KERNEL); 801 if(res->name) 802 snprintf((char *)res->name, 64, "%s LMMIO %d", 803 name, count); 804 res++; 805 count++; 806 } 807 } 808 809 res = &dino_dev->hba.lmmio_space; 810 811 for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) { 812 if(res[i].flags == 0) 813 break; 814 815 result = ccio_request_resource(dino_dev->hba.dev, &res[i]); 816 if (result < 0) { 817 printk(KERN_ERR "%s: failed to claim PCI Bus address " 818 "space %d (0x%lx-0x%lx)!\n", name, i, 819 (unsigned long)res[i].start, (unsigned long)res[i].end); 820 return result; 821 } 822 } 823 return 0; 824} 825 826static int __init dino_common_init(struct parisc_device *dev, 827 struct dino_device *dino_dev, const char *name) 828{ 829 int status; 830 u32 eim; 831 struct gsc_irq gsc_irq; 832 struct resource *res; 833 834 pcibios_register_hba(&dino_dev->hba); 835 836 pci_bios = &dino_bios_ops; /* used by pci_scan_bus() */ 837 pci_port = &dino_port_ops; 838 839 /* 840 ** Note: SMP systems can make use of IRR1/IAR1 registers 841 ** But it won't buy much performance except in very 842 ** specific applications/configurations. Note Dino 843 ** still only has 11 IRQ input lines - just map some of them 844 ** to a different processor. 845 */ 846 dev->irq = gsc_alloc_irq(&gsc_irq); 847 dino_dev->txn_addr = gsc_irq.txn_addr; 848 dino_dev->txn_data = gsc_irq.txn_data; 849 eim = ((u32) gsc_irq.txn_addr) | gsc_irq.txn_data; 850 851 /* 852 ** Dino needs a PA "IRQ" to get a processor's attention. 853 ** arch/parisc/kernel/irq.c returns an EIRR bit. 854 */ 855 if (dev->irq < 0) { 856 printk(KERN_WARNING "%s: gsc_alloc_irq() failed\n", name); 857 return 1; 858 } 859 860 status = request_irq(dev->irq, dino_isr, 0, name, dino_dev); 861 if (status) { 862 printk(KERN_WARNING "%s: request_irq() failed with %d\n", 863 name, status); 864 return 1; 865 } 866 867 /* Support the serial port which is sometimes attached on built-in 868 * Dino / Cujo chips. 869 */ 870 871 gsc_fixup_irqs(dev, dino_dev, dino_choose_irq); 872 873 /* 874 ** This enables DINO to generate interrupts when it sees 875 ** any of its inputs *change*. Just asserting an IRQ 876 ** before it's enabled (ie unmasked) isn't good enough. 877 */ 878 __raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0); 879 880 /* 881 ** Some platforms don't clear Dino's IRR0 register at boot time. 882 ** Reading will clear it now. 883 */ 884 __raw_readl(dino_dev->hba.base_addr+DINO_IRR0); 885 886 /* allocate I/O Port resource region */ 887 res = &dino_dev->hba.io_space; 888 if (!is_cujo(&dev->id)) { 889 res->name = "Dino I/O Port"; 890 } else { 891 res->name = "Cujo I/O Port"; 892 } 893 res->start = HBA_PORT_BASE(dino_dev->hba.hba_num); 894 res->end = res->start + (HBA_PORT_SPACE_SIZE - 1); 895 res->flags = IORESOURCE_IO; /* do not mark it busy ! */ 896 if (request_resource(&ioport_resource, res) < 0) { 897 printk(KERN_ERR "%s: request I/O Port region failed " 898 "0x%lx/%lx (hpa 0x%p)\n", 899 name, (unsigned long)res->start, (unsigned long)res->end, 900 dino_dev->hba.base_addr); 901 return 1; 902 } 903 904 return 0; 905} 906 907#define CUJO_RAVEN_ADDR F_EXTEND(0xf1000000UL) 908#define CUJO_FIREHAWK_ADDR F_EXTEND(0xf1604000UL) 909#define CUJO_RAVEN_BADPAGE 0x01003000UL 910#define CUJO_FIREHAWK_BADPAGE 0x01607000UL 911 912static const char *dino_vers[] = { 913 "2.0", 914 "2.1", 915 "3.0", 916 "3.1" 917}; 918 919static const char *cujo_vers[] = { 920 "1.0", 921 "2.0" 922}; 923 924void ccio_cujo20_fixup(struct parisc_device *dev, u32 iovp); 925 926/* 927** Determine if dino should claim this chip (return 0) or not (return 1). 928** If so, initialize the chip appropriately (card-mode vs bridge mode). 929** Much of the initialization is common though. 930*/ 931static int __init dino_probe(struct parisc_device *dev) 932{ 933 struct dino_device *dino_dev; // Dino specific control struct 934 const char *version = "unknown"; 935 char *name; 936 int is_cujo = 0; 937 struct pci_bus *bus; 938 unsigned long hpa = dev->hpa.start; 939 940 name = "Dino"; 941 if (is_card_dino(&dev->id)) { 942 version = "3.x (card mode)"; 943 } else { 944 if (!is_cujo(&dev->id)) { 945 if (dev->id.hversion_rev < 4) { 946 version = dino_vers[dev->id.hversion_rev]; 947 } 948 } else { 949 name = "Cujo"; 950 is_cujo = 1; 951 if (dev->id.hversion_rev < 2) { 952 version = cujo_vers[dev->id.hversion_rev]; 953 } 954 } 955 } 956 957 printk("%s version %s found at 0x%lx\n", name, version, hpa); 958 959 if (!request_mem_region(hpa, PAGE_SIZE, name)) { 960 printk(KERN_ERR "DINO: Hey! Someone took my MMIO space (0x%ld)!\n", 961 hpa); 962 return 1; 963 } 964 965 /* Check for bugs */ 966 if (is_cujo && dev->id.hversion_rev == 1) { 967#ifdef CONFIG_IOMMU_CCIO 968 printk(KERN_WARNING "Enabling Cujo 2.0 bug workaround\n"); 969 if (hpa == (unsigned long)CUJO_RAVEN_ADDR) { 970 ccio_cujo20_fixup(dev, CUJO_RAVEN_BADPAGE); 971 } else if (hpa == (unsigned long)CUJO_FIREHAWK_ADDR) { 972 ccio_cujo20_fixup(dev, CUJO_FIREHAWK_BADPAGE); 973 } else { 974 printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n", hpa); 975 } 976#endif 977 } else if (!is_cujo && !is_card_dino(&dev->id) && 978 dev->id.hversion_rev < 3) { 979 printk(KERN_WARNING 980"The GSCtoPCI (Dino hrev %d) bus converter found may exhibit\n" 981"data corruption. See Service Note Numbers: A4190A-01, A4191A-01.\n" 982"Systems shipped after Aug 20, 1997 will not exhibit this problem.\n" 983"Models affected: C180, C160, C160L, B160L, and B132L workstations.\n\n", 984 dev->id.hversion_rev); 985/* REVISIT: why are C200/C240 listed in the README table but not 986** "Models affected"? Could be an omission in the original literature. 987*/ 988 } 989 990 dino_dev = kzalloc(sizeof(struct dino_device), GFP_KERNEL); 991 if (!dino_dev) { 992 printk("dino_init_chip - couldn't alloc dino_device\n"); 993 return 1; 994 } 995 996 dino_dev->hba.dev = dev; 997 dino_dev->hba.base_addr = ioremap_nocache(hpa, 4096); 998 dino_dev->hba.lmmio_space_offset = 0; /* CPU addrs == bus addrs */ 999 spin_lock_init(&dino_dev->dinosaur_pen); 1000 dino_dev->hba.iommu = ccio_get_iommu(dev); 1001 1002 if (is_card_dino(&dev->id)) { 1003 dino_card_init(dino_dev); 1004 } else { 1005 dino_bridge_init(dino_dev, name); 1006 } 1007 1008 if (dino_common_init(dev, dino_dev, name)) 1009 return 1; 1010 1011 dev->dev.platform_data = dino_dev; 1012 1013 /* 1014 ** It's not used to avoid chicken/egg problems 1015 ** with configuration accessor functions. 1016 */ 1017 dino_dev->hba.hba_bus = bus = pci_scan_bus_parented(&dev->dev, 1018 dino_current_bus, &dino_cfg_ops, NULL); 1019 1020 if(bus) { 1021 /* This code *depends* on scanning being single threaded 1022 * if it isn't, this global bus number count will fail 1023 */ 1024 dino_current_bus = bus->subordinate + 1; 1025 pci_bus_assign_resources(bus); 1026 pci_bus_add_devices(bus); 1027 } else { 1028 printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (duplicate bus number %d?)\n", 1029 dev_name(&dev->dev), dino_current_bus); 1030 /* increment the bus number in case of duplicates */ 1031 dino_current_bus++; 1032 } 1033 return 0; 1034} 1035 1036/* 1037 * Normally, we would just test sversion. But the Elroy PCI adapter has 1038 * the same sversion as Dino, so we have to check hversion as well. 1039 * Unfortunately, the J2240 PDC reports the wrong hversion for the first 1040 * Dino, so we have to test for Dino, Cujo and Dino-in-a-J2240. 1041 * For card-mode Dino, most machines report an sversion of 9D. But 715 1042 * and 725 firmware misreport it as 0x08080 for no adequately explained 1043 * reason. 1044 */ 1045static struct parisc_device_id dino_tbl[] = { 1046 { HPHW_A_DMA, HVERSION_REV_ANY_ID, 0x004, 0x0009D },/* Card-mode Dino */ 1047 { HPHW_A_DMA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x08080 }, 1048 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x680, 0xa }, /* Bridge-mode Dino */ 1049 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x682, 0xa }, /* Bridge-mode Cujo */ 1050 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x05d, 0xa }, /* Dino in a J2240 */ 1051 { 0, } 1052}; 1053 1054static struct parisc_driver dino_driver = { 1055 .name = "dino", 1056 .id_table = dino_tbl, 1057 .probe = dino_probe, 1058}; 1059 1060/* 1061 * One time initialization to let the world know Dino is here. 1062 * This is the only routine which is NOT static. 1063 * Must be called exactly once before pci_init(). 1064 */ 1065int __init dino_init(void) 1066{ 1067 register_parisc_driver(&dino_driver); 1068 return 0; 1069} 1070