1/* 2 * This file is part of wl12xx 3 * 4 * Copyright (C) 1998-2009 Texas Instruments. All rights reserved. 5 * Copyright (C) 2009 Nokia Corporation 6 * 7 * Contact: Luciano Coelho <luciano.coelho@nokia.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * version 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 21 * 02110-1301 USA 22 * 23 */ 24 25#ifndef __REG_H__ 26#define __REG_H__ 27 28#include <linux/bitops.h> 29 30#define REGISTERS_BASE 0x00300000 31#define DRPW_BASE 0x00310000 32 33#define REGISTERS_DOWN_SIZE 0x00008800 34#define REGISTERS_WORK_SIZE 0x0000b000 35 36#define HW_ACCESS_ELP_CTRL_REG_ADDR 0x1FFFC 37#define FW_STATUS_ADDR (0x14FC0 + 0xA000) 38 39/* ELP register commands */ 40#define ELPCTRL_WAKE_UP 0x1 41#define ELPCTRL_WAKE_UP_WLAN_READY 0x5 42#define ELPCTRL_SLEEP 0x0 43/* ELP WLAN_READY bit */ 44#define ELPCTRL_WLAN_READY 0x2 45 46/*=============================================== 47 Host Software Reset - 32bit RW 48 ------------------------------------------ 49 [31:1] Reserved 50 0 SOFT_RESET Soft Reset - When this bit is set, 51 it holds the Wlan hardware in a soft reset state. 52 This reset disables all MAC and baseband processor 53 clocks except the CardBus/PCI interface clock. 54 It also initializes all MAC state machines except 55 the host interface. It does not reload the 56 contents of the EEPROM. When this bit is cleared 57 (not self-clearing), the Wlan hardware 58 exits the software reset state. 59===============================================*/ 60#define ACX_REG_SLV_SOFT_RESET (REGISTERS_BASE + 0x0000) 61 62#define WL1271_SLV_REG_DATA (REGISTERS_BASE + 0x0008) 63#define WL1271_SLV_REG_ADATA (REGISTERS_BASE + 0x000c) 64#define WL1271_SLV_MEM_DATA (REGISTERS_BASE + 0x0018) 65 66#define ACX_REG_INTERRUPT_TRIG (REGISTERS_BASE + 0x0474) 67#define ACX_REG_INTERRUPT_TRIG_H (REGISTERS_BASE + 0x0478) 68 69/*============================================= 70 Host Interrupt Mask Register - 32bit (RW) 71 ------------------------------------------ 72 Setting a bit in this register masks the 73 corresponding interrupt to the host. 74 0 - RX0 - Rx first dubble buffer Data Interrupt 75 1 - TXD - Tx Data Interrupt 76 2 - TXXFR - Tx Transfer Interrupt 77 3 - RX1 - Rx second dubble buffer Data Interrupt 78 4 - RXXFR - Rx Transfer Interrupt 79 5 - EVENT_A - Event Mailbox interrupt 80 6 - EVENT_B - Event Mailbox interrupt 81 7 - WNONHST - Wake On Host Interrupt 82 8 - TRACE_A - Debug Trace interrupt 83 9 - TRACE_B - Debug Trace interrupt 84 10 - CDCMP - Command Complete Interrupt 85 11 - 86 12 - 87 13 - 88 14 - ICOMP - Initialization Complete Interrupt 89 16 - SG SE - Soft Gemini - Sense enable interrupt 90 17 - SG SD - Soft Gemini - Sense disable interrupt 91 18 - - 92 19 - - 93 20 - - 94 21- - 95 Default: 0x0001 96*==============================================*/ 97#define ACX_REG_INTERRUPT_MASK (REGISTERS_BASE + 0x04DC) 98 99/*============================================= 100 Host Interrupt Mask Set 16bit, (Write only) 101 ------------------------------------------ 102 Setting a bit in this register sets 103 the corresponding bin in ACX_HINT_MASK register 104 without effecting the mask 105 state of other bits (0 = no effect). 106==============================================*/ 107#define ACX_REG_HINT_MASK_SET (REGISTERS_BASE + 0x04E0) 108 109/*============================================= 110 Host Interrupt Mask Clear 16bit,(Write only) 111 ------------------------------------------ 112 Setting a bit in this register clears 113 the corresponding bin in ACX_HINT_MASK register 114 without effecting the mask 115 state of other bits (0 = no effect). 116=============================================*/ 117#define ACX_REG_HINT_MASK_CLR (REGISTERS_BASE + 0x04E4) 118 119/*============================================= 120 Host Interrupt Status Nondestructive Read 121 16bit,(Read only) 122 ------------------------------------------ 123 The host can read this register to determine 124 which interrupts are active. 125 Reading this register doesn't 126 effect its content. 127=============================================*/ 128#define ACX_REG_INTERRUPT_NO_CLEAR (REGISTERS_BASE + 0x04E8) 129 130/*============================================= 131 Host Interrupt Status Clear on Read Register 132 16bit,(Read only) 133 ------------------------------------------ 134 The host can read this register to determine 135 which interrupts are active. 136 Reading this register clears it, 137 thus making all interrupts inactive. 138==============================================*/ 139#define ACX_REG_INTERRUPT_CLEAR (REGISTERS_BASE + 0x04F8) 140 141/*============================================= 142 Host Interrupt Acknowledge Register 143 16bit,(Write only) 144 ------------------------------------------ 145 The host can set individual bits in this 146 register to clear (acknowledge) the corresp. 147 interrupt status bits in the HINT_STS_CLR and 148 HINT_STS_ND registers, thus making the 149 assotiated interrupt inactive. (0-no effect) 150==============================================*/ 151#define ACX_REG_INTERRUPT_ACK (REGISTERS_BASE + 0x04F0) 152 153#define RX_DRIVER_COUNTER_ADDRESS (REGISTERS_BASE + 0x0538) 154 155/* Device Configuration registers*/ 156#define SOR_CFG (REGISTERS_BASE + 0x0800) 157 158/* Embedded ARM CPU Control */ 159 160/*=============================================== 161 Halt eCPU - 32bit RW 162 ------------------------------------------ 163 0 HALT_ECPU Halt Embedded CPU - This bit is the 164 compliment of bit 1 (MDATA2) in the SOR_CFG register. 165 During a hardware reset, this bit holds 166 the inverse of MDATA2. 167 When downloading firmware from the host, 168 set this bit (pull down MDATA2). 169 The host clears this bit after downloading the firmware into 170 zero-wait-state SSRAM. 171 When loading firmware from Flash, clear this bit (pull up MDATA2) 172 so that the eCPU can run the bootloader code in Flash 173 HALT_ECPU eCPU State 174 -------------------- 175 1 halt eCPU 176 0 enable eCPU 177 ===============================================*/ 178#define ACX_REG_ECPU_CONTROL (REGISTERS_BASE + 0x0804) 179 180#define HI_CFG (REGISTERS_BASE + 0x0808) 181 182/*=============================================== 183 EEPROM Burst Read Start - 32bit RW 184 ------------------------------------------ 185 [31:1] Reserved 186 0 ACX_EE_START - EEPROM Burst Read Start 0 187 Setting this bit starts a burst read from 188 the external EEPROM. 189 If this bit is set (after reset) before an EEPROM read/write, 190 the burst read starts at EEPROM address 0. 191 Otherwise, it starts at the address 192 following the address of the previous access. 193 TheWlan hardware hardware clears this bit automatically. 194 195 Default: 0x00000000 196*================================================*/ 197#define ACX_REG_EE_START (REGISTERS_BASE + 0x080C) 198 199#define OCP_POR_CTR (REGISTERS_BASE + 0x09B4) 200#define OCP_DATA_WRITE (REGISTERS_BASE + 0x09B8) 201#define OCP_DATA_READ (REGISTERS_BASE + 0x09BC) 202#define OCP_CMD (REGISTERS_BASE + 0x09C0) 203 204#define WL1271_HOST_WR_ACCESS (REGISTERS_BASE + 0x09F8) 205 206#define CHIP_ID_B (REGISTERS_BASE + 0x5674) 207 208#define CHIP_ID_1271_PG10 (0x4030101) 209#define CHIP_ID_1271_PG20 (0x4030111) 210 211#define ENABLE (REGISTERS_BASE + 0x5450) 212 213/* Power Management registers */ 214#define ELP_CFG_MODE (REGISTERS_BASE + 0x5804) 215#define ELP_CMD (REGISTERS_BASE + 0x5808) 216#define PLL_CAL_TIME (REGISTERS_BASE + 0x5810) 217#define CLK_REQ_TIME (REGISTERS_BASE + 0x5814) 218#define CLK_BUF_TIME (REGISTERS_BASE + 0x5818) 219 220#define CFG_PLL_SYNC_CNT (REGISTERS_BASE + 0x5820) 221 222/* Scratch Pad registers*/ 223#define SCR_PAD0 (REGISTERS_BASE + 0x5608) 224#define SCR_PAD1 (REGISTERS_BASE + 0x560C) 225#define SCR_PAD2 (REGISTERS_BASE + 0x5610) 226#define SCR_PAD3 (REGISTERS_BASE + 0x5614) 227#define SCR_PAD4 (REGISTERS_BASE + 0x5618) 228#define SCR_PAD4_SET (REGISTERS_BASE + 0x561C) 229#define SCR_PAD4_CLR (REGISTERS_BASE + 0x5620) 230#define SCR_PAD5 (REGISTERS_BASE + 0x5624) 231#define SCR_PAD5_SET (REGISTERS_BASE + 0x5628) 232#define SCR_PAD5_CLR (REGISTERS_BASE + 0x562C) 233#define SCR_PAD6 (REGISTERS_BASE + 0x5630) 234#define SCR_PAD7 (REGISTERS_BASE + 0x5634) 235#define SCR_PAD8 (REGISTERS_BASE + 0x5638) 236#define SCR_PAD9 (REGISTERS_BASE + 0x563C) 237 238/* Spare registers*/ 239#define SPARE_A1 (REGISTERS_BASE + 0x0994) 240#define SPARE_A2 (REGISTERS_BASE + 0x0998) 241#define SPARE_A3 (REGISTERS_BASE + 0x099C) 242#define SPARE_A4 (REGISTERS_BASE + 0x09A0) 243#define SPARE_A5 (REGISTERS_BASE + 0x09A4) 244#define SPARE_A6 (REGISTERS_BASE + 0x09A8) 245#define SPARE_A7 (REGISTERS_BASE + 0x09AC) 246#define SPARE_A8 (REGISTERS_BASE + 0x09B0) 247#define SPARE_B1 (REGISTERS_BASE + 0x5420) 248#define SPARE_B2 (REGISTERS_BASE + 0x5424) 249#define SPARE_B3 (REGISTERS_BASE + 0x5428) 250#define SPARE_B4 (REGISTERS_BASE + 0x542C) 251#define SPARE_B5 (REGISTERS_BASE + 0x5430) 252#define SPARE_B6 (REGISTERS_BASE + 0x5434) 253#define SPARE_B7 (REGISTERS_BASE + 0x5438) 254#define SPARE_B8 (REGISTERS_BASE + 0x543C) 255 256#define PLL_PARAMETERS (REGISTERS_BASE + 0x6040) 257#define WU_COUNTER_PAUSE (REGISTERS_BASE + 0x6008) 258#define WELP_ARM_COMMAND (REGISTERS_BASE + 0x6100) 259#define DRPW_SCRATCH_START (DRPW_BASE + 0x002C) 260 261 262#define ACX_SLV_SOFT_RESET_BIT BIT(1) 263#define ACX_REG_EEPROM_START_BIT BIT(1) 264 265/* Command/Information Mailbox Pointers */ 266 267/*=============================================== 268 Command Mailbox Pointer - 32bit RW 269 ------------------------------------------ 270 This register holds the start address of 271 the command mailbox located in the Wlan hardware memory. 272 The host must read this pointer after a reset to 273 find the location of the command mailbox. 274 The Wlan hardware initializes the command mailbox 275 pointer with the default address of the command mailbox. 276 The command mailbox pointer is not valid until after 277 the host receives the Init Complete interrupt from 278 the Wlan hardware. 279 ===============================================*/ 280#define REG_COMMAND_MAILBOX_PTR (SCR_PAD0) 281 282/*=============================================== 283 Information Mailbox Pointer - 32bit RW 284 ------------------------------------------ 285 This register holds the start address of 286 the information mailbox located in the Wlan hardware memory. 287 The host must read this pointer after a reset to find 288 the location of the information mailbox. 289 The Wlan hardware initializes the information mailbox pointer 290 with the default address of the information mailbox. 291 The information mailbox pointer is not valid 292 until after the host receives the Init Complete interrupt from 293 the Wlan hardware. 294 ===============================================*/ 295#define REG_EVENT_MAILBOX_PTR (SCR_PAD1) 296 297 298/* Misc */ 299 300#define REG_ENABLE_TX_RX (ENABLE) 301/* 302 * Rx configuration (filter) information element 303 * --------------------------------------------- 304 */ 305#define REG_RX_CONFIG (RX_CFG) 306#define REG_RX_FILTER (RX_FILTER_CFG) 307 308 309#define RX_CFG_ENABLE_PHY_HEADER_PLCP 0x0002 310 311/* promiscuous - receives all valid frames */ 312#define RX_CFG_PROMISCUOUS 0x0008 313 314/* receives frames from any BSSID */ 315#define RX_CFG_BSSID 0x0020 316 317/* receives frames destined to any MAC address */ 318#define RX_CFG_MAC 0x0010 319 320#define RX_CFG_ENABLE_ONLY_MY_DEST_MAC 0x0010 321#define RX_CFG_ENABLE_ANY_DEST_MAC 0x0000 322#define RX_CFG_ENABLE_ONLY_MY_BSSID 0x0020 323#define RX_CFG_ENABLE_ANY_BSSID 0x0000 324 325/* discards all broadcast frames */ 326#define RX_CFG_DISABLE_BCAST 0x0200 327 328#define RX_CFG_ENABLE_ONLY_MY_SSID 0x0400 329#define RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR 0x0800 330#define RX_CFG_COPY_RX_STATUS 0x2000 331#define RX_CFG_TSF 0x10000 332 333#define RX_CONFIG_OPTION_ANY_DST_MY_BSS (RX_CFG_ENABLE_ANY_DEST_MAC | \ 334 RX_CFG_ENABLE_ONLY_MY_BSSID) 335 336#define RX_CONFIG_OPTION_MY_DST_ANY_BSS (RX_CFG_ENABLE_ONLY_MY_DEST_MAC\ 337 | RX_CFG_ENABLE_ANY_BSSID) 338 339#define RX_CONFIG_OPTION_ANY_DST_ANY_BSS (RX_CFG_ENABLE_ANY_DEST_MAC | \ 340 RX_CFG_ENABLE_ANY_BSSID) 341 342#define RX_CONFIG_OPTION_MY_DST_MY_BSS (RX_CFG_ENABLE_ONLY_MY_DEST_MAC\ 343 | RX_CFG_ENABLE_ONLY_MY_BSSID) 344 345#define RX_CONFIG_OPTION_FOR_SCAN (RX_CFG_ENABLE_PHY_HEADER_PLCP \ 346 | RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR \ 347 | RX_CFG_COPY_RX_STATUS | RX_CFG_TSF) 348 349#define RX_CONFIG_OPTION_FOR_MEASUREMENT (RX_CFG_ENABLE_ANY_DEST_MAC) 350 351#define RX_CONFIG_OPTION_FOR_JOIN (RX_CFG_ENABLE_ONLY_MY_BSSID | \ 352 RX_CFG_ENABLE_ONLY_MY_DEST_MAC) 353 354#define RX_CONFIG_OPTION_FOR_IBSS_JOIN (RX_CFG_ENABLE_ONLY_MY_SSID | \ 355 RX_CFG_ENABLE_ONLY_MY_DEST_MAC) 356 357#define RX_FILTER_OPTION_DEF (CFG_RX_MGMT_EN | CFG_RX_DATA_EN\ 358 | CFG_RX_CTL_EN | CFG_RX_BCN_EN\ 359 | CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN) 360 361#define RX_FILTER_OPTION_FILTER_ALL 0 362 363#define RX_FILTER_OPTION_DEF_PRSP_BCN (CFG_RX_PRSP_EN | CFG_RX_MGMT_EN\ 364 | CFG_RX_RCTS_ACK | CFG_RX_BCN_EN) 365 366#define RX_FILTER_OPTION_JOIN (CFG_RX_MGMT_EN | CFG_RX_DATA_EN\ 367 | CFG_RX_BCN_EN | CFG_RX_AUTH_EN\ 368 | CFG_RX_ASSOC_EN | CFG_RX_RCTS_ACK\ 369 | CFG_RX_PRSP_EN) 370 371 372/*=============================================== 373 EEPROM Read/Write Request 32bit RW 374 ------------------------------------------ 375 1 EE_READ - EEPROM Read Request 1 - Setting this bit 376 loads a single byte of data into the EE_DATA 377 register from the EEPROM location specified in 378 the EE_ADDR register. 379 The Wlan hardware hardware clears this bit automatically. 380 EE_DATA is valid when this bit is cleared. 381 382 0 EE_WRITE - EEPROM Write Request - Setting this bit 383 writes a single byte of data from the EE_DATA register into the 384 EEPROM location specified in the EE_ADDR register. 385 The Wlan hardware hardware clears this bit automatically. 386*===============================================*/ 387#define ACX_EE_CTL_REG EE_CTL 388#define EE_WRITE 0x00000001ul 389#define EE_READ 0x00000002ul 390 391/*=============================================== 392 EEPROM Address - 32bit RW 393 ------------------------------------------ 394 This register specifies the address 395 within the EEPROM from/to which to read/write data. 396 ===============================================*/ 397#define ACX_EE_ADDR_REG EE_ADDR 398 399/*=============================================== 400 EEPROM Data - 32bit RW 401 ------------------------------------------ 402 This register either holds the read 8 bits of 403 data from the EEPROM or the write data 404 to be written to the EEPROM. 405 ===============================================*/ 406#define ACX_EE_DATA_REG EE_DATA 407 408/*=============================================== 409 EEPROM Base Address - 32bit RW 410 ------------------------------------------ 411 This register holds the upper nine bits 412 [23:15] of the 24-bit Wlan hardware memory 413 address for burst reads from EEPROM accesses. 414 The EEPROM provides the lower 15 bits of this address. 415 The MSB of the address from the EEPROM is ignored. 416 ===============================================*/ 417#define ACX_EE_CFG EE_CFG 418 419/*=============================================== 420 GPIO Output Values -32bit, RW 421 ------------------------------------------ 422 [31:16] Reserved 423 [15: 0] Specify the output values (at the output driver inputs) for 424 GPIO[15:0], respectively. 425 ===============================================*/ 426#define ACX_GPIO_OUT_REG GPIO_OUT 427#define ACX_MAX_GPIO_LINES 15 428 429/*=============================================== 430 Contention window -32bit, RW 431 ------------------------------------------ 432 [31:26] Reserved 433 [25:16] Max (0x3ff) 434 [15:07] Reserved 435 [06:00] Current contention window value - default is 0x1F 436 ===============================================*/ 437#define ACX_CONT_WIND_CFG_REG CONT_WIND_CFG 438#define ACX_CONT_WIND_MIN_MASK 0x0000007f 439#define ACX_CONT_WIND_MAX 0x03ff0000 440 441/*=============================================== 442 HI_CFG Interface Configuration Register Values 443 ------------------------------------------ 444 ===============================================*/ 445#define HI_CFG_UART_ENABLE 0x00000004 446#define HI_CFG_RST232_ENABLE 0x00000008 447#define HI_CFG_CLOCK_REQ_SELECT 0x00000010 448#define HI_CFG_HOST_INT_ENABLE 0x00000020 449#define HI_CFG_VLYNQ_OUTPUT_ENABLE 0x00000040 450#define HI_CFG_HOST_INT_ACTIVE_LOW 0x00000080 451#define HI_CFG_UART_TX_OUT_GPIO_15 0x00000100 452#define HI_CFG_UART_TX_OUT_GPIO_14 0x00000200 453#define HI_CFG_UART_TX_OUT_GPIO_7 0x00000400 454 455/* 456 * NOTE: USE_ACTIVE_HIGH compilation flag should be defined in makefile 457 * for platforms using active high interrupt level 458 */ 459#ifdef USE_ACTIVE_HIGH 460#define HI_CFG_DEF_VAL \ 461 (HI_CFG_UART_ENABLE | \ 462 HI_CFG_RST232_ENABLE | \ 463 HI_CFG_CLOCK_REQ_SELECT | \ 464 HI_CFG_HOST_INT_ENABLE) 465#else 466#define HI_CFG_DEF_VAL \ 467 (HI_CFG_UART_ENABLE | \ 468 HI_CFG_RST232_ENABLE | \ 469 HI_CFG_CLOCK_REQ_SELECT | \ 470 HI_CFG_HOST_INT_ENABLE) 471 472#endif 473 474#define REF_FREQ_19_2 0 475#define REF_FREQ_26_0 1 476#define REF_FREQ_38_4 2 477#define REF_FREQ_40_0 3 478#define REF_FREQ_33_6 4 479#define REF_FREQ_NUM 5 480 481#define LUT_PARAM_INTEGER_DIVIDER 0 482#define LUT_PARAM_FRACTIONAL_DIVIDER 1 483#define LUT_PARAM_ATTN_BB 2 484#define LUT_PARAM_ALPHA_BB 3 485#define LUT_PARAM_STOP_TIME_BB 4 486#define LUT_PARAM_BB_PLL_LOOP_FILTER 5 487#define LUT_PARAM_NUM 6 488 489#define ACX_EEPROMLESS_IND_REG (SCR_PAD4) 490#define USE_EEPROM 0 491#define SOFT_RESET_MAX_TIME 1000000 492#define SOFT_RESET_STALL_TIME 1000 493#define NVS_DATA_BUNDARY_ALIGNMENT 4 494 495 496/* Firmware image load chunk size */ 497#define CHUNK_SIZE 512 498 499/* Firmware image header size */ 500#define FW_HDR_SIZE 8 501 502#define ECPU_CONTROL_HALT 0x00000101 503 504 505/****************************************************************************** 506 507 CHANNELS, BAND & REG DOMAINS definitions 508 509******************************************************************************/ 510 511 512enum { 513 RADIO_BAND_2_4GHZ = 0, /* 2.4 Ghz band */ 514 RADIO_BAND_5GHZ = 1, /* 5 Ghz band */ 515 RADIO_BAND_JAPAN_4_9_GHZ = 2, 516 DEFAULT_BAND = RADIO_BAND_2_4GHZ, 517 INVALID_BAND = 0xFE, 518 MAX_RADIO_BANDS = 0xFF 519}; 520 521#define SHORT_PREAMBLE_BIT BIT(0) /* CCK or Barker depending on the rate */ 522#define OFDM_RATE_BIT BIT(6) 523#define PBCC_RATE_BIT BIT(7) 524 525enum { 526 CCK_LONG = 0, 527 CCK_SHORT = SHORT_PREAMBLE_BIT, 528 PBCC_LONG = PBCC_RATE_BIT, 529 PBCC_SHORT = PBCC_RATE_BIT | SHORT_PREAMBLE_BIT, 530 OFDM = OFDM_RATE_BIT 531}; 532 533/****************************************************************************** 534 535Transmit-Descriptor RATE-SET field definitions... 536 537Define a new "Rate-Set" for TX path that incorporates the 538Rate & Modulation info into a single 16-bit field. 539 540TxdRateSet_t: 541b15 - Indicates Preamble type (1=SHORT, 0=LONG). 542 Notes: 543 Must be LONG (0) for 1Mbps rate. 544 Does not apply (set to 0) for RevG-OFDM rates. 545b14 - Indicates PBCC encoding (1=PBCC, 0=not). 546 Notes: 547 Does not apply (set to 0) for rates 1 and 2 Mbps. 548 Does not apply (set to 0) for RevG-OFDM rates. 549b13 - Unused (set to 0). 550b12-b0 - Supported Rate indicator bits as defined below. 551 552******************************************************************************/ 553 554 555/************************************************************************* 556 557 Interrupt Trigger Register (Host -> WiLink) 558 559**************************************************************************/ 560 561/* Hardware to Embedded CPU Interrupts - first 32-bit register set */ 562 563/* 564 * Host Command Interrupt. Setting this bit masks 565 * the interrupt that the host issues to inform 566 * the FW that it has sent a command 567 * to the Wlan hardware Command Mailbox. 568 */ 569#define INTR_TRIG_CMD BIT(0) 570 571/* 572 * Host Event Acknowlegde Interrupt. The host 573 * sets this bit to acknowledge that it received 574 * the unsolicited information from the event 575 * mailbox. 576 */ 577#define INTR_TRIG_EVENT_ACK BIT(1) 578 579/* 580 * The host sets this bit to inform the Wlan 581 * FW that a TX packet is in the XFER 582 * Buffer #0. 583 */ 584#define INTR_TRIG_TX_PROC0 BIT(2) 585 586/* 587 * The host sets this bit to inform the FW 588 * that it read a packet from RX XFER 589 * Buffer #0. 590 */ 591#define INTR_TRIG_RX_PROC0 BIT(3) 592 593#define INTR_TRIG_DEBUG_ACK BIT(4) 594 595#define INTR_TRIG_STATE_CHANGED BIT(5) 596 597 598/* Hardware to Embedded CPU Interrupts - second 32-bit register set */ 599 600/* 601 * The host sets this bit to inform the FW 602 * that it read a packet from RX XFER 603 * Buffer #1. 604 */ 605#define INTR_TRIG_RX_PROC1 BIT(17) 606 607/* 608 * The host sets this bit to inform the Wlan 609 * hardware that a TX packet is in the XFER 610 * Buffer #1. 611 */ 612#define INTR_TRIG_TX_PROC1 BIT(18) 613 614#endif 615