1/* 2 * This file is part of wl1251 3 * 4 * Copyright (c) 1998-2007 Texas Instruments Incorporated 5 * Copyright (C) 2008-2009 Nokia Corporation 6 * 7 * Contact: Kalle Valo <kalle.valo@nokia.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * version 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 21 * 02110-1301 USA 22 * 23 */ 24 25#ifndef __WL1251_H__ 26#define __WL1251_H__ 27 28#include <linux/mutex.h> 29#include <linux/list.h> 30#include <linux/bitops.h> 31#include <net/mac80211.h> 32 33#define DRIVER_NAME "wl1251" 34#define DRIVER_PREFIX DRIVER_NAME ": " 35 36enum { 37 DEBUG_NONE = 0, 38 DEBUG_IRQ = BIT(0), 39 DEBUG_SPI = BIT(1), 40 DEBUG_BOOT = BIT(2), 41 DEBUG_MAILBOX = BIT(3), 42 DEBUG_NETLINK = BIT(4), 43 DEBUG_EVENT = BIT(5), 44 DEBUG_TX = BIT(6), 45 DEBUG_RX = BIT(7), 46 DEBUG_SCAN = BIT(8), 47 DEBUG_CRYPT = BIT(9), 48 DEBUG_PSM = BIT(10), 49 DEBUG_MAC80211 = BIT(11), 50 DEBUG_CMD = BIT(12), 51 DEBUG_ACX = BIT(13), 52 DEBUG_ALL = ~0, 53}; 54 55#define DEBUG_LEVEL (DEBUG_NONE) 56 57#define DEBUG_DUMP_LIMIT 1024 58 59#define wl1251_error(fmt, arg...) \ 60 printk(KERN_ERR DRIVER_PREFIX "ERROR " fmt "\n", ##arg) 61 62#define wl1251_warning(fmt, arg...) \ 63 printk(KERN_WARNING DRIVER_PREFIX "WARNING " fmt "\n", ##arg) 64 65#define wl1251_notice(fmt, arg...) \ 66 printk(KERN_INFO DRIVER_PREFIX fmt "\n", ##arg) 67 68#define wl1251_info(fmt, arg...) \ 69 printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg) 70 71#define wl1251_debug(level, fmt, arg...) \ 72 do { \ 73 if (level & DEBUG_LEVEL) \ 74 printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg); \ 75 } while (0) 76 77#define wl1251_dump(level, prefix, buf, len) \ 78 do { \ 79 if (level & DEBUG_LEVEL) \ 80 print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \ 81 DUMP_PREFIX_OFFSET, 16, 1, \ 82 buf, \ 83 min_t(size_t, len, DEBUG_DUMP_LIMIT), \ 84 0); \ 85 } while (0) 86 87#define wl1251_dump_ascii(level, prefix, buf, len) \ 88 do { \ 89 if (level & DEBUG_LEVEL) \ 90 print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \ 91 DUMP_PREFIX_OFFSET, 16, 1, \ 92 buf, \ 93 min_t(size_t, len, DEBUG_DUMP_LIMIT), \ 94 true); \ 95 } while (0) 96 97#define WL1251_DEFAULT_RX_CONFIG (CFG_UNI_FILTER_EN | \ 98 CFG_BSSID_FILTER_EN) 99 100#define WL1251_DEFAULT_RX_FILTER (CFG_RX_PRSP_EN | \ 101 CFG_RX_MGMT_EN | \ 102 CFG_RX_DATA_EN | \ 103 CFG_RX_CTL_EN | \ 104 CFG_RX_BCN_EN | \ 105 CFG_RX_AUTH_EN | \ 106 CFG_RX_ASSOC_EN) 107 108#define WL1251_BUSY_WORD_LEN 8 109 110struct boot_attr { 111 u32 radio_type; 112 u8 mac_clock; 113 u8 arm_clock; 114 int firmware_debug; 115 u32 minor; 116 u32 major; 117 u32 bugfix; 118}; 119 120enum wl1251_state { 121 WL1251_STATE_OFF, 122 WL1251_STATE_ON, 123 WL1251_STATE_PLT, 124}; 125 126enum wl1251_partition_type { 127 PART_DOWN, 128 PART_WORK, 129 PART_DRPW, 130 131 PART_TABLE_LEN 132}; 133 134struct wl1251_partition { 135 u32 size; 136 u32 start; 137}; 138 139struct wl1251_partition_set { 140 struct wl1251_partition mem; 141 struct wl1251_partition reg; 142}; 143 144struct wl1251; 145 146struct wl1251_stats { 147 struct acx_statistics *fw_stats; 148 unsigned long fw_stats_update; 149 150 unsigned int retry_count; 151 unsigned int excessive_retries; 152}; 153 154struct wl1251_debugfs { 155 struct dentry *rootdir; 156 struct dentry *fw_statistics; 157 158 struct dentry *tx_internal_desc_overflow; 159 160 struct dentry *rx_out_of_mem; 161 struct dentry *rx_hdr_overflow; 162 struct dentry *rx_hw_stuck; 163 struct dentry *rx_dropped; 164 struct dentry *rx_fcs_err; 165 struct dentry *rx_xfr_hint_trig; 166 struct dentry *rx_path_reset; 167 struct dentry *rx_reset_counter; 168 169 struct dentry *dma_rx_requested; 170 struct dentry *dma_rx_errors; 171 struct dentry *dma_tx_requested; 172 struct dentry *dma_tx_errors; 173 174 struct dentry *isr_cmd_cmplt; 175 struct dentry *isr_fiqs; 176 struct dentry *isr_rx_headers; 177 struct dentry *isr_rx_mem_overflow; 178 struct dentry *isr_rx_rdys; 179 struct dentry *isr_irqs; 180 struct dentry *isr_tx_procs; 181 struct dentry *isr_decrypt_done; 182 struct dentry *isr_dma0_done; 183 struct dentry *isr_dma1_done; 184 struct dentry *isr_tx_exch_complete; 185 struct dentry *isr_commands; 186 struct dentry *isr_rx_procs; 187 struct dentry *isr_hw_pm_mode_changes; 188 struct dentry *isr_host_acknowledges; 189 struct dentry *isr_pci_pm; 190 struct dentry *isr_wakeups; 191 struct dentry *isr_low_rssi; 192 193 struct dentry *wep_addr_key_count; 194 struct dentry *wep_default_key_count; 195 /* skipping wep.reserved */ 196 struct dentry *wep_key_not_found; 197 struct dentry *wep_decrypt_fail; 198 struct dentry *wep_packets; 199 struct dentry *wep_interrupt; 200 201 struct dentry *pwr_ps_enter; 202 struct dentry *pwr_elp_enter; 203 struct dentry *pwr_missing_bcns; 204 struct dentry *pwr_wake_on_host; 205 struct dentry *pwr_wake_on_timer_exp; 206 struct dentry *pwr_tx_with_ps; 207 struct dentry *pwr_tx_without_ps; 208 struct dentry *pwr_rcvd_beacons; 209 struct dentry *pwr_power_save_off; 210 struct dentry *pwr_enable_ps; 211 struct dentry *pwr_disable_ps; 212 struct dentry *pwr_fix_tsf_ps; 213 /* skipping cont_miss_bcns_spread for now */ 214 struct dentry *pwr_rcvd_awake_beacons; 215 216 struct dentry *mic_rx_pkts; 217 struct dentry *mic_calc_failure; 218 219 struct dentry *aes_encrypt_fail; 220 struct dentry *aes_decrypt_fail; 221 struct dentry *aes_encrypt_packets; 222 struct dentry *aes_decrypt_packets; 223 struct dentry *aes_encrypt_interrupt; 224 struct dentry *aes_decrypt_interrupt; 225 226 struct dentry *event_heart_beat; 227 struct dentry *event_calibration; 228 struct dentry *event_rx_mismatch; 229 struct dentry *event_rx_mem_empty; 230 struct dentry *event_rx_pool; 231 struct dentry *event_oom_late; 232 struct dentry *event_phy_transmit_error; 233 struct dentry *event_tx_stuck; 234 235 struct dentry *ps_pspoll_timeouts; 236 struct dentry *ps_upsd_timeouts; 237 struct dentry *ps_upsd_max_sptime; 238 struct dentry *ps_upsd_max_apturn; 239 struct dentry *ps_pspoll_max_apturn; 240 struct dentry *ps_pspoll_utilization; 241 struct dentry *ps_upsd_utilization; 242 243 struct dentry *rxpipe_rx_prep_beacon_drop; 244 struct dentry *rxpipe_descr_host_int_trig_rx_data; 245 struct dentry *rxpipe_beacon_buffer_thres_host_int_trig_rx_data; 246 struct dentry *rxpipe_missed_beacon_host_int_trig_rx_data; 247 struct dentry *rxpipe_tx_xfr_host_int_trig_rx_data; 248 249 struct dentry *tx_queue_len; 250 struct dentry *tx_queue_status; 251 252 struct dentry *retry_count; 253 struct dentry *excessive_retries; 254}; 255 256struct wl1251_if_operations { 257 void (*read)(struct wl1251 *wl, int addr, void *buf, size_t len); 258 void (*write)(struct wl1251 *wl, int addr, void *buf, size_t len); 259 void (*read_elp)(struct wl1251 *wl, int addr, u32 *val); 260 void (*write_elp)(struct wl1251 *wl, int addr, u32 val); 261 void (*reset)(struct wl1251 *wl); 262 void (*enable_irq)(struct wl1251 *wl); 263 void (*disable_irq)(struct wl1251 *wl); 264}; 265 266struct wl1251 { 267 struct ieee80211_hw *hw; 268 bool mac80211_registered; 269 270 void *if_priv; 271 const struct wl1251_if_operations *if_ops; 272 273 void (*set_power)(bool enable); 274 int irq; 275 bool use_eeprom; 276 277 enum wl1251_state state; 278 struct mutex mutex; 279 280 int physical_mem_addr; 281 int physical_reg_addr; 282 int virtual_mem_addr; 283 int virtual_reg_addr; 284 285 int cmd_box_addr; 286 int event_box_addr; 287 struct boot_attr boot_attr; 288 289 u8 *fw; 290 size_t fw_len; 291 u8 *nvs; 292 size_t nvs_len; 293 294 u8 bssid[ETH_ALEN]; 295 u8 mac_addr[ETH_ALEN]; 296 u8 bss_type; 297 u8 listen_int; 298 int channel; 299 300 void *target_mem_map; 301 struct acx_data_path_params_resp *data_path; 302 303 /* Number of TX packets transferred to the FW, modulo 16 */ 304 u32 data_in_count; 305 306 /* Frames scheduled for transmission, not handled yet */ 307 struct sk_buff_head tx_queue; 308 bool tx_queue_stopped; 309 310 struct work_struct tx_work; 311 struct work_struct filter_work; 312 313 /* Pending TX frames */ 314 struct sk_buff *tx_frames[16]; 315 316 /* 317 * Index pointing to the next TX complete entry 318 * in the cyclic XT complete array we get from 319 * the FW. 320 */ 321 u32 next_tx_complete; 322 323 /* FW Rx counter */ 324 u32 rx_counter; 325 326 /* Rx frames handled */ 327 u32 rx_handled; 328 329 /* Current double buffer */ 330 u32 rx_current_buffer; 331 u32 rx_last_id; 332 333 /* The target interrupt mask */ 334 u32 intr_mask; 335 struct work_struct irq_work; 336 337 /* The mbox event mask */ 338 u32 event_mask; 339 340 /* Mailbox pointers */ 341 u32 mbox_ptr[2]; 342 343 /* Are we currently scanning */ 344 bool scanning; 345 346 /* Default key (for WEP) */ 347 u32 default_key; 348 349 unsigned int tx_mgmt_frm_rate; 350 unsigned int tx_mgmt_frm_mod; 351 352 unsigned int rx_config; 353 unsigned int rx_filter; 354 355 /* is firmware in elp mode */ 356 bool elp; 357 358 struct delayed_work elp_work; 359 360 /* we can be in psm, but not in elp, we have to differentiate */ 361 bool psm; 362 363 /* PSM mode requested */ 364 bool psm_requested; 365 366 u16 beacon_int; 367 u8 dtim_period; 368 369 /* in dBm */ 370 int power_level; 371 372 struct wl1251_stats stats; 373 struct wl1251_debugfs debugfs; 374 375 u32 buffer_32; 376 u32 buffer_cmd; 377 u8 buffer_busyword[WL1251_BUSY_WORD_LEN]; 378 struct wl1251_rx_descriptor *rx_descriptor; 379 380 struct ieee80211_vif *vif; 381 382 u32 chip_id; 383 char fw_ver[21]; 384 385 /* Most recently reported noise in dBm */ 386 s8 noise; 387}; 388 389int wl1251_plt_start(struct wl1251 *wl); 390int wl1251_plt_stop(struct wl1251 *wl); 391 392struct ieee80211_hw *wl1251_alloc_hw(void); 393int wl1251_free_hw(struct wl1251 *wl); 394int wl1251_init_ieee80211(struct wl1251 *wl); 395void wl1251_enable_interrupts(struct wl1251 *wl); 396void wl1251_disable_interrupts(struct wl1251 *wl); 397 398#define DEFAULT_HW_GEN_MODULATION_TYPE CCK_LONG /* Long Preamble */ 399#define DEFAULT_HW_GEN_TX_RATE RATE_2MBPS 400#define JOIN_TIMEOUT 5000 /* 5000 milliseconds to join */ 401 402#define WL1251_DEFAULT_POWER_LEVEL 20 403 404#define WL1251_TX_QUEUE_MAX_LENGTH 20 405 406#define WL1251_DEFAULT_BEACON_INT 100 407#define WL1251_DEFAULT_DTIM_PERIOD 1 408 409#define WL1251_DEFAULT_CHANNEL 0 410 411#define CHIP_ID_1251_PG10 (0x7010101) 412#define CHIP_ID_1251_PG11 (0x7020101) 413#define CHIP_ID_1251_PG12 (0x7030101) 414#define CHIP_ID_1271_PG10 (0x4030101) 415#define CHIP_ID_1271_PG20 (0x4030111) 416 417#define WL1251_FW_NAME "wl1251-fw.bin" 418#define WL1251_NVS_NAME "wl1251-nvs.bin" 419 420#define WL1251_POWER_ON_SLEEP 10 /* in miliseconds */ 421 422#define WL1251_PART_DOWN_MEM_START 0x0 423#define WL1251_PART_DOWN_MEM_SIZE 0x16800 424#define WL1251_PART_DOWN_REG_START REGISTERS_BASE 425#define WL1251_PART_DOWN_REG_SIZE REGISTERS_DOWN_SIZE 426 427#define WL1251_PART_WORK_MEM_START 0x28000 428#define WL1251_PART_WORK_MEM_SIZE 0x14000 429#define WL1251_PART_WORK_REG_START REGISTERS_BASE 430#define WL1251_PART_WORK_REG_SIZE REGISTERS_WORK_SIZE 431 432#endif 433