1/* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/nl80211.h> 18#include "ath9k.h" 19#include "btcoex.h" 20 21static void ath_cache_conf_rate(struct ath_softc *sc, 22 struct ieee80211_conf *conf) 23{ 24 switch (conf->channel->band) { 25 case IEEE80211_BAND_2GHZ: 26 if (conf_is_ht20(conf)) 27 sc->cur_rate_mode = ATH9K_MODE_11NG_HT20; 28 else if (conf_is_ht40_minus(conf)) 29 sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS; 30 else if (conf_is_ht40_plus(conf)) 31 sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS; 32 else 33 sc->cur_rate_mode = ATH9K_MODE_11G; 34 break; 35 case IEEE80211_BAND_5GHZ: 36 if (conf_is_ht20(conf)) 37 sc->cur_rate_mode = ATH9K_MODE_11NA_HT20; 38 else if (conf_is_ht40_minus(conf)) 39 sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS; 40 else if (conf_is_ht40_plus(conf)) 41 sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS; 42 else 43 sc->cur_rate_mode = ATH9K_MODE_11A; 44 break; 45 default: 46 BUG_ON(1); 47 break; 48 } 49} 50 51static void ath_update_txpow(struct ath_softc *sc) 52{ 53 struct ath_hw *ah = sc->sc_ah; 54 55 if (sc->curtxpow != sc->config.txpowlimit) { 56 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit); 57 /* read back in case value is clamped */ 58 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; 59 } 60} 61 62static u8 parse_mpdudensity(u8 mpdudensity) 63{ 64 /* 65 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": 66 * 0 for no restriction 67 * 1 for 1/4 us 68 * 2 for 1/2 us 69 * 3 for 1 us 70 * 4 for 2 us 71 * 5 for 4 us 72 * 6 for 8 us 73 * 7 for 16 us 74 */ 75 switch (mpdudensity) { 76 case 0: 77 return 0; 78 case 1: 79 case 2: 80 case 3: 81 /* Our lower layer calculations limit our precision to 82 1 microsecond */ 83 return 1; 84 case 4: 85 return 2; 86 case 5: 87 return 4; 88 case 6: 89 return 8; 90 case 7: 91 return 16; 92 default: 93 return 0; 94 } 95} 96 97static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc, 98 struct ieee80211_hw *hw) 99{ 100 struct ieee80211_channel *curchan = hw->conf.channel; 101 struct ath9k_channel *channel; 102 u8 chan_idx; 103 104 chan_idx = curchan->hw_value; 105 channel = &sc->sc_ah->channels[chan_idx]; 106 ath9k_update_ichannel(sc, hw, channel); 107 return channel; 108} 109 110bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) 111{ 112 unsigned long flags; 113 bool ret; 114 115 spin_lock_irqsave(&sc->sc_pm_lock, flags); 116 ret = ath9k_hw_setpower(sc->sc_ah, mode); 117 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 118 119 return ret; 120} 121 122void ath9k_ps_wakeup(struct ath_softc *sc) 123{ 124 unsigned long flags; 125 126 spin_lock_irqsave(&sc->sc_pm_lock, flags); 127 if (++sc->ps_usecount != 1) 128 goto unlock; 129 130 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 131 132 unlock: 133 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 134} 135 136void ath9k_ps_restore(struct ath_softc *sc) 137{ 138 unsigned long flags; 139 140 spin_lock_irqsave(&sc->sc_pm_lock, flags); 141 if (--sc->ps_usecount != 0) 142 goto unlock; 143 144 if (sc->ps_idle) 145 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); 146 else if (sc->ps_enabled && 147 !(sc->ps_flags & (PS_WAIT_FOR_BEACON | 148 PS_WAIT_FOR_CAB | 149 PS_WAIT_FOR_PSPOLL_DATA | 150 PS_WAIT_FOR_TX_ACK))) 151 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); 152 153 unlock: 154 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 155} 156 157static void ath_start_ani(struct ath_common *common) 158{ 159 struct ath_hw *ah = common->ah; 160 unsigned long timestamp = jiffies_to_msecs(jiffies); 161 struct ath_softc *sc = (struct ath_softc *) common->priv; 162 163 if (!(sc->sc_flags & SC_OP_ANI_RUN)) 164 return; 165 166 if (sc->sc_flags & SC_OP_OFFCHANNEL) 167 return; 168 169 common->ani.longcal_timer = timestamp; 170 common->ani.shortcal_timer = timestamp; 171 common->ani.checkani_timer = timestamp; 172 173 mod_timer(&common->ani.timer, 174 jiffies + 175 msecs_to_jiffies((u32)ah->config.ani_poll_interval)); 176} 177 178/* 179 * Set/change channels. If the channel is really being changed, it's done 180 * by reseting the chip. To accomplish this we must first cleanup any pending 181 * DMA, then restart stuff. 182*/ 183int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, 184 struct ath9k_channel *hchan) 185{ 186 struct ath_wiphy *aphy = hw->priv; 187 struct ath_hw *ah = sc->sc_ah; 188 struct ath_common *common = ath9k_hw_common(ah); 189 struct ieee80211_conf *conf = &common->hw->conf; 190 bool fastcc = true, stopped; 191 struct ieee80211_channel *channel = hw->conf.channel; 192 struct ath9k_hw_cal_data *caldata = NULL; 193 int r; 194 195 if (sc->sc_flags & SC_OP_INVALID) 196 return -EIO; 197 198 del_timer_sync(&common->ani.timer); 199 cancel_work_sync(&sc->paprd_work); 200 cancel_work_sync(&sc->hw_check_work); 201 cancel_delayed_work_sync(&sc->tx_complete_work); 202 203 ath9k_ps_wakeup(sc); 204 205 /* 206 * This is only performed if the channel settings have 207 * actually changed. 208 * 209 * To switch channels clear any pending DMA operations; 210 * wait long enough for the RX fifo to drain, reset the 211 * hardware at the new frequency, and then re-enable 212 * the relevant bits of the h/w. 213 */ 214 ath9k_hw_set_interrupts(ah, 0); 215 ath_drain_all_txq(sc, false); 216 217 spin_lock_bh(&sc->sc_pcu_lock); 218 219 stopped = ath_stoprecv(sc); 220 221 222 if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL)) 223 fastcc = false; 224 225 if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) 226 caldata = &aphy->caldata; 227 228 ath_print(common, ATH_DBG_CONFIG, 229 "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n", 230 sc->sc_ah->curchan->channel, 231 channel->center_freq, conf_is_ht40(conf)); 232 233 r = ath9k_hw_reset(ah, hchan, caldata, fastcc); 234 if (r) { 235 ath_print(common, ATH_DBG_FATAL, 236 "Unable to reset channel (%u MHz), " 237 "reset status %d\n", 238 channel->center_freq, r); 239 spin_unlock_bh(&sc->sc_pcu_lock); 240 goto ps_restore; 241 } 242 243 if (ath_startrecv(sc) != 0) { 244 ath_print(common, ATH_DBG_FATAL, 245 "Unable to restart recv logic\n"); 246 r = -EIO; 247 spin_unlock_bh(&sc->sc_pcu_lock); 248 goto ps_restore; 249 } 250 251 spin_unlock_bh(&sc->sc_pcu_lock); 252 253 ath_cache_conf_rate(sc, &hw->conf); 254 ath_update_txpow(sc); 255 ath9k_hw_set_interrupts(ah, ah->imask); 256 257 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) { 258 if (sc->sc_flags & SC_OP_BEACONS) 259 ath_beacon_config(sc, NULL); 260 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 261 ath_start_ani(common); 262 } 263 264 ps_restore: 265 ath9k_ps_restore(sc); 266 return r; 267} 268 269static void ath_paprd_activate(struct ath_softc *sc) 270{ 271 struct ath_hw *ah = sc->sc_ah; 272 struct ath9k_hw_cal_data *caldata = ah->caldata; 273 struct ath_common *common = ath9k_hw_common(ah); 274 int chain; 275 276 if (!caldata || !caldata->paprd_done) 277 return; 278 279 ath9k_ps_wakeup(sc); 280 ar9003_paprd_enable(ah, false); 281 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { 282 if (!(common->tx_chainmask & BIT(chain))) 283 continue; 284 285 ar9003_paprd_populate_single_table(ah, caldata, chain); 286 } 287 288 ar9003_paprd_enable(ah, true); 289 ath9k_ps_restore(sc); 290} 291 292void ath_paprd_calibrate(struct work_struct *work) 293{ 294 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work); 295 struct ieee80211_hw *hw = sc->hw; 296 struct ath_hw *ah = sc->sc_ah; 297 struct ieee80211_hdr *hdr; 298 struct sk_buff *skb = NULL; 299 struct ieee80211_tx_info *tx_info; 300 int band = hw->conf.channel->band; 301 struct ieee80211_supported_band *sband = &sc->sbands[band]; 302 struct ath_tx_control txctl; 303 struct ath9k_hw_cal_data *caldata = ah->caldata; 304 struct ath_common *common = ath9k_hw_common(ah); 305 int qnum, ftype; 306 int chain_ok = 0; 307 int chain; 308 int len = 1800; 309 int time_left; 310 int i; 311 312 if (!caldata) 313 return; 314 315 skb = alloc_skb(len, GFP_KERNEL); 316 if (!skb) 317 return; 318 319 tx_info = IEEE80211_SKB_CB(skb); 320 321 skb_put(skb, len); 322 memset(skb->data, 0, len); 323 hdr = (struct ieee80211_hdr *)skb->data; 324 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC; 325 hdr->frame_control = cpu_to_le16(ftype); 326 hdr->duration_id = cpu_to_le16(10); 327 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN); 328 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN); 329 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN); 330 331 memset(&txctl, 0, sizeof(txctl)); 332 qnum = sc->tx.hwq_map[WME_AC_BE]; 333 txctl.txq = &sc->tx.txq[qnum]; 334 335 ath9k_ps_wakeup(sc); 336 ar9003_paprd_init_table(ah); 337 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { 338 if (!(common->tx_chainmask & BIT(chain))) 339 continue; 340 341 chain_ok = 0; 342 memset(tx_info, 0, sizeof(*tx_info)); 343 tx_info->band = band; 344 345 for (i = 0; i < 4; i++) { 346 tx_info->control.rates[i].idx = sband->n_bitrates - 1; 347 tx_info->control.rates[i].count = 6; 348 } 349 350 init_completion(&sc->paprd_complete); 351 ar9003_paprd_setup_gain_table(ah, chain); 352 txctl.paprd = BIT(chain); 353 if (ath_tx_start(hw, skb, &txctl) != 0) 354 break; 355 356 time_left = wait_for_completion_timeout(&sc->paprd_complete, 357 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); 358 if (!time_left) { 359 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, 360 "Timeout waiting for paprd training on " 361 "TX chain %d\n", 362 chain); 363 goto fail_paprd; 364 } 365 366 if (!ar9003_paprd_is_done(ah)) 367 break; 368 369 if (ar9003_paprd_create_curve(ah, caldata, chain) != 0) 370 break; 371 372 chain_ok = 1; 373 } 374 kfree_skb(skb); 375 376 if (chain_ok) { 377 caldata->paprd_done = true; 378 ath_paprd_activate(sc); 379 } 380 381fail_paprd: 382 ath9k_ps_restore(sc); 383} 384 385/* 386 * This routine performs the periodic noise floor calibration function 387 * that is used to adjust and optimize the chip performance. This 388 * takes environmental changes (location, temperature) into account. 389 * When the task is complete, it reschedules itself depending on the 390 * appropriate interval that was calculated. 391 */ 392void ath_ani_calibrate(unsigned long data) 393{ 394 struct ath_softc *sc = (struct ath_softc *)data; 395 struct ath_hw *ah = sc->sc_ah; 396 struct ath_common *common = ath9k_hw_common(ah); 397 bool longcal = false; 398 bool shortcal = false; 399 bool aniflag = false; 400 unsigned int timestamp = jiffies_to_msecs(jiffies); 401 u32 cal_interval, short_cal_interval; 402 403 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? 404 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; 405 406 /* Only calibrate if awake */ 407 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) 408 goto set_timer; 409 410 ath9k_ps_wakeup(sc); 411 412 /* Long calibration runs independently of short calibration. */ 413 if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) { 414 longcal = true; 415 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); 416 common->ani.longcal_timer = timestamp; 417 } 418 419 /* Short calibration applies only while caldone is false */ 420 if (!common->ani.caldone) { 421 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { 422 shortcal = true; 423 ath_print(common, ATH_DBG_ANI, 424 "shortcal @%lu\n", jiffies); 425 common->ani.shortcal_timer = timestamp; 426 common->ani.resetcal_timer = timestamp; 427 } 428 } else { 429 if ((timestamp - common->ani.resetcal_timer) >= 430 ATH_RESTART_CALINTERVAL) { 431 common->ani.caldone = ath9k_hw_reset_calvalid(ah); 432 if (common->ani.caldone) 433 common->ani.resetcal_timer = timestamp; 434 } 435 } 436 437 /* Verify whether we must check ANI */ 438 if ((timestamp - common->ani.checkani_timer) >= 439 ah->config.ani_poll_interval) { 440 aniflag = true; 441 common->ani.checkani_timer = timestamp; 442 } 443 444 /* Skip all processing if there's nothing to do. */ 445 if (longcal || shortcal || aniflag) { 446 /* Call ANI routine if necessary */ 447 if (aniflag) 448 ath9k_hw_ani_monitor(ah, ah->curchan); 449 450 /* Perform calibration if necessary */ 451 if (longcal || shortcal) { 452 common->ani.caldone = 453 ath9k_hw_calibrate(ah, 454 ah->curchan, 455 common->rx_chainmask, 456 longcal); 457 458 if (longcal) 459 common->ani.noise_floor = ath9k_hw_getchan_noise(ah, 460 ah->curchan); 461 462 ath_print(common, ATH_DBG_ANI, 463 " calibrate chan %u/%x nf: %d\n", 464 ah->curchan->channel, 465 ah->curchan->channelFlags, 466 common->ani.noise_floor); 467 } 468 } 469 470 ath9k_ps_restore(sc); 471 472set_timer: 473 /* 474 * Set timer interval based on previous results. 475 * The interval must be the shortest necessary to satisfy ANI, 476 * short calibration and long calibration. 477 */ 478 cal_interval = ATH_LONG_CALINTERVAL; 479 if (sc->sc_ah->config.enable_ani) 480 cal_interval = min(cal_interval, 481 (u32)ah->config.ani_poll_interval); 482 if (!common->ani.caldone) 483 cal_interval = min(cal_interval, (u32)short_cal_interval); 484 485 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); 486 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) { 487 if (!ah->caldata->paprd_done) 488 ieee80211_queue_work(sc->hw, &sc->paprd_work); 489 else 490 ath_paprd_activate(sc); 491 } 492} 493 494/* 495 * Update tx/rx chainmask. For legacy association, 496 * hard code chainmask to 1x1, for 11n association, use 497 * the chainmask configuration, for bt coexistence, use 498 * the chainmask configuration even in legacy mode. 499 */ 500void ath_update_chainmask(struct ath_softc *sc, int is_ht) 501{ 502 struct ath_hw *ah = sc->sc_ah; 503 struct ath_common *common = ath9k_hw_common(ah); 504 505 if ((sc->sc_flags & SC_OP_OFFCHANNEL) || is_ht || 506 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) { 507 common->tx_chainmask = ah->caps.tx_chainmask; 508 common->rx_chainmask = ah->caps.rx_chainmask; 509 } else { 510 common->tx_chainmask = 1; 511 common->rx_chainmask = 1; 512 } 513 514 ath_print(common, ATH_DBG_CONFIG, 515 "tx chmask: %d, rx chmask: %d\n", 516 common->tx_chainmask, 517 common->rx_chainmask); 518} 519 520static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) 521{ 522 struct ath_node *an; 523 524 an = (struct ath_node *)sta->drv_priv; 525 526 if (sc->sc_flags & SC_OP_TXAGGR) { 527 ath_tx_node_init(sc, an); 528 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + 529 sta->ht_cap.ampdu_factor); 530 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); 531 an->last_rssi = ATH_RSSI_DUMMY_MARKER; 532 } 533} 534 535static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) 536{ 537 struct ath_node *an = (struct ath_node *)sta->drv_priv; 538 539 if (sc->sc_flags & SC_OP_TXAGGR) 540 ath_tx_node_cleanup(sc, an); 541} 542 543void ath_hw_check(struct work_struct *work) 544{ 545 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work); 546 int i; 547 548 ath9k_ps_wakeup(sc); 549 550 for (i = 0; i < 3; i++) { 551 if (ath9k_hw_check_alive(sc->sc_ah)) 552 goto out; 553 554 msleep(1); 555 } 556 ath_reset(sc, true); 557 558out: 559 ath9k_ps_restore(sc); 560} 561 562void ath9k_tasklet(unsigned long data) 563{ 564 struct ath_softc *sc = (struct ath_softc *)data; 565 struct ath_hw *ah = sc->sc_ah; 566 struct ath_common *common = ath9k_hw_common(ah); 567 568 u32 status = sc->intrstatus; 569 u32 rxmask; 570 571 ath9k_ps_wakeup(sc); 572 573 if (status & ATH9K_INT_FATAL) { 574 ath_reset(sc, true); 575 ath9k_ps_restore(sc); 576 return; 577 } 578 579 if (!ath9k_hw_check_alive(ah)) 580 ieee80211_queue_work(sc->hw, &sc->hw_check_work); 581 582 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 583 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | 584 ATH9K_INT_RXORN); 585 else 586 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 587 588 if (status & rxmask) { 589 spin_lock_bh(&sc->sc_pcu_lock); 590 591 /* Check for high priority Rx first */ 592 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 593 (status & ATH9K_INT_RXHP)) 594 ath_rx_tasklet(sc, 0, true); 595 596 ath_rx_tasklet(sc, 0, false); 597 spin_unlock_bh(&sc->sc_pcu_lock); 598 } 599 600 if (status & ATH9K_INT_TX) { 601 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 602 ath_tx_edma_tasklet(sc); 603 else 604 ath_tx_tasklet(sc); 605 } 606 607 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { 608 /* 609 * TSF sync does not look correct; remain awake to sync with 610 * the next Beacon. 611 */ 612 ath_print(common, ATH_DBG_PS, 613 "TSFOOR - Sync with next Beacon\n"); 614 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; 615 } 616 617 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) 618 if (status & ATH9K_INT_GENTIMER) 619 ath_gen_timer_isr(sc->sc_ah); 620 621 /* re-enable hardware interrupt */ 622 ath9k_hw_set_interrupts(ah, ah->imask); 623 ath9k_ps_restore(sc); 624} 625 626irqreturn_t ath_isr(int irq, void *dev) 627{ 628#define SCHED_INTR ( \ 629 ATH9K_INT_FATAL | \ 630 ATH9K_INT_RXORN | \ 631 ATH9K_INT_RXEOL | \ 632 ATH9K_INT_RX | \ 633 ATH9K_INT_RXLP | \ 634 ATH9K_INT_RXHP | \ 635 ATH9K_INT_TX | \ 636 ATH9K_INT_BMISS | \ 637 ATH9K_INT_CST | \ 638 ATH9K_INT_TSFOOR | \ 639 ATH9K_INT_GENTIMER) 640 641 struct ath_softc *sc = dev; 642 struct ath_hw *ah = sc->sc_ah; 643 enum ath9k_int status; 644 bool sched = false; 645 646 /* 647 * The hardware is not ready/present, don't 648 * touch anything. Note this can happen early 649 * on if the IRQ is shared. 650 */ 651 if (sc->sc_flags & SC_OP_INVALID) 652 return IRQ_NONE; 653 654 655 /* shared irq, not for us */ 656 657 if (!ath9k_hw_intrpend(ah)) 658 return IRQ_NONE; 659 660 /* 661 * Figure out the reason(s) for the interrupt. Note 662 * that the hal returns a pseudo-ISR that may include 663 * bits we haven't explicitly enabled so we mask the 664 * value to insure we only process bits we requested. 665 */ 666 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ 667 status &= ah->imask; /* discard unasked-for bits */ 668 669 /* 670 * If there are no status bits set, then this interrupt was not 671 * for me (should have been caught above). 672 */ 673 if (!status) 674 return IRQ_NONE; 675 676 /* Cache the status */ 677 sc->intrstatus = status; 678 679 if (status & SCHED_INTR) 680 sched = true; 681 682 /* 683 * If a FATAL or RXORN interrupt is received, we have to reset the 684 * chip immediately. 685 */ 686 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && 687 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) 688 goto chip_reset; 689 690 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 691 (status & ATH9K_INT_BB_WATCHDOG)) { 692 ar9003_hw_bb_watchdog_dbg_info(ah); 693 goto chip_reset; 694 } 695 696 if (status & ATH9K_INT_SWBA) 697 tasklet_schedule(&sc->bcon_tasklet); 698 699 if (status & ATH9K_INT_TXURN) 700 ath9k_hw_updatetxtriglevel(ah, true); 701 702 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 703 if (status & ATH9K_INT_RXEOL) { 704 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 705 ath9k_hw_set_interrupts(ah, ah->imask); 706 } 707 } 708 709 if (status & ATH9K_INT_MIB) { 710 /* 711 * Disable interrupts until we service the MIB 712 * interrupt; otherwise it will continue to 713 * fire. 714 */ 715 ath9k_hw_set_interrupts(ah, 0); 716 /* 717 * Let the hal handle the event. We assume 718 * it will clear whatever condition caused 719 * the interrupt. 720 */ 721 ath9k_hw_procmibevent(ah); 722 ath9k_hw_set_interrupts(ah, ah->imask); 723 } 724 725 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 726 if (status & ATH9K_INT_TIM_TIMER) { 727 /* Clear RxAbort bit so that we can 728 * receive frames */ 729 ath9k_setpower(sc, ATH9K_PM_AWAKE); 730 ath9k_hw_setrxabort(sc->sc_ah, 0); 731 sc->ps_flags |= PS_WAIT_FOR_BEACON; 732 } 733 734chip_reset: 735 736 ath_debug_stat_interrupt(sc, status); 737 738 if (sched) { 739 /* turn off every interrupt except SWBA */ 740 ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA)); 741 tasklet_schedule(&sc->intr_tq); 742 } 743 744 return IRQ_HANDLED; 745 746#undef SCHED_INTR 747} 748 749static u32 ath_get_extchanmode(struct ath_softc *sc, 750 struct ieee80211_channel *chan, 751 enum nl80211_channel_type channel_type) 752{ 753 u32 chanmode = 0; 754 755 switch (chan->band) { 756 case IEEE80211_BAND_2GHZ: 757 switch(channel_type) { 758 case NL80211_CHAN_NO_HT: 759 case NL80211_CHAN_HT20: 760 chanmode = CHANNEL_G_HT20; 761 break; 762 case NL80211_CHAN_HT40PLUS: 763 chanmode = CHANNEL_G_HT40PLUS; 764 break; 765 case NL80211_CHAN_HT40MINUS: 766 chanmode = CHANNEL_G_HT40MINUS; 767 break; 768 } 769 break; 770 case IEEE80211_BAND_5GHZ: 771 switch(channel_type) { 772 case NL80211_CHAN_NO_HT: 773 case NL80211_CHAN_HT20: 774 chanmode = CHANNEL_A_HT20; 775 break; 776 case NL80211_CHAN_HT40PLUS: 777 chanmode = CHANNEL_A_HT40PLUS; 778 break; 779 case NL80211_CHAN_HT40MINUS: 780 chanmode = CHANNEL_A_HT40MINUS; 781 break; 782 } 783 break; 784 default: 785 break; 786 } 787 788 return chanmode; 789} 790 791static void ath9k_bss_assoc_info(struct ath_softc *sc, 792 struct ieee80211_vif *vif, 793 struct ieee80211_bss_conf *bss_conf) 794{ 795 struct ath_hw *ah = sc->sc_ah; 796 struct ath_common *common = ath9k_hw_common(ah); 797 798 if (bss_conf->assoc) { 799 ath_print(common, ATH_DBG_CONFIG, 800 "Bss Info ASSOC %d, bssid: %pM\n", 801 bss_conf->aid, common->curbssid); 802 803 /* New association, store aid */ 804 common->curaid = bss_conf->aid; 805 ath9k_hw_write_associd(ah); 806 807 /* 808 * Request a re-configuration of Beacon related timers 809 * on the receipt of the first Beacon frame (i.e., 810 * after time sync with the AP). 811 */ 812 sc->ps_flags |= PS_BEACON_SYNC; 813 814 /* Configure the beacon */ 815 ath_beacon_config(sc, vif); 816 817 /* Reset rssi stats */ 818 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 819 820 sc->sc_flags |= SC_OP_ANI_RUN; 821 ath_start_ani(common); 822 } else { 823 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); 824 common->curaid = 0; 825 /* Stop ANI */ 826 sc->sc_flags &= ~SC_OP_ANI_RUN; 827 del_timer_sync(&common->ani.timer); 828 } 829} 830 831void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw) 832{ 833 struct ath_hw *ah = sc->sc_ah; 834 struct ath_common *common = ath9k_hw_common(ah); 835 struct ieee80211_channel *channel = hw->conf.channel; 836 int r; 837 838 ath9k_ps_wakeup(sc); 839 ath9k_hw_configpcipowersave(ah, 0, 0); 840 841 if (!ah->curchan) 842 ah->curchan = ath_get_curchannel(sc, sc->hw); 843 844 spin_lock_bh(&sc->sc_pcu_lock); 845 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 846 if (r) { 847 ath_print(common, ATH_DBG_FATAL, 848 "Unable to reset channel (%u MHz), " 849 "reset status %d\n", 850 channel->center_freq, r); 851 } 852 853 ath_update_txpow(sc); 854 if (ath_startrecv(sc) != 0) { 855 ath_print(common, ATH_DBG_FATAL, 856 "Unable to restart recv logic\n"); 857 spin_unlock_bh(&sc->sc_pcu_lock); 858 return; 859 } 860 spin_unlock_bh(&sc->sc_pcu_lock); 861 862 if (sc->sc_flags & SC_OP_BEACONS) 863 ath_beacon_config(sc, NULL); /* restart beacons */ 864 865 /* Re-Enable interrupts */ 866 ath9k_hw_set_interrupts(ah, ah->imask); 867 868 /* Enable LED */ 869 ath9k_hw_cfg_output(ah, ah->led_pin, 870 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 871 ath9k_hw_set_gpio(ah, ah->led_pin, 0); 872 873 ieee80211_wake_queues(hw); 874 ath9k_ps_restore(sc); 875} 876 877void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw) 878{ 879 struct ath_hw *ah = sc->sc_ah; 880 struct ieee80211_channel *channel = hw->conf.channel; 881 int r; 882 883 ath9k_ps_wakeup(sc); 884 ieee80211_stop_queues(hw); 885 886 /* 887 * Keep the LED on when the radio is disabled 888 * during idle unassociated state. 889 */ 890 if (!sc->ps_idle) { 891 ath9k_hw_set_gpio(ah, ah->led_pin, 1); 892 ath9k_hw_cfg_gpio_input(ah, ah->led_pin); 893 } 894 895 /* Disable interrupts */ 896 ath9k_hw_set_interrupts(ah, 0); 897 898 ath_drain_all_txq(sc, false); /* clear pending tx frames */ 899 900 spin_lock_bh(&sc->sc_pcu_lock); 901 902 ath_stoprecv(sc); /* turn off frame recv */ 903 ath_flushrecv(sc); /* flush recv queue */ 904 905 if (!ah->curchan) 906 ah->curchan = ath_get_curchannel(sc, hw); 907 908 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 909 if (r) { 910 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, 911 "Unable to reset channel (%u MHz), " 912 "reset status %d\n", 913 channel->center_freq, r); 914 } 915 916 ath9k_hw_phy_disable(ah); 917 918 spin_unlock_bh(&sc->sc_pcu_lock); 919 920 ath9k_hw_configpcipowersave(ah, 1, 1); 921 ath9k_ps_restore(sc); 922 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); 923} 924 925int ath_reset(struct ath_softc *sc, bool retry_tx) 926{ 927 struct ath_hw *ah = sc->sc_ah; 928 struct ath_common *common = ath9k_hw_common(ah); 929 struct ieee80211_hw *hw = sc->hw; 930 int r; 931 932 /* Stop ANI */ 933 del_timer_sync(&common->ani.timer); 934 935 ieee80211_stop_queues(hw); 936 937 ath9k_hw_set_interrupts(ah, 0); 938 ath_drain_all_txq(sc, retry_tx); 939 940 spin_lock_bh(&sc->sc_pcu_lock); 941 942 ath_stoprecv(sc); 943 ath_flushrecv(sc); 944 945 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false); 946 if (r) 947 ath_print(common, ATH_DBG_FATAL, 948 "Unable to reset hardware; reset status %d\n", r); 949 950 if (ath_startrecv(sc) != 0) 951 ath_print(common, ATH_DBG_FATAL, 952 "Unable to start recv logic\n"); 953 954 spin_unlock_bh(&sc->sc_pcu_lock); 955 956 /* 957 * We may be doing a reset in response to a request 958 * that changes the channel so update any state that 959 * might change as a result. 960 */ 961 ath_cache_conf_rate(sc, &hw->conf); 962 963 ath_update_txpow(sc); 964 965 if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL))) 966 ath_beacon_config(sc, NULL); /* restart beacons */ 967 968 ath9k_hw_set_interrupts(ah, ah->imask); 969 970 if (retry_tx) { 971 int i; 972 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 973 if (ATH_TXQ_SETUP(sc, i)) { 974 spin_lock_bh(&sc->tx.txq[i].axq_lock); 975 ath_txq_schedule(sc, &sc->tx.txq[i]); 976 spin_unlock_bh(&sc->tx.txq[i].axq_lock); 977 } 978 } 979 } 980 981 ieee80211_wake_queues(hw); 982 983 /* Start ANI */ 984 ath_start_ani(common); 985 986 return r; 987} 988 989static int ath_get_hal_qnum(u16 queue, struct ath_softc *sc) 990{ 991 int qnum; 992 993 switch (queue) { 994 case 0: 995 qnum = sc->tx.hwq_map[WME_AC_VO]; 996 break; 997 case 1: 998 qnum = sc->tx.hwq_map[WME_AC_VI]; 999 break; 1000 case 2: 1001 qnum = sc->tx.hwq_map[WME_AC_BE]; 1002 break; 1003 case 3: 1004 qnum = sc->tx.hwq_map[WME_AC_BK]; 1005 break; 1006 default: 1007 qnum = sc->tx.hwq_map[WME_AC_BE]; 1008 break; 1009 } 1010 1011 return qnum; 1012} 1013 1014int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc) 1015{ 1016 int qnum; 1017 1018 switch (queue) { 1019 case WME_AC_VO: 1020 qnum = 0; 1021 break; 1022 case WME_AC_VI: 1023 qnum = 1; 1024 break; 1025 case WME_AC_BE: 1026 qnum = 2; 1027 break; 1028 case WME_AC_BK: 1029 qnum = 3; 1030 break; 1031 default: 1032 qnum = -1; 1033 break; 1034 } 1035 1036 return qnum; 1037} 1038 1039void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, 1040 struct ath9k_channel *ichan) 1041{ 1042 struct ieee80211_channel *chan = hw->conf.channel; 1043 struct ieee80211_conf *conf = &hw->conf; 1044 1045 ichan->channel = chan->center_freq; 1046 ichan->chan = chan; 1047 1048 if (chan->band == IEEE80211_BAND_2GHZ) { 1049 ichan->chanmode = CHANNEL_G; 1050 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G; 1051 } else { 1052 ichan->chanmode = CHANNEL_A; 1053 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM; 1054 } 1055 1056 if (conf_is_ht(conf)) 1057 ichan->chanmode = ath_get_extchanmode(sc, chan, 1058 conf->channel_type); 1059} 1060 1061/**********************/ 1062/* mac80211 callbacks */ 1063/**********************/ 1064 1065static int ath9k_start(struct ieee80211_hw *hw) 1066{ 1067 struct ath_wiphy *aphy = hw->priv; 1068 struct ath_softc *sc = aphy->sc; 1069 struct ath_hw *ah = sc->sc_ah; 1070 struct ath_common *common = ath9k_hw_common(ah); 1071 struct ieee80211_channel *curchan = hw->conf.channel; 1072 struct ath9k_channel *init_channel; 1073 int r; 1074 1075 ath_print(common, ATH_DBG_CONFIG, 1076 "Starting driver with initial channel: %d MHz\n", 1077 curchan->center_freq); 1078 1079 mutex_lock(&sc->mutex); 1080 1081 if (ath9k_wiphy_started(sc)) { 1082 if (sc->chan_idx == curchan->hw_value) { 1083 /* 1084 * Already on the operational channel, the new wiphy 1085 * can be marked active. 1086 */ 1087 aphy->state = ATH_WIPHY_ACTIVE; 1088 ieee80211_wake_queues(hw); 1089 } else { 1090 /* 1091 * Another wiphy is on another channel, start the new 1092 * wiphy in paused state. 1093 */ 1094 aphy->state = ATH_WIPHY_PAUSED; 1095 ieee80211_stop_queues(hw); 1096 } 1097 mutex_unlock(&sc->mutex); 1098 return 0; 1099 } 1100 aphy->state = ATH_WIPHY_ACTIVE; 1101 1102 /* setup initial channel */ 1103 1104 sc->chan_idx = curchan->hw_value; 1105 1106 init_channel = ath_get_curchannel(sc, hw); 1107 1108 /* Reset SERDES registers */ 1109 ath9k_hw_configpcipowersave(ah, 0, 0); 1110 1111 /* 1112 * The basic interface to setting the hardware in a good 1113 * state is ``reset''. On return the hardware is known to 1114 * be powered up and with interrupts disabled. This must 1115 * be followed by initialization of the appropriate bits 1116 * and then setup of the interrupt mask. 1117 */ 1118 spin_lock_bh(&sc->sc_pcu_lock); 1119 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); 1120 if (r) { 1121 ath_print(common, ATH_DBG_FATAL, 1122 "Unable to reset hardware; reset status %d " 1123 "(freq %u MHz)\n", r, 1124 curchan->center_freq); 1125 spin_unlock_bh(&sc->sc_pcu_lock); 1126 goto mutex_unlock; 1127 } 1128 1129 /* 1130 * This is needed only to setup initial state 1131 * but it's best done after a reset. 1132 */ 1133 ath_update_txpow(sc); 1134 1135 /* 1136 * Setup the hardware after reset: 1137 * The receive engine is set going. 1138 * Frame transmit is handled entirely 1139 * in the frame output path; there's nothing to do 1140 * here except setup the interrupt mask. 1141 */ 1142 if (ath_startrecv(sc) != 0) { 1143 ath_print(common, ATH_DBG_FATAL, 1144 "Unable to start recv logic\n"); 1145 r = -EIO; 1146 spin_unlock_bh(&sc->sc_pcu_lock); 1147 goto mutex_unlock; 1148 } 1149 spin_unlock_bh(&sc->sc_pcu_lock); 1150 1151 /* Setup our intr mask. */ 1152 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | 1153 ATH9K_INT_RXORN | ATH9K_INT_FATAL | 1154 ATH9K_INT_GLOBAL; 1155 1156 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 1157 ah->imask |= ATH9K_INT_RXHP | 1158 ATH9K_INT_RXLP | 1159 ATH9K_INT_BB_WATCHDOG; 1160 else 1161 ah->imask |= ATH9K_INT_RX; 1162 1163 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT) 1164 ah->imask |= ATH9K_INT_GTT; 1165 1166 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) 1167 ah->imask |= ATH9K_INT_CST; 1168 1169 ath_cache_conf_rate(sc, &hw->conf); 1170 1171 sc->sc_flags &= ~SC_OP_INVALID; 1172 1173 /* Disable BMISS interrupt when we're not associated */ 1174 ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); 1175 ath9k_hw_set_interrupts(ah, ah->imask); 1176 1177 ieee80211_wake_queues(hw); 1178 1179 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 1180 1181 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && 1182 !ah->btcoex_hw.enabled) { 1183 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, 1184 AR_STOMP_LOW_WLAN_WGHT); 1185 ath9k_hw_btcoex_enable(ah); 1186 1187 if (common->bus_ops->bt_coex_prep) 1188 common->bus_ops->bt_coex_prep(common); 1189 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) 1190 ath9k_btcoex_timer_resume(sc); 1191 } 1192 1193mutex_unlock: 1194 mutex_unlock(&sc->mutex); 1195 1196 return r; 1197} 1198 1199static int ath9k_tx(struct ieee80211_hw *hw, 1200 struct sk_buff *skb) 1201{ 1202 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1203 struct ath_wiphy *aphy = hw->priv; 1204 struct ath_softc *sc = aphy->sc; 1205 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1206 struct ath_tx_control txctl; 1207 int padpos, padsize; 1208 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 1209 int qnum; 1210 1211 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { 1212 ath_print(common, ATH_DBG_XMIT, 1213 "ath9k: %s: TX in unexpected wiphy state " 1214 "%d\n", wiphy_name(hw->wiphy), aphy->state); 1215 goto exit; 1216 } 1217 1218 if (sc->ps_enabled) { 1219 /* 1220 * mac80211 does not set PM field for normal data frames, so we 1221 * need to update that based on the current PS mode. 1222 */ 1223 if (ieee80211_is_data(hdr->frame_control) && 1224 !ieee80211_is_nullfunc(hdr->frame_control) && 1225 !ieee80211_has_pm(hdr->frame_control)) { 1226 ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame " 1227 "while in PS mode\n"); 1228 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 1229 } 1230 } 1231 1232 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { 1233 /* 1234 * We are using PS-Poll and mac80211 can request TX while in 1235 * power save mode. Need to wake up hardware for the TX to be 1236 * completed and if needed, also for RX of buffered frames. 1237 */ 1238 ath9k_ps_wakeup(sc); 1239 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 1240 ath9k_hw_setrxabort(sc->sc_ah, 0); 1241 if (ieee80211_is_pspoll(hdr->frame_control)) { 1242 ath_print(common, ATH_DBG_PS, 1243 "Sending PS-Poll to pick a buffered frame\n"); 1244 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; 1245 } else { 1246 ath_print(common, ATH_DBG_PS, 1247 "Wake up to complete TX\n"); 1248 sc->ps_flags |= PS_WAIT_FOR_TX_ACK; 1249 } 1250 /* 1251 * The actual restore operation will happen only after 1252 * the sc_flags bit is cleared. We are just dropping 1253 * the ps_usecount here. 1254 */ 1255 ath9k_ps_restore(sc); 1256 } 1257 1258 memset(&txctl, 0, sizeof(struct ath_tx_control)); 1259 1260 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { 1261 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 1262 sc->tx.seq_no += 0x10; 1263 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 1264 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); 1265 } 1266 1267 /* Add the padding after the header if this is not already done */ 1268 padpos = ath9k_cmn_padpos(hdr->frame_control); 1269 padsize = padpos & 3; 1270 if (padsize && skb->len>padpos) { 1271 if (skb_headroom(skb) < padsize) 1272 return -1; 1273 skb_push(skb, padsize); 1274 memmove(skb->data, skb->data + padsize, padpos); 1275 } 1276 1277 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); 1278 txctl.txq = &sc->tx.txq[qnum]; 1279 1280 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); 1281 1282 if (ath_tx_start(hw, skb, &txctl) != 0) { 1283 ath_print(common, ATH_DBG_XMIT, "TX failed\n"); 1284 goto exit; 1285 } 1286 1287 return 0; 1288exit: 1289 dev_kfree_skb_any(skb); 1290 return 0; 1291} 1292 1293static void ath9k_stop(struct ieee80211_hw *hw) 1294{ 1295 struct ath_wiphy *aphy = hw->priv; 1296 struct ath_softc *sc = aphy->sc; 1297 struct ath_hw *ah = sc->sc_ah; 1298 struct ath_common *common = ath9k_hw_common(ah); 1299 int i; 1300 1301 mutex_lock(&sc->mutex); 1302 1303 aphy->state = ATH_WIPHY_INACTIVE; 1304 1305 if (led_blink) 1306 cancel_delayed_work_sync(&sc->ath_led_blink_work); 1307 1308 cancel_delayed_work_sync(&sc->tx_complete_work); 1309 cancel_work_sync(&sc->paprd_work); 1310 cancel_work_sync(&sc->hw_check_work); 1311 1312 for (i = 0; i < sc->num_sec_wiphy; i++) { 1313 if (sc->sec_wiphy[i]) 1314 break; 1315 } 1316 1317 if (i == sc->num_sec_wiphy) { 1318 cancel_delayed_work_sync(&sc->wiphy_work); 1319 cancel_work_sync(&sc->chan_work); 1320 } 1321 1322 if (sc->sc_flags & SC_OP_INVALID) { 1323 ath_print(common, ATH_DBG_ANY, "Device not present\n"); 1324 mutex_unlock(&sc->mutex); 1325 return; 1326 } 1327 1328 if (ath9k_wiphy_started(sc)) { 1329 mutex_unlock(&sc->mutex); 1330 return; /* another wiphy still in use */ 1331 } 1332 1333 /* Ensure HW is awake when we try to shut it down. */ 1334 ath9k_ps_wakeup(sc); 1335 1336 if (ah->btcoex_hw.enabled) { 1337 ath9k_hw_btcoex_disable(ah); 1338 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) 1339 ath9k_btcoex_timer_pause(sc); 1340 } 1341 1342 /* make sure h/w will not generate any interrupt 1343 * before setting the invalid flag. */ 1344 ath9k_hw_set_interrupts(ah, 0); 1345 1346 if (!(sc->sc_flags & SC_OP_INVALID)) { 1347 ath_drain_all_txq(sc, false); 1348 spin_lock_bh(&sc->sc_pcu_lock); 1349 ath_stoprecv(sc); 1350 ath9k_hw_phy_disable(ah); 1351 spin_unlock_bh(&sc->sc_pcu_lock); 1352 } else { 1353 spin_lock_bh(&sc->sc_pcu_lock); 1354 sc->rx.rxlink = NULL; 1355 spin_unlock_bh(&sc->sc_pcu_lock); 1356 } 1357 1358 /* disable HAL and put h/w to sleep */ 1359 ath9k_hw_disable(ah); 1360 ath9k_hw_configpcipowersave(ah, 1, 1); 1361 ath9k_ps_restore(sc); 1362 1363 sc->ps_idle = true; 1364 ath9k_set_wiphy_idle(aphy, true); 1365 ath_radio_disable(sc, hw); 1366 1367 sc->sc_flags |= SC_OP_INVALID; 1368 1369 mutex_unlock(&sc->mutex); 1370 1371 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n"); 1372} 1373 1374static int ath9k_add_interface(struct ieee80211_hw *hw, 1375 struct ieee80211_vif *vif) 1376{ 1377 struct ath_wiphy *aphy = hw->priv; 1378 struct ath_softc *sc = aphy->sc; 1379 struct ath_hw *ah = sc->sc_ah; 1380 struct ath_common *common = ath9k_hw_common(ah); 1381 struct ath_vif *avp = (void *)vif->drv_priv; 1382 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED; 1383 int ret = 0; 1384 1385 mutex_lock(&sc->mutex); 1386 1387 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) && 1388 sc->nvifs > 0) { 1389 ret = -ENOBUFS; 1390 goto out; 1391 } 1392 1393 switch (vif->type) { 1394 case NL80211_IFTYPE_STATION: 1395 ic_opmode = NL80211_IFTYPE_STATION; 1396 break; 1397 case NL80211_IFTYPE_ADHOC: 1398 case NL80211_IFTYPE_AP: 1399 case NL80211_IFTYPE_MESH_POINT: 1400 if (sc->nbcnvifs >= ATH_BCBUF) { 1401 ret = -ENOBUFS; 1402 goto out; 1403 } 1404 ic_opmode = vif->type; 1405 break; 1406 default: 1407 ath_print(common, ATH_DBG_FATAL, 1408 "Interface type %d not yet supported\n", vif->type); 1409 ret = -EOPNOTSUPP; 1410 goto out; 1411 } 1412 1413 ath_print(common, ATH_DBG_CONFIG, 1414 "Attach a VIF of type: %d\n", ic_opmode); 1415 1416 /* Set the VIF opmode */ 1417 avp->av_opmode = ic_opmode; 1418 avp->av_bslot = -1; 1419 1420 sc->nvifs++; 1421 1422 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) 1423 ath9k_set_bssid_mask(hw); 1424 1425 if (sc->nvifs > 1) 1426 goto out; /* skip global settings for secondary vif */ 1427 1428 if (ic_opmode == NL80211_IFTYPE_AP) { 1429 ath9k_hw_set_tsfadjust(ah, 1); 1430 sc->sc_flags |= SC_OP_TSF_RESET; 1431 } 1432 1433 /* Set the device opmode */ 1434 ah->opmode = ic_opmode; 1435 1436 /* 1437 * Enable MIB interrupts when there are hardware phy counters. 1438 * Note we only do this (at the moment) for station mode. 1439 */ 1440 if ((vif->type == NL80211_IFTYPE_STATION) || 1441 (vif->type == NL80211_IFTYPE_ADHOC) || 1442 (vif->type == NL80211_IFTYPE_MESH_POINT)) { 1443 if (ah->config.enable_ani) 1444 ah->imask |= ATH9K_INT_MIB; 1445 ah->imask |= ATH9K_INT_TSFOOR; 1446 } 1447 1448 ath9k_hw_set_interrupts(ah, ah->imask); 1449 1450 if (vif->type == NL80211_IFTYPE_AP || 1451 vif->type == NL80211_IFTYPE_ADHOC || 1452 vif->type == NL80211_IFTYPE_MONITOR) { 1453 sc->sc_flags |= SC_OP_ANI_RUN; 1454 ath_start_ani(common); 1455 } 1456 1457out: 1458 mutex_unlock(&sc->mutex); 1459 return ret; 1460} 1461 1462static void ath9k_remove_interface(struct ieee80211_hw *hw, 1463 struct ieee80211_vif *vif) 1464{ 1465 struct ath_wiphy *aphy = hw->priv; 1466 struct ath_softc *sc = aphy->sc; 1467 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1468 struct ath_vif *avp = (void *)vif->drv_priv; 1469 bool bs_valid = false; 1470 int i; 1471 1472 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n"); 1473 1474 mutex_lock(&sc->mutex); 1475 1476 /* Stop ANI */ 1477 sc->sc_flags &= ~SC_OP_ANI_RUN; 1478 del_timer_sync(&common->ani.timer); 1479 1480 /* Reclaim beacon resources */ 1481 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || 1482 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) || 1483 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) { 1484 ath9k_ps_wakeup(sc); 1485 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); 1486 ath9k_ps_restore(sc); 1487 } 1488 1489 ath_beacon_return(sc, avp); 1490 sc->sc_flags &= ~SC_OP_BEACONS; 1491 1492 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { 1493 if (sc->beacon.bslot[i] == vif) { 1494 printk(KERN_DEBUG "%s: vif had allocated beacon " 1495 "slot\n", __func__); 1496 sc->beacon.bslot[i] = NULL; 1497 sc->beacon.bslot_aphy[i] = NULL; 1498 } else if (sc->beacon.bslot[i]) 1499 bs_valid = true; 1500 } 1501 if (!bs_valid && (sc->sc_ah->imask & ATH9K_INT_SWBA)) { 1502 /* Disable SWBA interrupt */ 1503 sc->sc_ah->imask &= ~ATH9K_INT_SWBA; 1504 ath9k_ps_wakeup(sc); 1505 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask); 1506 ath9k_ps_restore(sc); 1507 } 1508 1509 sc->nvifs--; 1510 1511 mutex_unlock(&sc->mutex); 1512} 1513 1514void ath9k_enable_ps(struct ath_softc *sc) 1515{ 1516 struct ath_hw *ah = sc->sc_ah; 1517 1518 sc->ps_enabled = true; 1519 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1520 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { 1521 ah->imask |= ATH9K_INT_TIM_TIMER; 1522 ath9k_hw_set_interrupts(ah, ah->imask); 1523 } 1524 ath9k_hw_setrxabort(ah, 1); 1525 } 1526} 1527 1528static int ath9k_config(struct ieee80211_hw *hw, u32 changed) 1529{ 1530 struct ath_wiphy *aphy = hw->priv; 1531 struct ath_softc *sc = aphy->sc; 1532 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1533 struct ieee80211_conf *conf = &hw->conf; 1534 struct ath_hw *ah = sc->sc_ah; 1535 bool disable_radio; 1536 1537 mutex_lock(&sc->mutex); 1538 1539 /* 1540 * Leave this as the first check because we need to turn on the 1541 * radio if it was disabled before prior to processing the rest 1542 * of the changes. Likewise we must only disable the radio towards 1543 * the end. 1544 */ 1545 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1546 bool enable_radio; 1547 bool all_wiphys_idle; 1548 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE); 1549 1550 spin_lock_bh(&sc->wiphy_lock); 1551 all_wiphys_idle = ath9k_all_wiphys_idle(sc); 1552 ath9k_set_wiphy_idle(aphy, idle); 1553 1554 enable_radio = (!idle && all_wiphys_idle); 1555 1556 /* 1557 * After we unlock here its possible another wiphy 1558 * can be re-renabled so to account for that we will 1559 * only disable the radio toward the end of this routine 1560 * if by then all wiphys are still idle. 1561 */ 1562 spin_unlock_bh(&sc->wiphy_lock); 1563 1564 if (enable_radio) { 1565 sc->ps_idle = false; 1566 ath_radio_enable(sc, hw); 1567 ath_print(common, ATH_DBG_CONFIG, 1568 "not-idle: enabling radio\n"); 1569 } 1570 } 1571 1572 /* 1573 * We just prepare to enable PS. We have to wait until our AP has 1574 * ACK'd our null data frame to disable RX otherwise we'll ignore 1575 * those ACKs and end up retransmitting the same null data frames. 1576 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. 1577 */ 1578 if (changed & IEEE80211_CONF_CHANGE_PS) { 1579 unsigned long flags; 1580 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1581 if (conf->flags & IEEE80211_CONF_PS) { 1582 sc->ps_flags |= PS_ENABLED; 1583 /* 1584 * At this point we know hardware has received an ACK 1585 * of a previously sent null data frame. 1586 */ 1587 if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) { 1588 sc->ps_flags &= ~PS_NULLFUNC_COMPLETED; 1589 ath9k_enable_ps(sc); 1590 } 1591 } else { 1592 sc->ps_enabled = false; 1593 sc->ps_flags &= ~(PS_ENABLED | 1594 PS_NULLFUNC_COMPLETED); 1595 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 1596 if (!(ah->caps.hw_caps & 1597 ATH9K_HW_CAP_AUTOSLEEP)) { 1598 ath9k_hw_setrxabort(sc->sc_ah, 0); 1599 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | 1600 PS_WAIT_FOR_CAB | 1601 PS_WAIT_FOR_PSPOLL_DATA | 1602 PS_WAIT_FOR_TX_ACK); 1603 if (ah->imask & ATH9K_INT_TIM_TIMER) { 1604 ah->imask &= ~ATH9K_INT_TIM_TIMER; 1605 ath9k_hw_set_interrupts(sc->sc_ah, 1606 ah->imask); 1607 } 1608 } 1609 } 1610 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1611 } 1612 1613 if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 1614 if (conf->flags & IEEE80211_CONF_MONITOR) { 1615 ath_print(common, ATH_DBG_CONFIG, 1616 "HW opmode set to Monitor mode\n"); 1617 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR; 1618 } 1619 } 1620 1621 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 1622 struct ieee80211_channel *curchan = hw->conf.channel; 1623 int pos = curchan->hw_value; 1624 1625 aphy->chan_idx = pos; 1626 aphy->chan_is_ht = conf_is_ht(conf); 1627 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) 1628 sc->sc_flags |= SC_OP_OFFCHANNEL; 1629 else 1630 sc->sc_flags &= ~SC_OP_OFFCHANNEL; 1631 1632 if (aphy->state == ATH_WIPHY_SCAN || 1633 aphy->state == ATH_WIPHY_ACTIVE) 1634 ath9k_wiphy_pause_all_forced(sc, aphy); 1635 else { 1636 /* 1637 * Do not change operational channel based on a paused 1638 * wiphy changes. 1639 */ 1640 goto skip_chan_change; 1641 } 1642 1643 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n", 1644 curchan->center_freq); 1645 1646 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); 1647 1648 ath_update_chainmask(sc, conf_is_ht(conf)); 1649 1650 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { 1651 ath_print(common, ATH_DBG_FATAL, 1652 "Unable to set channel\n"); 1653 mutex_unlock(&sc->mutex); 1654 return -EINVAL; 1655 } 1656 } 1657 1658skip_chan_change: 1659 if (changed & IEEE80211_CONF_CHANGE_POWER) { 1660 sc->config.txpowlimit = 2 * conf->power_level; 1661 ath_update_txpow(sc); 1662 } 1663 1664 spin_lock_bh(&sc->wiphy_lock); 1665 disable_radio = ath9k_all_wiphys_idle(sc); 1666 spin_unlock_bh(&sc->wiphy_lock); 1667 1668 if (disable_radio) { 1669 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n"); 1670 sc->ps_idle = true; 1671 ath_radio_disable(sc, hw); 1672 } 1673 1674 mutex_unlock(&sc->mutex); 1675 1676 return 0; 1677} 1678 1679#define SUPPORTED_FILTERS \ 1680 (FIF_PROMISC_IN_BSS | \ 1681 FIF_ALLMULTI | \ 1682 FIF_CONTROL | \ 1683 FIF_PSPOLL | \ 1684 FIF_OTHER_BSS | \ 1685 FIF_BCN_PRBRESP_PROMISC | \ 1686 FIF_FCSFAIL) 1687 1688static void ath9k_configure_filter(struct ieee80211_hw *hw, 1689 unsigned int changed_flags, 1690 unsigned int *total_flags, 1691 u64 multicast) 1692{ 1693 struct ath_wiphy *aphy = hw->priv; 1694 struct ath_softc *sc = aphy->sc; 1695 u32 rfilt; 1696 1697 changed_flags &= SUPPORTED_FILTERS; 1698 *total_flags &= SUPPORTED_FILTERS; 1699 1700 sc->rx.rxfilter = *total_flags; 1701 ath9k_ps_wakeup(sc); 1702 rfilt = ath_calcrxfilter(sc); 1703 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 1704 ath9k_ps_restore(sc); 1705 1706 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, 1707 "Set HW RX filter: 0x%x\n", rfilt); 1708} 1709 1710static int ath9k_sta_add(struct ieee80211_hw *hw, 1711 struct ieee80211_vif *vif, 1712 struct ieee80211_sta *sta) 1713{ 1714 struct ath_wiphy *aphy = hw->priv; 1715 struct ath_softc *sc = aphy->sc; 1716 1717 ath_node_attach(sc, sta); 1718 1719 return 0; 1720} 1721 1722static int ath9k_sta_remove(struct ieee80211_hw *hw, 1723 struct ieee80211_vif *vif, 1724 struct ieee80211_sta *sta) 1725{ 1726 struct ath_wiphy *aphy = hw->priv; 1727 struct ath_softc *sc = aphy->sc; 1728 1729 ath_node_detach(sc, sta); 1730 1731 return 0; 1732} 1733 1734static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, 1735 const struct ieee80211_tx_queue_params *params) 1736{ 1737 struct ath_wiphy *aphy = hw->priv; 1738 struct ath_softc *sc = aphy->sc; 1739 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1740 struct ath9k_tx_queue_info qi; 1741 int ret = 0, qnum; 1742 1743 if (queue >= WME_NUM_AC) 1744 return 0; 1745 1746 mutex_lock(&sc->mutex); 1747 1748 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); 1749 1750 qi.tqi_aifs = params->aifs; 1751 qi.tqi_cwmin = params->cw_min; 1752 qi.tqi_cwmax = params->cw_max; 1753 qi.tqi_burstTime = params->txop; 1754 qnum = ath_get_hal_qnum(queue, sc); 1755 1756 ath_print(common, ATH_DBG_CONFIG, 1757 "Configure tx [queue/halq] [%d/%d], " 1758 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1759 queue, qnum, params->aifs, params->cw_min, 1760 params->cw_max, params->txop); 1761 1762 ret = ath_txq_update(sc, qnum, &qi); 1763 if (ret) 1764 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n"); 1765 1766 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) 1767 if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret) 1768 ath_beaconq_config(sc); 1769 1770 mutex_unlock(&sc->mutex); 1771 1772 return ret; 1773} 1774 1775static int ath9k_set_key(struct ieee80211_hw *hw, 1776 enum set_key_cmd cmd, 1777 struct ieee80211_vif *vif, 1778 struct ieee80211_sta *sta, 1779 struct ieee80211_key_conf *key) 1780{ 1781 struct ath_wiphy *aphy = hw->priv; 1782 struct ath_softc *sc = aphy->sc; 1783 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1784 int ret = 0; 1785 1786 if (modparam_nohwcrypt) 1787 return -ENOSPC; 1788 1789 mutex_lock(&sc->mutex); 1790 ath9k_ps_wakeup(sc); 1791 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n"); 1792 1793 switch (cmd) { 1794 case SET_KEY: 1795 ret = ath9k_cmn_key_config(common, vif, sta, key); 1796 if (ret >= 0) { 1797 key->hw_key_idx = ret; 1798 /* push IV and Michael MIC generation to stack */ 1799 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 1800 if (key->alg == ALG_TKIP) 1801 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 1802 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP) 1803 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; 1804 ret = 0; 1805 } 1806 break; 1807 case DISABLE_KEY: 1808 ath9k_cmn_key_delete(common, key); 1809 break; 1810 default: 1811 ret = -EINVAL; 1812 } 1813 1814 ath9k_ps_restore(sc); 1815 mutex_unlock(&sc->mutex); 1816 1817 return ret; 1818} 1819 1820static void ath9k_bss_info_changed(struct ieee80211_hw *hw, 1821 struct ieee80211_vif *vif, 1822 struct ieee80211_bss_conf *bss_conf, 1823 u32 changed) 1824{ 1825 struct ath_wiphy *aphy = hw->priv; 1826 struct ath_softc *sc = aphy->sc; 1827 struct ath_hw *ah = sc->sc_ah; 1828 struct ath_common *common = ath9k_hw_common(ah); 1829 struct ath_vif *avp = (void *)vif->drv_priv; 1830 int slottime; 1831 int error; 1832 1833 mutex_lock(&sc->mutex); 1834 1835 if (changed & BSS_CHANGED_BSSID) { 1836 /* Set BSSID */ 1837 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1838 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); 1839 common->curaid = 0; 1840 ath9k_hw_write_associd(ah); 1841 1842 /* Set aggregation protection mode parameters */ 1843 sc->config.ath_aggr_prot = 0; 1844 1845 /* Only legacy IBSS for now */ 1846 if (vif->type == NL80211_IFTYPE_ADHOC) 1847 ath_update_chainmask(sc, 0); 1848 1849 ath_print(common, ATH_DBG_CONFIG, 1850 "BSSID: %pM aid: 0x%x\n", 1851 common->curbssid, common->curaid); 1852 1853 /* need to reconfigure the beacon */ 1854 sc->sc_flags &= ~SC_OP_BEACONS ; 1855 } 1856 1857 /* Enable transmission of beacons (AP, IBSS, MESH) */ 1858 if ((changed & BSS_CHANGED_BEACON) || 1859 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) { 1860 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); 1861 error = ath_beacon_alloc(aphy, vif); 1862 if (!error) 1863 ath_beacon_config(sc, vif); 1864 } 1865 1866 if (changed & BSS_CHANGED_ERP_SLOT) { 1867 if (bss_conf->use_short_slot) 1868 slottime = 9; 1869 else 1870 slottime = 20; 1871 if (vif->type == NL80211_IFTYPE_AP) { 1872 /* 1873 * Defer update, so that connected stations can adjust 1874 * their settings at the same time. 1875 * See beacon.c for more details 1876 */ 1877 sc->beacon.slottime = slottime; 1878 sc->beacon.updateslot = UPDATE; 1879 } else { 1880 ah->slottime = slottime; 1881 ath9k_hw_init_global_settings(ah); 1882 } 1883 } 1884 1885 /* Disable transmission of beacons */ 1886 if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon) 1887 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); 1888 1889 if (changed & BSS_CHANGED_BEACON_INT) { 1890 sc->beacon_interval = bss_conf->beacon_int; 1891 /* 1892 * In case of AP mode, the HW TSF has to be reset 1893 * when the beacon interval changes. 1894 */ 1895 if (vif->type == NL80211_IFTYPE_AP) { 1896 sc->sc_flags |= SC_OP_TSF_RESET; 1897 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); 1898 error = ath_beacon_alloc(aphy, vif); 1899 if (!error) 1900 ath_beacon_config(sc, vif); 1901 } else { 1902 ath_beacon_config(sc, vif); 1903 } 1904 } 1905 1906 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 1907 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", 1908 bss_conf->use_short_preamble); 1909 if (bss_conf->use_short_preamble) 1910 sc->sc_flags |= SC_OP_PREAMBLE_SHORT; 1911 else 1912 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; 1913 } 1914 1915 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 1916 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", 1917 bss_conf->use_cts_prot); 1918 if (bss_conf->use_cts_prot && 1919 hw->conf.channel->band != IEEE80211_BAND_5GHZ) 1920 sc->sc_flags |= SC_OP_PROTECT_ENABLE; 1921 else 1922 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; 1923 } 1924 1925 if (changed & BSS_CHANGED_ASSOC) { 1926 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", 1927 bss_conf->assoc); 1928 ath9k_bss_assoc_info(sc, vif, bss_conf); 1929 } 1930 1931 mutex_unlock(&sc->mutex); 1932} 1933 1934static u64 ath9k_get_tsf(struct ieee80211_hw *hw) 1935{ 1936 u64 tsf; 1937 struct ath_wiphy *aphy = hw->priv; 1938 struct ath_softc *sc = aphy->sc; 1939 1940 mutex_lock(&sc->mutex); 1941 tsf = ath9k_hw_gettsf64(sc->sc_ah); 1942 mutex_unlock(&sc->mutex); 1943 1944 return tsf; 1945} 1946 1947static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf) 1948{ 1949 struct ath_wiphy *aphy = hw->priv; 1950 struct ath_softc *sc = aphy->sc; 1951 1952 mutex_lock(&sc->mutex); 1953 ath9k_hw_settsf64(sc->sc_ah, tsf); 1954 mutex_unlock(&sc->mutex); 1955} 1956 1957static void ath9k_reset_tsf(struct ieee80211_hw *hw) 1958{ 1959 struct ath_wiphy *aphy = hw->priv; 1960 struct ath_softc *sc = aphy->sc; 1961 1962 mutex_lock(&sc->mutex); 1963 1964 ath9k_ps_wakeup(sc); 1965 ath9k_hw_reset_tsf(sc->sc_ah); 1966 ath9k_ps_restore(sc); 1967 1968 mutex_unlock(&sc->mutex); 1969} 1970 1971static int ath9k_ampdu_action(struct ieee80211_hw *hw, 1972 struct ieee80211_vif *vif, 1973 enum ieee80211_ampdu_mlme_action action, 1974 struct ieee80211_sta *sta, 1975 u16 tid, u16 *ssn) 1976{ 1977 struct ath_wiphy *aphy = hw->priv; 1978 struct ath_softc *sc = aphy->sc; 1979 int ret = 0; 1980 1981 local_bh_disable(); 1982 1983 switch (action) { 1984 case IEEE80211_AMPDU_RX_START: 1985 if (!(sc->sc_flags & SC_OP_RXAGGR)) 1986 ret = -ENOTSUPP; 1987 break; 1988 case IEEE80211_AMPDU_RX_STOP: 1989 break; 1990 case IEEE80211_AMPDU_TX_START: 1991 ath9k_ps_wakeup(sc); 1992 ret = ath_tx_aggr_start(sc, sta, tid, ssn); 1993 if (!ret) 1994 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1995 ath9k_ps_restore(sc); 1996 break; 1997 case IEEE80211_AMPDU_TX_STOP: 1998 ath9k_ps_wakeup(sc); 1999 ath_tx_aggr_stop(sc, sta, tid); 2000 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 2001 ath9k_ps_restore(sc); 2002 break; 2003 case IEEE80211_AMPDU_TX_OPERATIONAL: 2004 ath9k_ps_wakeup(sc); 2005 ath_tx_aggr_resume(sc, sta, tid); 2006 ath9k_ps_restore(sc); 2007 break; 2008 default: 2009 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, 2010 "Unknown AMPDU action\n"); 2011 } 2012 2013 local_bh_enable(); 2014 2015 return ret; 2016} 2017 2018static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, 2019 struct survey_info *survey) 2020{ 2021 struct ath_wiphy *aphy = hw->priv; 2022 struct ath_softc *sc = aphy->sc; 2023 struct ath_hw *ah = sc->sc_ah; 2024 struct ath_common *common = ath9k_hw_common(ah); 2025 struct ieee80211_conf *conf = &hw->conf; 2026 2027 if (idx != 0) 2028 return -ENOENT; 2029 2030 survey->channel = conf->channel; 2031 survey->filled = SURVEY_INFO_NOISE_DBM; 2032 survey->noise = common->ani.noise_floor; 2033 2034 return 0; 2035} 2036 2037static void ath9k_sw_scan_start(struct ieee80211_hw *hw) 2038{ 2039 struct ath_wiphy *aphy = hw->priv; 2040 struct ath_softc *sc = aphy->sc; 2041 2042 mutex_lock(&sc->mutex); 2043 if (ath9k_wiphy_scanning(sc)) { 2044 /* 2045 * There is a race here in mac80211 but fixing it requires 2046 * we revisit how we handle the scan complete callback. 2047 * After mac80211 fixes we will not have configured hardware 2048 * to the home channel nor would we have configured the RX 2049 * filter yet. 2050 */ 2051 mutex_unlock(&sc->mutex); 2052 return; 2053 } 2054 2055 aphy->state = ATH_WIPHY_SCAN; 2056 ath9k_wiphy_pause_all_forced(sc, aphy); 2057 mutex_unlock(&sc->mutex); 2058} 2059 2060static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) 2061{ 2062 struct ath_wiphy *aphy = hw->priv; 2063 struct ath_softc *sc = aphy->sc; 2064 2065 mutex_lock(&sc->mutex); 2066 aphy->state = ATH_WIPHY_ACTIVE; 2067 mutex_unlock(&sc->mutex); 2068} 2069 2070static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) 2071{ 2072 struct ath_wiphy *aphy = hw->priv; 2073 struct ath_softc *sc = aphy->sc; 2074 struct ath_hw *ah = sc->sc_ah; 2075 2076 mutex_lock(&sc->mutex); 2077 ah->coverage_class = coverage_class; 2078 ath9k_hw_init_global_settings(ah); 2079 mutex_unlock(&sc->mutex); 2080} 2081 2082struct ieee80211_ops ath9k_ops = { 2083 .tx = ath9k_tx, 2084 .start = ath9k_start, 2085 .stop = ath9k_stop, 2086 .add_interface = ath9k_add_interface, 2087 .remove_interface = ath9k_remove_interface, 2088 .config = ath9k_config, 2089 .configure_filter = ath9k_configure_filter, 2090 .sta_add = ath9k_sta_add, 2091 .sta_remove = ath9k_sta_remove, 2092 .conf_tx = ath9k_conf_tx, 2093 .bss_info_changed = ath9k_bss_info_changed, 2094 .set_key = ath9k_set_key, 2095 .get_tsf = ath9k_get_tsf, 2096 .set_tsf = ath9k_set_tsf, 2097 .reset_tsf = ath9k_reset_tsf, 2098 .ampdu_action = ath9k_ampdu_action, 2099 .get_survey = ath9k_get_survey, 2100 .sw_scan_start = ath9k_sw_scan_start, 2101 .sw_scan_complete = ath9k_sw_scan_complete, 2102 .rfkill_poll = ath9k_rfkill_poll_state, 2103 .set_coverage_class = ath9k_set_coverage_class, 2104}; 2105