1/* 2 * driver/mfd/asic3.c 3 * 4 * Compaq ASIC3 support. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Copyright 2001 Compaq Computer Corporation. 11 * Copyright 2004-2005 Phil Blundell 12 * Copyright 2007-2008 OpenedHand Ltd. 13 * 14 * Authors: Phil Blundell <pb@handhelds.org>, 15 * Samuel Ortiz <sameo@openedhand.com> 16 * 17 */ 18 19#include <linux/kernel.h> 20#include <linux/delay.h> 21#include <linux/irq.h> 22#include <linux/gpio.h> 23#include <linux/io.h> 24#include <linux/slab.h> 25#include <linux/spinlock.h> 26#include <linux/platform_device.h> 27 28#include <linux/mfd/asic3.h> 29#include <linux/mfd/core.h> 30#include <linux/mfd/ds1wm.h> 31#include <linux/mfd/tmio.h> 32 33enum { 34 ASIC3_CLOCK_SPI, 35 ASIC3_CLOCK_OWM, 36 ASIC3_CLOCK_PWM0, 37 ASIC3_CLOCK_PWM1, 38 ASIC3_CLOCK_LED0, 39 ASIC3_CLOCK_LED1, 40 ASIC3_CLOCK_LED2, 41 ASIC3_CLOCK_SD_HOST, 42 ASIC3_CLOCK_SD_BUS, 43 ASIC3_CLOCK_SMBUS, 44 ASIC3_CLOCK_EX0, 45 ASIC3_CLOCK_EX1, 46}; 47 48struct asic3_clk { 49 int enabled; 50 unsigned int cdex; 51 unsigned long rate; 52}; 53 54#define INIT_CDEX(_name, _rate) \ 55 [ASIC3_CLOCK_##_name] = { \ 56 .cdex = CLOCK_CDEX_##_name, \ 57 .rate = _rate, \ 58 } 59 60struct asic3_clk asic3_clk_init[] __initdata = { 61 INIT_CDEX(SPI, 0), 62 INIT_CDEX(OWM, 5000000), 63 INIT_CDEX(PWM0, 0), 64 INIT_CDEX(PWM1, 0), 65 INIT_CDEX(LED0, 0), 66 INIT_CDEX(LED1, 0), 67 INIT_CDEX(LED2, 0), 68 INIT_CDEX(SD_HOST, 24576000), 69 INIT_CDEX(SD_BUS, 12288000), 70 INIT_CDEX(SMBUS, 0), 71 INIT_CDEX(EX0, 32768), 72 INIT_CDEX(EX1, 24576000), 73}; 74 75struct asic3 { 76 void __iomem *mapping; 77 unsigned int bus_shift; 78 unsigned int irq_nr; 79 unsigned int irq_base; 80 spinlock_t lock; 81 u16 irq_bothedge[4]; 82 struct gpio_chip gpio; 83 struct device *dev; 84 void __iomem *tmio_cnf; 85 86 struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)]; 87}; 88 89static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset); 90 91static inline void asic3_write_register(struct asic3 *asic, 92 unsigned int reg, u32 value) 93{ 94 iowrite16(value, asic->mapping + 95 (reg >> asic->bus_shift)); 96} 97 98static inline u32 asic3_read_register(struct asic3 *asic, 99 unsigned int reg) 100{ 101 return ioread16(asic->mapping + 102 (reg >> asic->bus_shift)); 103} 104 105void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set) 106{ 107 unsigned long flags; 108 u32 val; 109 110 spin_lock_irqsave(&asic->lock, flags); 111 val = asic3_read_register(asic, reg); 112 if (set) 113 val |= bits; 114 else 115 val &= ~bits; 116 asic3_write_register(asic, reg, val); 117 spin_unlock_irqrestore(&asic->lock, flags); 118} 119 120/* IRQs */ 121#define MAX_ASIC_ISR_LOOPS 20 122#define ASIC3_GPIO_BASE_INCR \ 123 (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE) 124 125static void asic3_irq_flip_edge(struct asic3 *asic, 126 u32 base, int bit) 127{ 128 u16 edge; 129 unsigned long flags; 130 131 spin_lock_irqsave(&asic->lock, flags); 132 edge = asic3_read_register(asic, 133 base + ASIC3_GPIO_EDGE_TRIGGER); 134 edge ^= bit; 135 asic3_write_register(asic, 136 base + ASIC3_GPIO_EDGE_TRIGGER, edge); 137 spin_unlock_irqrestore(&asic->lock, flags); 138} 139 140static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc) 141{ 142 int iter, i; 143 unsigned long flags; 144 struct asic3 *asic; 145 146 desc->chip->ack(irq); 147 148 asic = desc->handler_data; 149 150 for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) { 151 u32 status; 152 int bank; 153 154 spin_lock_irqsave(&asic->lock, flags); 155 status = asic3_read_register(asic, 156 ASIC3_OFFSET(INTR, P_INT_STAT)); 157 spin_unlock_irqrestore(&asic->lock, flags); 158 159 /* Check all ten register bits */ 160 if ((status & 0x3ff) == 0) 161 break; 162 163 /* Handle GPIO IRQs */ 164 for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) { 165 if (status & (1 << bank)) { 166 unsigned long base, istat; 167 168 base = ASIC3_GPIO_A_BASE 169 + bank * ASIC3_GPIO_BASE_INCR; 170 171 spin_lock_irqsave(&asic->lock, flags); 172 istat = asic3_read_register(asic, 173 base + 174 ASIC3_GPIO_INT_STATUS); 175 /* Clearing IntStatus */ 176 asic3_write_register(asic, 177 base + 178 ASIC3_GPIO_INT_STATUS, 0); 179 spin_unlock_irqrestore(&asic->lock, flags); 180 181 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) { 182 int bit = (1 << i); 183 unsigned int irqnr; 184 185 if (!(istat & bit)) 186 continue; 187 188 irqnr = asic->irq_base + 189 (ASIC3_GPIOS_PER_BANK * bank) 190 + i; 191 desc = irq_to_desc(irqnr); 192 desc->handle_irq(irqnr, desc); 193 if (asic->irq_bothedge[bank] & bit) 194 asic3_irq_flip_edge(asic, base, 195 bit); 196 } 197 } 198 } 199 200 /* Handle remaining IRQs in the status register */ 201 for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) { 202 /* They start at bit 4 and go up */ 203 if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) { 204 desc = irq_to_desc(asic->irq_base + i); 205 desc->handle_irq(asic->irq_base + i, 206 desc); 207 } 208 } 209 } 210 211 if (iter >= MAX_ASIC_ISR_LOOPS) 212 dev_err(asic->dev, "interrupt processing overrun\n"); 213} 214 215static inline int asic3_irq_to_bank(struct asic3 *asic, int irq) 216{ 217 int n; 218 219 n = (irq - asic->irq_base) >> 4; 220 221 return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)); 222} 223 224static inline int asic3_irq_to_index(struct asic3 *asic, int irq) 225{ 226 return (irq - asic->irq_base) & 0xf; 227} 228 229static void asic3_mask_gpio_irq(unsigned int irq) 230{ 231 struct asic3 *asic = get_irq_chip_data(irq); 232 u32 val, bank, index; 233 unsigned long flags; 234 235 bank = asic3_irq_to_bank(asic, irq); 236 index = asic3_irq_to_index(asic, irq); 237 238 spin_lock_irqsave(&asic->lock, flags); 239 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); 240 val |= 1 << index; 241 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val); 242 spin_unlock_irqrestore(&asic->lock, flags); 243} 244 245static void asic3_mask_irq(unsigned int irq) 246{ 247 struct asic3 *asic = get_irq_chip_data(irq); 248 int regval; 249 unsigned long flags; 250 251 spin_lock_irqsave(&asic->lock, flags); 252 regval = asic3_read_register(asic, 253 ASIC3_INTR_BASE + 254 ASIC3_INTR_INT_MASK); 255 256 regval &= ~(ASIC3_INTMASK_MASK0 << 257 (irq - (asic->irq_base + ASIC3_NUM_GPIOS))); 258 259 asic3_write_register(asic, 260 ASIC3_INTR_BASE + 261 ASIC3_INTR_INT_MASK, 262 regval); 263 spin_unlock_irqrestore(&asic->lock, flags); 264} 265 266static void asic3_unmask_gpio_irq(unsigned int irq) 267{ 268 struct asic3 *asic = get_irq_chip_data(irq); 269 u32 val, bank, index; 270 unsigned long flags; 271 272 bank = asic3_irq_to_bank(asic, irq); 273 index = asic3_irq_to_index(asic, irq); 274 275 spin_lock_irqsave(&asic->lock, flags); 276 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); 277 val &= ~(1 << index); 278 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val); 279 spin_unlock_irqrestore(&asic->lock, flags); 280} 281 282static void asic3_unmask_irq(unsigned int irq) 283{ 284 struct asic3 *asic = get_irq_chip_data(irq); 285 int regval; 286 unsigned long flags; 287 288 spin_lock_irqsave(&asic->lock, flags); 289 regval = asic3_read_register(asic, 290 ASIC3_INTR_BASE + 291 ASIC3_INTR_INT_MASK); 292 293 regval |= (ASIC3_INTMASK_MASK0 << 294 (irq - (asic->irq_base + ASIC3_NUM_GPIOS))); 295 296 asic3_write_register(asic, 297 ASIC3_INTR_BASE + 298 ASIC3_INTR_INT_MASK, 299 regval); 300 spin_unlock_irqrestore(&asic->lock, flags); 301} 302 303static int asic3_gpio_irq_type(unsigned int irq, unsigned int type) 304{ 305 struct asic3 *asic = get_irq_chip_data(irq); 306 u32 bank, index; 307 u16 trigger, level, edge, bit; 308 unsigned long flags; 309 310 bank = asic3_irq_to_bank(asic, irq); 311 index = asic3_irq_to_index(asic, irq); 312 bit = 1<<index; 313 314 spin_lock_irqsave(&asic->lock, flags); 315 level = asic3_read_register(asic, 316 bank + ASIC3_GPIO_LEVEL_TRIGGER); 317 edge = asic3_read_register(asic, 318 bank + ASIC3_GPIO_EDGE_TRIGGER); 319 trigger = asic3_read_register(asic, 320 bank + ASIC3_GPIO_TRIGGER_TYPE); 321 asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit; 322 323 if (type == IRQ_TYPE_EDGE_RISING) { 324 trigger |= bit; 325 edge |= bit; 326 } else if (type == IRQ_TYPE_EDGE_FALLING) { 327 trigger |= bit; 328 edge &= ~bit; 329 } else if (type == IRQ_TYPE_EDGE_BOTH) { 330 trigger |= bit; 331 if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base)) 332 edge &= ~bit; 333 else 334 edge |= bit; 335 asic->irq_bothedge[(irq - asic->irq_base) >> 4] |= bit; 336 } else if (type == IRQ_TYPE_LEVEL_LOW) { 337 trigger &= ~bit; 338 level &= ~bit; 339 } else if (type == IRQ_TYPE_LEVEL_HIGH) { 340 trigger &= ~bit; 341 level |= bit; 342 } else { 343 /* 344 * if type == IRQ_TYPE_NONE, we should mask interrupts, but 345 * be careful to not unmask them if mask was also called. 346 * Probably need internal state for mask. 347 */ 348 dev_notice(asic->dev, "irq type not changed\n"); 349 } 350 asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER, 351 level); 352 asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER, 353 edge); 354 asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE, 355 trigger); 356 spin_unlock_irqrestore(&asic->lock, flags); 357 return 0; 358} 359 360static struct irq_chip asic3_gpio_irq_chip = { 361 .name = "ASIC3-GPIO", 362 .ack = asic3_mask_gpio_irq, 363 .mask = asic3_mask_gpio_irq, 364 .unmask = asic3_unmask_gpio_irq, 365 .set_type = asic3_gpio_irq_type, 366}; 367 368static struct irq_chip asic3_irq_chip = { 369 .name = "ASIC3", 370 .ack = asic3_mask_irq, 371 .mask = asic3_mask_irq, 372 .unmask = asic3_unmask_irq, 373}; 374 375static int __init asic3_irq_probe(struct platform_device *pdev) 376{ 377 struct asic3 *asic = platform_get_drvdata(pdev); 378 unsigned long clksel = 0; 379 unsigned int irq, irq_base; 380 int ret; 381 382 ret = platform_get_irq(pdev, 0); 383 if (ret < 0) 384 return ret; 385 asic->irq_nr = ret; 386 387 /* turn on clock to IRQ controller */ 388 clksel |= CLOCK_SEL_CX; 389 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 390 clksel); 391 392 irq_base = asic->irq_base; 393 394 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) { 395 if (irq < asic->irq_base + ASIC3_NUM_GPIOS) 396 set_irq_chip(irq, &asic3_gpio_irq_chip); 397 else 398 set_irq_chip(irq, &asic3_irq_chip); 399 400 set_irq_chip_data(irq, asic); 401 set_irq_handler(irq, handle_level_irq); 402 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 403 } 404 405 asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK), 406 ASIC3_INTMASK_GINTMASK); 407 408 set_irq_chained_handler(asic->irq_nr, asic3_irq_demux); 409 set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING); 410 set_irq_data(asic->irq_nr, asic); 411 412 return 0; 413} 414 415static void asic3_irq_remove(struct platform_device *pdev) 416{ 417 struct asic3 *asic = platform_get_drvdata(pdev); 418 unsigned int irq, irq_base; 419 420 irq_base = asic->irq_base; 421 422 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) { 423 set_irq_flags(irq, 0); 424 set_irq_handler(irq, NULL); 425 set_irq_chip(irq, NULL); 426 set_irq_chip_data(irq, NULL); 427 } 428 set_irq_chained_handler(asic->irq_nr, NULL); 429} 430 431/* GPIOs */ 432static int asic3_gpio_direction(struct gpio_chip *chip, 433 unsigned offset, int out) 434{ 435 u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg; 436 unsigned int gpio_base; 437 unsigned long flags; 438 struct asic3 *asic; 439 440 asic = container_of(chip, struct asic3, gpio); 441 gpio_base = ASIC3_GPIO_TO_BASE(offset); 442 443 if (gpio_base > ASIC3_GPIO_D_BASE) { 444 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", 445 gpio_base, offset); 446 return -EINVAL; 447 } 448 449 spin_lock_irqsave(&asic->lock, flags); 450 451 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION); 452 453 /* Input is 0, Output is 1 */ 454 if (out) 455 out_reg |= mask; 456 else 457 out_reg &= ~mask; 458 459 asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg); 460 461 spin_unlock_irqrestore(&asic->lock, flags); 462 463 return 0; 464 465} 466 467static int asic3_gpio_direction_input(struct gpio_chip *chip, 468 unsigned offset) 469{ 470 return asic3_gpio_direction(chip, offset, 0); 471} 472 473static int asic3_gpio_direction_output(struct gpio_chip *chip, 474 unsigned offset, int value) 475{ 476 return asic3_gpio_direction(chip, offset, 1); 477} 478 479static int asic3_gpio_get(struct gpio_chip *chip, 480 unsigned offset) 481{ 482 unsigned int gpio_base; 483 u32 mask = ASIC3_GPIO_TO_MASK(offset); 484 struct asic3 *asic; 485 486 asic = container_of(chip, struct asic3, gpio); 487 gpio_base = ASIC3_GPIO_TO_BASE(offset); 488 489 if (gpio_base > ASIC3_GPIO_D_BASE) { 490 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", 491 gpio_base, offset); 492 return -EINVAL; 493 } 494 495 return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask; 496} 497 498static void asic3_gpio_set(struct gpio_chip *chip, 499 unsigned offset, int value) 500{ 501 u32 mask, out_reg; 502 unsigned int gpio_base; 503 unsigned long flags; 504 struct asic3 *asic; 505 506 asic = container_of(chip, struct asic3, gpio); 507 gpio_base = ASIC3_GPIO_TO_BASE(offset); 508 509 if (gpio_base > ASIC3_GPIO_D_BASE) { 510 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", 511 gpio_base, offset); 512 return; 513 } 514 515 mask = ASIC3_GPIO_TO_MASK(offset); 516 517 spin_lock_irqsave(&asic->lock, flags); 518 519 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT); 520 521 if (value) 522 out_reg |= mask; 523 else 524 out_reg &= ~mask; 525 526 asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg); 527 528 spin_unlock_irqrestore(&asic->lock, flags); 529 530 return; 531} 532 533static __init int asic3_gpio_probe(struct platform_device *pdev, 534 u16 *gpio_config, int num) 535{ 536 struct asic3 *asic = platform_get_drvdata(pdev); 537 u16 alt_reg[ASIC3_NUM_GPIO_BANKS]; 538 u16 out_reg[ASIC3_NUM_GPIO_BANKS]; 539 u16 dir_reg[ASIC3_NUM_GPIO_BANKS]; 540 int i; 541 542 memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); 543 memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); 544 memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); 545 546 /* Enable all GPIOs */ 547 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff); 548 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff); 549 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff); 550 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff); 551 552 for (i = 0; i < num; i++) { 553 u8 alt, pin, dir, init, bank_num, bit_num; 554 u16 config = gpio_config[i]; 555 556 pin = ASIC3_CONFIG_GPIO_PIN(config); 557 alt = ASIC3_CONFIG_GPIO_ALT(config); 558 dir = ASIC3_CONFIG_GPIO_DIR(config); 559 init = ASIC3_CONFIG_GPIO_INIT(config); 560 561 bank_num = ASIC3_GPIO_TO_BANK(pin); 562 bit_num = ASIC3_GPIO_TO_BIT(pin); 563 564 alt_reg[bank_num] |= (alt << bit_num); 565 out_reg[bank_num] |= (init << bit_num); 566 dir_reg[bank_num] |= (dir << bit_num); 567 } 568 569 for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) { 570 asic3_write_register(asic, 571 ASIC3_BANK_TO_BASE(i) + 572 ASIC3_GPIO_DIRECTION, 573 dir_reg[i]); 574 asic3_write_register(asic, 575 ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT, 576 out_reg[i]); 577 asic3_write_register(asic, 578 ASIC3_BANK_TO_BASE(i) + 579 ASIC3_GPIO_ALT_FUNCTION, 580 alt_reg[i]); 581 } 582 583 return gpiochip_add(&asic->gpio); 584} 585 586static int asic3_gpio_remove(struct platform_device *pdev) 587{ 588 struct asic3 *asic = platform_get_drvdata(pdev); 589 590 return gpiochip_remove(&asic->gpio); 591} 592 593static int asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk) 594{ 595 unsigned long flags; 596 u32 cdex; 597 598 spin_lock_irqsave(&asic->lock, flags); 599 if (clk->enabled++ == 0) { 600 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX)); 601 cdex |= clk->cdex; 602 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex); 603 } 604 spin_unlock_irqrestore(&asic->lock, flags); 605 606 return 0; 607} 608 609static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk) 610{ 611 unsigned long flags; 612 u32 cdex; 613 614 WARN_ON(clk->enabled == 0); 615 616 spin_lock_irqsave(&asic->lock, flags); 617 if (--clk->enabled == 0) { 618 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX)); 619 cdex &= ~clk->cdex; 620 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex); 621 } 622 spin_unlock_irqrestore(&asic->lock, flags); 623} 624 625/* MFD cells (SPI, PWM, LED, DS1WM, MMC) */ 626static struct ds1wm_driver_data ds1wm_pdata = { 627 .active_high = 1, 628}; 629 630static struct resource ds1wm_resources[] = { 631 { 632 .start = ASIC3_OWM_BASE, 633 .end = ASIC3_OWM_BASE + 0x13, 634 .flags = IORESOURCE_MEM, 635 }, 636 { 637 .start = ASIC3_IRQ_OWM, 638 .start = ASIC3_IRQ_OWM, 639 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, 640 }, 641}; 642 643static int ds1wm_enable(struct platform_device *pdev) 644{ 645 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); 646 647 /* Turn on external clocks and the OWM clock */ 648 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); 649 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); 650 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]); 651 msleep(1); 652 653 /* Reset and enable DS1WM */ 654 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET), 655 ASIC3_EXTCF_OWM_RESET, 1); 656 msleep(1); 657 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET), 658 ASIC3_EXTCF_OWM_RESET, 0); 659 msleep(1); 660 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), 661 ASIC3_EXTCF_OWM_EN, 1); 662 msleep(1); 663 664 return 0; 665} 666 667static int ds1wm_disable(struct platform_device *pdev) 668{ 669 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); 670 671 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), 672 ASIC3_EXTCF_OWM_EN, 0); 673 674 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]); 675 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); 676 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); 677 678 return 0; 679} 680 681static struct mfd_cell asic3_cell_ds1wm = { 682 .name = "ds1wm", 683 .enable = ds1wm_enable, 684 .disable = ds1wm_disable, 685 .driver_data = &ds1wm_pdata, 686 .num_resources = ARRAY_SIZE(ds1wm_resources), 687 .resources = ds1wm_resources, 688}; 689 690static void asic3_mmc_pwr(struct platform_device *pdev, int state) 691{ 692 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); 693 694 tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state); 695} 696 697static void asic3_mmc_clk_div(struct platform_device *pdev, int state) 698{ 699 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); 700 701 tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state); 702} 703 704static struct tmio_mmc_data asic3_mmc_data = { 705 .hclk = 24576000, 706 .set_pwr = asic3_mmc_pwr, 707 .set_clk_div = asic3_mmc_clk_div, 708}; 709 710static struct resource asic3_mmc_resources[] = { 711 { 712 .start = ASIC3_SD_CTRL_BASE, 713 .end = ASIC3_SD_CTRL_BASE + 0x3ff, 714 .flags = IORESOURCE_MEM, 715 }, 716 { 717 .start = 0, 718 .end = 0, 719 .flags = IORESOURCE_IRQ, 720 }, 721}; 722 723static int asic3_mmc_enable(struct platform_device *pdev) 724{ 725 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); 726 727 /* Not sure if it must be done bit by bit, but leaving as-is */ 728 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), 729 ASIC3_SDHWCTRL_LEVCD, 1); 730 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), 731 ASIC3_SDHWCTRL_LEVWP, 1); 732 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), 733 ASIC3_SDHWCTRL_SUSPEND, 0); 734 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), 735 ASIC3_SDHWCTRL_PCLR, 0); 736 737 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); 738 /* CLK32 used for card detection and for interruption detection 739 * when HCLK is stopped. 740 */ 741 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); 742 msleep(1); 743 744 /* HCLK 24.576 MHz, BCLK 12.288 MHz: */ 745 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 746 CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL); 747 748 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]); 749 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]); 750 msleep(1); 751 752 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), 753 ASIC3_EXTCF_SD_MEM_ENABLE, 1); 754 755 /* Enable SD card slot 3.3V power supply */ 756 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), 757 ASIC3_SDHWCTRL_SDPWR, 1); 758 759 /* ASIC3_SD_CTRL_BASE assumes 32-bit addressing, TMIO is 16-bit */ 760 tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift, 761 ASIC3_SD_CTRL_BASE >> 1); 762 763 return 0; 764} 765 766static int asic3_mmc_disable(struct platform_device *pdev) 767{ 768 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); 769 770 /* Put in suspend mode */ 771 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), 772 ASIC3_SDHWCTRL_SUSPEND, 1); 773 774 /* Disable clocks */ 775 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]); 776 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]); 777 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); 778 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); 779 return 0; 780} 781 782static struct mfd_cell asic3_cell_mmc = { 783 .name = "tmio-mmc", 784 .enable = asic3_mmc_enable, 785 .disable = asic3_mmc_disable, 786 .driver_data = &asic3_mmc_data, 787 .num_resources = ARRAY_SIZE(asic3_mmc_resources), 788 .resources = asic3_mmc_resources, 789}; 790 791static int __init asic3_mfd_probe(struct platform_device *pdev, 792 struct resource *mem) 793{ 794 struct asic3 *asic = platform_get_drvdata(pdev); 795 struct resource *mem_sdio; 796 int irq, ret; 797 798 mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1); 799 if (!mem_sdio) 800 dev_dbg(asic->dev, "no SDIO MEM resource\n"); 801 802 irq = platform_get_irq(pdev, 1); 803 if (irq < 0) 804 dev_dbg(asic->dev, "no SDIO IRQ resource\n"); 805 806 /* DS1WM */ 807 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), 808 ASIC3_EXTCF_OWM_SMB, 0); 809 810 ds1wm_resources[0].start >>= asic->bus_shift; 811 ds1wm_resources[0].end >>= asic->bus_shift; 812 813 asic3_cell_ds1wm.platform_data = &asic3_cell_ds1wm; 814 asic3_cell_ds1wm.data_size = sizeof(asic3_cell_ds1wm); 815 816 /* MMC */ 817 asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >> asic->bus_shift) + 818 mem_sdio->start, 0x400 >> asic->bus_shift); 819 if (!asic->tmio_cnf) { 820 ret = -ENOMEM; 821 dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n"); 822 goto out; 823 } 824 asic3_mmc_resources[0].start >>= asic->bus_shift; 825 asic3_mmc_resources[0].end >>= asic->bus_shift; 826 827 asic3_cell_mmc.platform_data = &asic3_cell_mmc; 828 asic3_cell_mmc.data_size = sizeof(asic3_cell_mmc); 829 830 ret = mfd_add_devices(&pdev->dev, pdev->id, 831 &asic3_cell_ds1wm, 1, mem, asic->irq_base); 832 if (ret < 0) 833 goto out; 834 835 if (mem_sdio && (irq >= 0)) 836 ret = mfd_add_devices(&pdev->dev, pdev->id, 837 &asic3_cell_mmc, 1, mem_sdio, irq); 838 839 out: 840 return ret; 841} 842 843static void asic3_mfd_remove(struct platform_device *pdev) 844{ 845 struct asic3 *asic = platform_get_drvdata(pdev); 846 847 mfd_remove_devices(&pdev->dev); 848 iounmap(asic->tmio_cnf); 849} 850 851/* Core */ 852static int __init asic3_probe(struct platform_device *pdev) 853{ 854 struct asic3_platform_data *pdata = pdev->dev.platform_data; 855 struct asic3 *asic; 856 struct resource *mem; 857 unsigned long clksel; 858 int ret = 0; 859 860 asic = kzalloc(sizeof(struct asic3), GFP_KERNEL); 861 if (asic == NULL) { 862 printk(KERN_ERR "kzalloc failed\n"); 863 return -ENOMEM; 864 } 865 866 spin_lock_init(&asic->lock); 867 platform_set_drvdata(pdev, asic); 868 asic->dev = &pdev->dev; 869 870 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 871 if (!mem) { 872 ret = -ENOMEM; 873 dev_err(asic->dev, "no MEM resource\n"); 874 goto out_free; 875 } 876 877 asic->mapping = ioremap(mem->start, resource_size(mem)); 878 if (!asic->mapping) { 879 ret = -ENOMEM; 880 dev_err(asic->dev, "Couldn't ioremap\n"); 881 goto out_free; 882 } 883 884 asic->irq_base = pdata->irq_base; 885 886 /* calculate bus shift from mem resource */ 887 asic->bus_shift = 2 - (resource_size(mem) >> 12); 888 889 clksel = 0; 890 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel); 891 892 ret = asic3_irq_probe(pdev); 893 if (ret < 0) { 894 dev_err(asic->dev, "Couldn't probe IRQs\n"); 895 goto out_unmap; 896 } 897 898 asic->gpio.base = pdata->gpio_base; 899 asic->gpio.ngpio = ASIC3_NUM_GPIOS; 900 asic->gpio.get = asic3_gpio_get; 901 asic->gpio.set = asic3_gpio_set; 902 asic->gpio.direction_input = asic3_gpio_direction_input; 903 asic->gpio.direction_output = asic3_gpio_direction_output; 904 905 ret = asic3_gpio_probe(pdev, 906 pdata->gpio_config, 907 pdata->gpio_config_num); 908 if (ret < 0) { 909 dev_err(asic->dev, "GPIO probe failed\n"); 910 goto out_irq; 911 } 912 913 /* Making a per-device copy is only needed for the 914 * theoretical case of multiple ASIC3s on one board: 915 */ 916 memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init)); 917 918 asic3_mfd_probe(pdev, mem); 919 920 dev_info(asic->dev, "ASIC3 Core driver\n"); 921 922 return 0; 923 924 out_irq: 925 asic3_irq_remove(pdev); 926 927 out_unmap: 928 iounmap(asic->mapping); 929 930 out_free: 931 kfree(asic); 932 933 return ret; 934} 935 936static int __devexit asic3_remove(struct platform_device *pdev) 937{ 938 int ret; 939 struct asic3 *asic = platform_get_drvdata(pdev); 940 941 asic3_mfd_remove(pdev); 942 943 ret = asic3_gpio_remove(pdev); 944 if (ret < 0) 945 return ret; 946 asic3_irq_remove(pdev); 947 948 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0); 949 950 iounmap(asic->mapping); 951 952 kfree(asic); 953 954 return 0; 955} 956 957static void asic3_shutdown(struct platform_device *pdev) 958{ 959} 960 961static struct platform_driver asic3_device_driver = { 962 .driver = { 963 .name = "asic3", 964 }, 965 .remove = __devexit_p(asic3_remove), 966 .shutdown = asic3_shutdown, 967}; 968 969static int __init asic3_init(void) 970{ 971 int retval = 0; 972 retval = platform_driver_probe(&asic3_device_driver, asic3_probe); 973 return retval; 974} 975 976subsys_initcall(asic3_init); 977