1/* 2 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org> 3 * Copyright (C) 2006-2007, 2009 MontaVista Software, Inc. 4 * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz 5 * 6 * Portions Copyright (C) 1999 Promise Technology, Inc. 7 * Author: Frank Tiernan (frankt@promise.com) 8 * Released under terms of General Public License 9 */ 10 11#include <linux/types.h> 12#include <linux/module.h> 13#include <linux/kernel.h> 14#include <linux/delay.h> 15#include <linux/blkdev.h> 16#include <linux/pci.h> 17#include <linux/init.h> 18#include <linux/ide.h> 19 20#include <asm/io.h> 21 22#define DRV_NAME "pdc202xx_old" 23 24static void pdc202xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive) 25{ 26 struct pci_dev *dev = to_pci_dev(hwif->dev); 27 u8 drive_pci = 0x60 + (drive->dn << 2); 28 const u8 speed = drive->dma_mode; 29 30 u8 AP = 0, BP = 0, CP = 0; 31 u8 TA = 0, TB = 0, TC = 0; 32 33 pci_read_config_byte(dev, drive_pci, &AP); 34 pci_read_config_byte(dev, drive_pci + 1, &BP); 35 pci_read_config_byte(dev, drive_pci + 2, &CP); 36 37 switch(speed) { 38 case XFER_UDMA_5: 39 case XFER_UDMA_4: TB = 0x20; TC = 0x01; break; 40 case XFER_UDMA_2: TB = 0x20; TC = 0x01; break; 41 case XFER_UDMA_3: 42 case XFER_UDMA_1: TB = 0x40; TC = 0x02; break; 43 case XFER_UDMA_0: 44 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break; 45 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break; 46 case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break; 47 case XFER_PIO_4: TA = 0x01; TB = 0x04; break; 48 case XFER_PIO_3: TA = 0x02; TB = 0x06; break; 49 case XFER_PIO_2: TA = 0x03; TB = 0x08; break; 50 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break; 51 case XFER_PIO_0: 52 default: TA = 0x09; TB = 0x13; break; 53 } 54 55 if (speed < XFER_SW_DMA_0) { 56 /* 57 * preserve SYNC_INT / ERDDY_EN bits while clearing 58 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A 59 */ 60 AP &= ~0x3f; 61 if (ide_pio_need_iordy(drive, speed - XFER_PIO_0)) 62 AP |= 0x20; /* set IORDY_EN bit */ 63 if (drive->media == ide_disk) 64 AP |= 0x10; /* set Prefetch_EN bit */ 65 /* clear PB[4:0] bits of register B */ 66 BP &= ~0x1f; 67 pci_write_config_byte(dev, drive_pci, AP | TA); 68 pci_write_config_byte(dev, drive_pci + 1, BP | TB); 69 } else { 70 /* clear MB[2:0] bits of register B */ 71 BP &= ~0xe0; 72 /* clear MC[3:0] bits of register C */ 73 CP &= ~0x0f; 74 pci_write_config_byte(dev, drive_pci + 1, BP | TB); 75 pci_write_config_byte(dev, drive_pci + 2, CP | TC); 76 } 77} 78 79static void pdc202xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) 80{ 81 drive->dma_mode = drive->pio_mode; 82 pdc202xx_set_mode(hwif, drive); 83} 84 85static int pdc202xx_test_irq(ide_hwif_t *hwif) 86{ 87 struct pci_dev *dev = to_pci_dev(hwif->dev); 88 unsigned long high_16 = pci_resource_start(dev, 4); 89 u8 sc1d = inb(high_16 + 0x1d); 90 91 if (hwif->channel) { 92 /* 93 * bit 7: error, bit 6: interrupting, 94 * bit 5: FIFO full, bit 4: FIFO empty 95 */ 96 return (sc1d & 0x40) ? 1 : 0; 97 } else { 98 /* 99 * bit 3: error, bit 2: interrupting, 100 * bit 1: FIFO full, bit 0: FIFO empty 101 */ 102 return (sc1d & 0x04) ? 1 : 0; 103 } 104} 105 106static u8 pdc2026x_cable_detect(ide_hwif_t *hwif) 107{ 108 struct pci_dev *dev = to_pci_dev(hwif->dev); 109 u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10); 110 111 pci_read_config_word(dev, 0x50, &CIS); 112 113 return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; 114} 115 116static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif) 117{ 118 unsigned long clock_reg = hwif->extra_base + 0x01; 119 u8 clock = inb(clock_reg); 120 121 outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg); 122} 123 124static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif) 125{ 126 unsigned long clock_reg = hwif->extra_base + 0x01; 127 u8 clock = inb(clock_reg); 128 129 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg); 130} 131 132static void pdc2026x_init_hwif(ide_hwif_t *hwif) 133{ 134 pdc_old_disable_66MHz_clock(hwif); 135} 136 137static void pdc202xx_dma_start(ide_drive_t *drive) 138{ 139 if (drive->current_speed > XFER_UDMA_2) 140 pdc_old_enable_66MHz_clock(drive->hwif); 141 if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) { 142 ide_hwif_t *hwif = drive->hwif; 143 struct request *rq = hwif->rq; 144 unsigned long high_16 = hwif->extra_base - 16; 145 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20); 146 u32 word_count = 0; 147 u8 clock = inb(high_16 + 0x11); 148 149 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11); 150 word_count = (blk_rq_sectors(rq) << 8); 151 word_count = (rq_data_dir(rq) == READ) ? 152 word_count | 0x05000000 : 153 word_count | 0x06000000; 154 outl(word_count, atapi_reg); 155 } 156 ide_dma_start(drive); 157} 158 159static int pdc202xx_dma_end(ide_drive_t *drive) 160{ 161 if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) { 162 ide_hwif_t *hwif = drive->hwif; 163 unsigned long high_16 = hwif->extra_base - 16; 164 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20); 165 u8 clock = 0; 166 167 outl(0, atapi_reg); /* zero out extra */ 168 clock = inb(high_16 + 0x11); 169 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11); 170 } 171 if (drive->current_speed > XFER_UDMA_2) 172 pdc_old_disable_66MHz_clock(drive->hwif); 173 return ide_dma_end(drive); 174} 175 176static int init_chipset_pdc202xx(struct pci_dev *dev) 177{ 178 unsigned long dmabase = pci_resource_start(dev, 4); 179 u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0; 180 181 if (dmabase == 0) 182 goto out; 183 184 udma_speed_flag = inb(dmabase | 0x1f); 185 primary_mode = inb(dmabase | 0x1a); 186 secondary_mode = inb(dmabase | 0x1b); 187 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \ 188 "Primary %s Mode " \ 189 "Secondary %s Mode.\n", pci_name(dev), 190 (udma_speed_flag & 1) ? "EN" : "DIS", 191 (primary_mode & 1) ? "MASTER" : "PCI", 192 (secondary_mode & 1) ? "MASTER" : "PCI" ); 193 194 if (!(udma_speed_flag & 1)) { 195 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ", 196 pci_name(dev), udma_speed_flag, 197 (udma_speed_flag|1)); 198 outb(udma_speed_flag | 1, dmabase | 0x1f); 199 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN"); 200 } 201out: 202 return 0; 203} 204 205static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev, 206 const char *name) 207{ 208 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) { 209 u8 irq = 0, irq2 = 0; 210 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 211 /* 0xbc */ 212 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2); 213 if (irq != irq2) { 214 pci_write_config_byte(dev, 215 (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */ 216 printk(KERN_INFO "%s %s: PCI config space interrupt " 217 "mirror fixed\n", name, pci_name(dev)); 218 } 219 } 220} 221 222#define IDE_HFLAGS_PDC202XX \ 223 (IDE_HFLAG_ERROR_STOPS_FIFO | \ 224 IDE_HFLAG_OFF_BOARD) 225 226static const struct ide_port_ops pdc20246_port_ops = { 227 .set_pio_mode = pdc202xx_set_pio_mode, 228 .set_dma_mode = pdc202xx_set_mode, 229 .test_irq = pdc202xx_test_irq, 230}; 231 232static const struct ide_port_ops pdc2026x_port_ops = { 233 .set_pio_mode = pdc202xx_set_pio_mode, 234 .set_dma_mode = pdc202xx_set_mode, 235 .test_irq = pdc202xx_test_irq, 236 .cable_detect = pdc2026x_cable_detect, 237}; 238 239static const struct ide_dma_ops pdc2026x_dma_ops = { 240 .dma_host_set = ide_dma_host_set, 241 .dma_setup = ide_dma_setup, 242 .dma_start = pdc202xx_dma_start, 243 .dma_end = pdc202xx_dma_end, 244 .dma_test_irq = ide_dma_test_irq, 245 .dma_lost_irq = ide_dma_lost_irq, 246 .dma_timer_expiry = ide_dma_sff_timer_expiry, 247 .dma_sff_read_status = ide_dma_sff_read_status, 248}; 249 250#define DECLARE_PDC2026X_DEV(udma, sectors) \ 251 { \ 252 .name = DRV_NAME, \ 253 .init_chipset = init_chipset_pdc202xx, \ 254 .init_hwif = pdc2026x_init_hwif, \ 255 .port_ops = &pdc2026x_port_ops, \ 256 .dma_ops = &pdc2026x_dma_ops, \ 257 .host_flags = IDE_HFLAGS_PDC202XX, \ 258 .pio_mask = ATA_PIO4, \ 259 .mwdma_mask = ATA_MWDMA2, \ 260 .udma_mask = udma, \ 261 .max_sectors = sectors, \ 262 } 263 264static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = { 265 { /* 0: PDC20246 */ 266 .name = DRV_NAME, 267 .init_chipset = init_chipset_pdc202xx, 268 .port_ops = &pdc20246_port_ops, 269 .dma_ops = &sff_dma_ops, 270 .host_flags = IDE_HFLAGS_PDC202XX, 271 .pio_mask = ATA_PIO4, 272 .mwdma_mask = ATA_MWDMA2, 273 .udma_mask = ATA_UDMA2, 274 }, 275 276 /* 1: PDC2026{2,3} */ 277 DECLARE_PDC2026X_DEV(ATA_UDMA4, 0), 278 /* 2: PDC2026{5,7}: UDMA5, limit LBA48 requests to 256 sectors */ 279 DECLARE_PDC2026X_DEV(ATA_UDMA5, 256), 280}; 281 282/** 283 * pdc202xx_init_one - called when a PDC202xx is found 284 * @dev: the pdc202xx device 285 * @id: the matching pci id 286 * 287 * Called when the PCI registration layer (or the IDE initialization) 288 * finds a device matching our IDE device tables. 289 */ 290 291static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id) 292{ 293 const struct ide_port_info *d; 294 u8 idx = id->driver_data; 295 296 d = &pdc202xx_chipsets[idx]; 297 298 if (idx < 2) 299 pdc202ata4_fixup_irq(dev, d->name); 300 301 if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) { 302 struct pci_dev *bridge = dev->bus->self; 303 304 if (bridge && 305 bridge->vendor == PCI_VENDOR_ID_INTEL && 306 (bridge->device == PCI_DEVICE_ID_INTEL_I960 || 307 bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) { 308 printk(KERN_INFO DRV_NAME " %s: skipping Promise " 309 "PDC20265 attached to I2O RAID controller\n", 310 pci_name(dev)); 311 return -ENODEV; 312 } 313 } 314 315 return ide_pci_init_one(dev, d, NULL); 316} 317 318static const struct pci_device_id pdc202xx_pci_tbl[] = { 319 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 }, 320 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 }, 321 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 }, 322 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 }, 323 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 }, 324 { 0, }, 325}; 326MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl); 327 328static struct pci_driver pdc202xx_pci_driver = { 329 .name = "Promise_Old_IDE", 330 .id_table = pdc202xx_pci_tbl, 331 .probe = pdc202xx_init_one, 332 .remove = ide_pci_remove, 333 .suspend = ide_pci_suspend, 334 .resume = ide_pci_resume, 335}; 336 337static int __init pdc202xx_ide_init(void) 338{ 339 return ide_pci_register_driver(&pdc202xx_pci_driver); 340} 341 342static void __exit pdc202xx_ide_exit(void) 343{ 344 pci_unregister_driver(&pdc202xx_pci_driver); 345} 346 347module_init(pdc202xx_ide_init); 348module_exit(pdc202xx_ide_exit); 349 350MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Bartlomiej Zolnierkiewicz"); 351MODULE_DESCRIPTION("PCI driver module for older Promise IDE"); 352MODULE_LICENSE("GPL"); 353