1/* 2 * Copyright (C) 2007 Ben Skeggs. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27#include "drmP.h" 28#include "drm.h" 29#include "nouveau_drv.h" 30 31#include "nouveau_grctx.h" 32 33static void 34nv50_graph_init_reset(struct drm_device *dev) 35{ 36 uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH | (1 << 21); 37 38 NV_DEBUG(dev, "\n"); 39 40 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e); 41 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | pmc_e); 42} 43 44static void 45nv50_graph_init_intr(struct drm_device *dev) 46{ 47 NV_DEBUG(dev, "\n"); 48 49 nv_wr32(dev, NV03_PGRAPH_INTR, 0xffffffff); 50 nv_wr32(dev, 0x400138, 0xffffffff); 51 nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xffffffff); 52} 53 54static void 55nv50_graph_init_regs__nv(struct drm_device *dev) 56{ 57 struct drm_nouveau_private *dev_priv = dev->dev_private; 58 uint32_t units = nv_rd32(dev, 0x1540); 59 int i; 60 61 NV_DEBUG(dev, "\n"); 62 63 nv_wr32(dev, 0x400804, 0xc0000000); 64 nv_wr32(dev, 0x406800, 0xc0000000); 65 nv_wr32(dev, 0x400c04, 0xc0000000); 66 nv_wr32(dev, 0x401800, 0xc0000000); 67 nv_wr32(dev, 0x405018, 0xc0000000); 68 nv_wr32(dev, 0x402000, 0xc0000000); 69 70 for (i = 0; i < 16; i++) { 71 if (units & 1 << i) { 72 if (dev_priv->chipset < 0xa0) { 73 nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000); 74 nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000); 75 nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000); 76 } else { 77 nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000); 78 nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000); 79 nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000); 80 } 81 } 82 } 83 84 nv_wr32(dev, 0x400108, 0xffffffff); 85 86 nv_wr32(dev, 0x400824, 0x00004000); 87 nv_wr32(dev, 0x400500, 0x00010001); 88} 89 90static void 91nv50_graph_init_regs(struct drm_device *dev) 92{ 93 NV_DEBUG(dev, "\n"); 94 95 nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 96 (1 << 2) /* HW_CONTEXT_SWITCH_ENABLED */); 97 nv_wr32(dev, 0x402ca8, 0x800); 98} 99 100static int 101nv50_graph_init_ctxctl(struct drm_device *dev) 102{ 103 struct drm_nouveau_private *dev_priv = dev->dev_private; 104 struct nouveau_grctx ctx = {}; 105 uint32_t *cp; 106 int i; 107 108 NV_DEBUG(dev, "\n"); 109 110 cp = kmalloc(512 * 4, GFP_KERNEL); 111 if (!cp) { 112 NV_ERROR(dev, "failed to allocate ctxprog\n"); 113 dev_priv->engine.graph.accel_blocked = true; 114 return 0; 115 } 116 117 ctx.dev = dev; 118 ctx.mode = NOUVEAU_GRCTX_PROG; 119 ctx.data = cp; 120 ctx.ctxprog_max = 512; 121 if (!nv50_grctx_init(&ctx)) { 122 dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4; 123 124 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0); 125 for (i = 0; i < ctx.ctxprog_len; i++) 126 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]); 127 } else { 128 dev_priv->engine.graph.accel_blocked = true; 129 } 130 kfree(cp); 131 132 nv_wr32(dev, 0x400320, 4); 133 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0); 134 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, 0); 135 return 0; 136} 137 138int 139nv50_graph_init(struct drm_device *dev) 140{ 141 int ret; 142 143 NV_DEBUG(dev, "\n"); 144 145 nv50_graph_init_reset(dev); 146 nv50_graph_init_regs__nv(dev); 147 nv50_graph_init_regs(dev); 148 nv50_graph_init_intr(dev); 149 150 ret = nv50_graph_init_ctxctl(dev); 151 if (ret) 152 return ret; 153 154 return 0; 155} 156 157void 158nv50_graph_takedown(struct drm_device *dev) 159{ 160 NV_DEBUG(dev, "\n"); 161} 162 163void 164nv50_graph_fifo_access(struct drm_device *dev, bool enabled) 165{ 166 const uint32_t mask = 0x00010001; 167 168 if (enabled) 169 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | mask); 170 else 171 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) & ~mask); 172} 173 174struct nouveau_channel * 175nv50_graph_channel(struct drm_device *dev) 176{ 177 struct drm_nouveau_private *dev_priv = dev->dev_private; 178 uint32_t inst; 179 int i; 180 181 /* Be sure we're not in the middle of a context switch or bad things 182 * will happen, such as unloading the wrong pgraph context. 183 */ 184 if (!nv_wait(0x400300, 0x00000001, 0x00000000)) 185 NV_ERROR(dev, "Ctxprog is still running\n"); 186 187 inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR); 188 if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED)) 189 return NULL; 190 inst = (inst & NV50_PGRAPH_CTXCTL_CUR_INSTANCE) << 12; 191 192 for (i = 0; i < dev_priv->engine.fifo.channels; i++) { 193 struct nouveau_channel *chan = dev_priv->fifos[i]; 194 195 if (chan && chan->ramin && chan->ramin->instance == inst) 196 return chan; 197 } 198 199 return NULL; 200} 201 202int 203nv50_graph_create_context(struct nouveau_channel *chan) 204{ 205 struct drm_device *dev = chan->dev; 206 struct drm_nouveau_private *dev_priv = dev->dev_private; 207 struct nouveau_gpuobj *ramin = chan->ramin->gpuobj; 208 struct nouveau_gpuobj *obj; 209 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 210 struct nouveau_grctx ctx = {}; 211 int hdr, ret; 212 213 NV_DEBUG(dev, "ch%d\n", chan->id); 214 215 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size, 216 0x1000, NVOBJ_FLAG_ZERO_ALLOC | 217 NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx); 218 if (ret) 219 return ret; 220 obj = chan->ramin_grctx->gpuobj; 221 222 hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20; 223 nv_wo32(dev, ramin, (hdr + 0x00)/4, 0x00190002); 224 nv_wo32(dev, ramin, (hdr + 0x04)/4, chan->ramin_grctx->instance + 225 pgraph->grctx_size - 1); 226 nv_wo32(dev, ramin, (hdr + 0x08)/4, chan->ramin_grctx->instance); 227 nv_wo32(dev, ramin, (hdr + 0x0c)/4, 0); 228 nv_wo32(dev, ramin, (hdr + 0x10)/4, 0); 229 nv_wo32(dev, ramin, (hdr + 0x14)/4, 0x00010000); 230 231 ctx.dev = chan->dev; 232 ctx.mode = NOUVEAU_GRCTX_VALS; 233 ctx.data = obj; 234 nv50_grctx_init(&ctx); 235 236 nv_wo32(dev, obj, 0x00000/4, chan->ramin->instance >> 12); 237 238 dev_priv->engine.instmem.flush(dev); 239 return 0; 240} 241 242void 243nv50_graph_destroy_context(struct nouveau_channel *chan) 244{ 245 struct drm_device *dev = chan->dev; 246 struct drm_nouveau_private *dev_priv = dev->dev_private; 247 int i, hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20; 248 249 NV_DEBUG(dev, "ch%d\n", chan->id); 250 251 if (!chan->ramin || !chan->ramin->gpuobj) 252 return; 253 254 for (i = hdr; i < hdr + 24; i += 4) 255 nv_wo32(dev, chan->ramin->gpuobj, i/4, 0); 256 dev_priv->engine.instmem.flush(dev); 257 258 nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); 259} 260 261static int 262nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst) 263{ 264 uint32_t fifo = nv_rd32(dev, 0x400500); 265 266 nv_wr32(dev, 0x400500, fifo & ~1); 267 nv_wr32(dev, 0x400784, inst); 268 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x40); 269 nv_wr32(dev, 0x400320, nv_rd32(dev, 0x400320) | 0x11); 270 nv_wr32(dev, 0x400040, 0xffffffff); 271 (void)nv_rd32(dev, 0x400040); 272 nv_wr32(dev, 0x400040, 0x00000000); 273 nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 1); 274 275 if (nouveau_wait_for_idle(dev)) 276 nv_wr32(dev, 0x40032c, inst | (1<<31)); 277 nv_wr32(dev, 0x400500, fifo); 278 279 return 0; 280} 281 282int 283nv50_graph_load_context(struct nouveau_channel *chan) 284{ 285 uint32_t inst = chan->ramin->instance >> 12; 286 287 NV_DEBUG(chan->dev, "ch%d\n", chan->id); 288 return nv50_graph_do_load_context(chan->dev, inst); 289} 290 291int 292nv50_graph_unload_context(struct drm_device *dev) 293{ 294 uint32_t inst; 295 296 inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR); 297 if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED)) 298 return 0; 299 inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE; 300 301 nouveau_wait_for_idle(dev); 302 nv_wr32(dev, 0x400784, inst); 303 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20); 304 nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01); 305 nouveau_wait_for_idle(dev); 306 307 nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst); 308 return 0; 309} 310 311void 312nv50_graph_context_switch(struct drm_device *dev) 313{ 314 uint32_t inst; 315 316 nv50_graph_unload_context(dev); 317 318 inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_NEXT); 319 inst &= NV50_PGRAPH_CTXCTL_NEXT_INSTANCE; 320 nv50_graph_do_load_context(dev, inst); 321 322 nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev, 323 NV40_PGRAPH_INTR_EN) | NV_PGRAPH_INTR_CONTEXT_SWITCH); 324} 325 326static int 327nv50_graph_nvsw_dma_vblsem(struct nouveau_channel *chan, int grclass, 328 int mthd, uint32_t data) 329{ 330 struct nouveau_gpuobj_ref *ref = NULL; 331 332 if (nouveau_gpuobj_ref_find(chan, data, &ref)) 333 return -ENOENT; 334 335 if (nouveau_notifier_offset(ref->gpuobj, NULL)) 336 return -EINVAL; 337 338 chan->nvsw.vblsem = ref->gpuobj; 339 chan->nvsw.vblsem_offset = ~0; 340 return 0; 341} 342 343static int 344nv50_graph_nvsw_vblsem_offset(struct nouveau_channel *chan, int grclass, 345 int mthd, uint32_t data) 346{ 347 if (nouveau_notifier_offset(chan->nvsw.vblsem, &data)) 348 return -ERANGE; 349 350 chan->nvsw.vblsem_offset = data >> 2; 351 return 0; 352} 353 354static int 355nv50_graph_nvsw_vblsem_release_val(struct nouveau_channel *chan, int grclass, 356 int mthd, uint32_t data) 357{ 358 chan->nvsw.vblsem_rval = data; 359 return 0; 360} 361 362static int 363nv50_graph_nvsw_vblsem_release(struct nouveau_channel *chan, int grclass, 364 int mthd, uint32_t data) 365{ 366 struct drm_device *dev = chan->dev; 367 struct drm_nouveau_private *dev_priv = dev->dev_private; 368 369 if (!chan->nvsw.vblsem || chan->nvsw.vblsem_offset == ~0 || data > 1) 370 return -EINVAL; 371 372 if (!(nv_rd32(dev, NV50_PDISPLAY_INTR_EN) & 373 NV50_PDISPLAY_INTR_EN_VBLANK_CRTC_(data))) { 374 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 375 NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(data)); 376 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev, 377 NV50_PDISPLAY_INTR_EN) | 378 NV50_PDISPLAY_INTR_EN_VBLANK_CRTC_(data)); 379 } 380 381 list_add(&chan->nvsw.vbl_wait, &dev_priv->vbl_waiting); 382 return 0; 383} 384 385static struct nouveau_pgraph_object_method nv50_graph_nvsw_methods[] = { 386 { 0x018c, nv50_graph_nvsw_dma_vblsem }, 387 { 0x0400, nv50_graph_nvsw_vblsem_offset }, 388 { 0x0404, nv50_graph_nvsw_vblsem_release_val }, 389 { 0x0408, nv50_graph_nvsw_vblsem_release }, 390 {} 391}; 392 393struct nouveau_pgraph_object_class nv50_graph_grclass[] = { 394 { 0x506e, true, nv50_graph_nvsw_methods }, /* nvsw */ 395 { 0x0030, false, NULL }, /* null */ 396 { 0x5039, false, NULL }, /* m2mf */ 397 { 0x502d, false, NULL }, /* 2d */ 398 { 0x50c0, false, NULL }, /* compute */ 399 { 0x85c0, false, NULL }, /* compute (nva3, nva5, nva8) */ 400 { 0x5097, false, NULL }, /* tesla (nv50) */ 401 { 0x8297, false, NULL }, /* tesla (nv8x/nv9x) */ 402 { 0x8397, false, NULL }, /* tesla (nva0, nvaa, nvac) */ 403 { 0x8597, false, NULL }, /* tesla (nva3, nva5, nva8) */ 404 {} 405}; 406