1#include "drmP.h" 2#include "drm.h" 3#include "nouveau_drv.h" 4 5/* returns the size of fifo context */ 6static int 7nouveau_fifo_ctx_size(struct drm_device *dev) 8{ 9 struct drm_nouveau_private *dev_priv = dev->dev_private; 10 11 if (dev_priv->chipset >= 0x40) 12 return 128; 13 else 14 if (dev_priv->chipset >= 0x17) 15 return 64; 16 17 return 32; 18} 19 20static void 21nv04_instmem_determine_amount(struct drm_device *dev) 22{ 23 struct drm_nouveau_private *dev_priv = dev->dev_private; 24 int i; 25 26 /* Figure out how much instance memory we need */ 27 if (dev_priv->card_type >= NV_40) { 28 /* We'll want more instance memory than this on some NV4x cards. 29 * There's a 16MB aperture to play with that maps onto the end 30 * of vram. For now, only reserve a small piece until we know 31 * more about what each chipset requires. 32 */ 33 switch (dev_priv->chipset) { 34 case 0x40: 35 case 0x47: 36 case 0x49: 37 case 0x4b: 38 dev_priv->ramin_rsvd_vram = (2 * 1024 * 1024); 39 break; 40 default: 41 dev_priv->ramin_rsvd_vram = (1 * 1024 * 1024); 42 break; 43 } 44 } else { 45 dev_priv->ramin_rsvd_vram = (512 * 1024); 46 } 47 NV_DEBUG(dev, "RAMIN size: %dKiB\n", dev_priv->ramin_rsvd_vram >> 10); 48 49 /* Clear all of it, except the BIOS image that's in the first 64KiB */ 50 for (i = 64 * 1024; i < dev_priv->ramin_rsvd_vram; i += 4) 51 nv_wi32(dev, i, 0x00000000); 52} 53 54static void 55nv04_instmem_configure_fixed_tables(struct drm_device *dev) 56{ 57 struct drm_nouveau_private *dev_priv = dev->dev_private; 58 struct nouveau_engine *engine = &dev_priv->engine; 59 60 /* FIFO hash table (RAMHT) 61 * use 4k hash table at RAMIN+0x10000 62 * TODO: extend the hash table 63 */ 64 dev_priv->ramht_offset = 0x10000; 65 dev_priv->ramht_bits = 9; 66 dev_priv->ramht_size = (1 << dev_priv->ramht_bits); /* nr entries */ 67 dev_priv->ramht_size *= 8; /* 2 32-bit values per entry in RAMHT */ 68 NV_DEBUG(dev, "RAMHT offset=0x%x, size=%d\n", dev_priv->ramht_offset, 69 dev_priv->ramht_size); 70 71 /* FIFO runout table (RAMRO) - 512k at 0x11200 */ 72 dev_priv->ramro_offset = 0x11200; 73 dev_priv->ramro_size = 512; 74 NV_DEBUG(dev, "RAMRO offset=0x%x, size=%d\n", dev_priv->ramro_offset, 75 dev_priv->ramro_size); 76 77 /* FIFO context table (RAMFC) 78 * NV40 : Not sure exactly how to position RAMFC on some cards, 79 * 0x30002 seems to position it at RAMIN+0x20000 on these 80 * cards. RAMFC is 4kb (32 fifos, 128byte entries). 81 * Others: Position RAMFC at RAMIN+0x11400 82 */ 83 dev_priv->ramfc_size = engine->fifo.channels * 84 nouveau_fifo_ctx_size(dev); 85 switch (dev_priv->card_type) { 86 case NV_40: 87 dev_priv->ramfc_offset = 0x20000; 88 break; 89 case NV_30: 90 case NV_20: 91 case NV_10: 92 case NV_04: 93 default: 94 dev_priv->ramfc_offset = 0x11400; 95 break; 96 } 97 NV_DEBUG(dev, "RAMFC offset=0x%x, size=%d\n", dev_priv->ramfc_offset, 98 dev_priv->ramfc_size); 99} 100 101int nv04_instmem_init(struct drm_device *dev) 102{ 103 struct drm_nouveau_private *dev_priv = dev->dev_private; 104 uint32_t offset; 105 int ret; 106 107 nv04_instmem_determine_amount(dev); 108 nv04_instmem_configure_fixed_tables(dev); 109 110 /* Create a heap to manage RAMIN allocations, we don't allocate 111 * the space that was reserved for RAMHT/FC/RO. 112 */ 113 offset = dev_priv->ramfc_offset + dev_priv->ramfc_size; 114 115 /* It appears RAMRO (or something?) is controlled by 0x2220/0x2230 116 * on certain NV4x chipsets as well as RAMFC. When 0x2230 == 0 117 * ("new style" control) the upper 16-bits of 0x2220 points at this 118 * other mysterious table that's clobbering important things. 119 * 120 * We're now pointing this at RAMIN+0x30000 to avoid RAMFC getting 121 * smashed to pieces on us, so reserve 0x30000-0x40000 too.. 122 */ 123 if (dev_priv->card_type >= NV_40) { 124 if (offset < 0x40000) 125 offset = 0x40000; 126 } 127 128 ret = drm_mm_init(&dev_priv->ramin_heap, offset, 129 dev_priv->ramin_rsvd_vram - offset); 130 if (ret) { 131 NV_ERROR(dev, "Failed to init RAMIN heap: %d\n", ret); 132 return ret; 133 } 134 135 return 0; 136} 137 138void 139nv04_instmem_takedown(struct drm_device *dev) 140{ 141} 142 143int 144nv04_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, uint32_t *sz) 145{ 146 if (gpuobj->im_backing) 147 return -EINVAL; 148 149 return 0; 150} 151 152void 153nv04_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) 154{ 155 struct drm_nouveau_private *dev_priv = dev->dev_private; 156 157 if (gpuobj && gpuobj->im_backing) { 158 if (gpuobj->im_bound) 159 dev_priv->engine.instmem.unbind(dev, gpuobj); 160 gpuobj->im_backing = NULL; 161 } 162} 163 164int 165nv04_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) 166{ 167 if (!gpuobj->im_pramin || gpuobj->im_bound) 168 return -EINVAL; 169 170 gpuobj->im_bound = 1; 171 return 0; 172} 173 174int 175nv04_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) 176{ 177 if (gpuobj->im_bound == 0) 178 return -EINVAL; 179 180 gpuobj->im_bound = 0; 181 return 0; 182} 183 184void 185nv04_instmem_flush(struct drm_device *dev) 186{ 187} 188 189int 190nv04_instmem_suspend(struct drm_device *dev) 191{ 192 return 0; 193} 194 195void 196nv04_instmem_resume(struct drm_device *dev) 197{ 198} 199