1/* 2 * pata_optidma.c - Opti DMA PATA for new ATA layer 3 * (C) 2006 Red Hat Inc 4 * 5 * The Opti DMA controllers are related to the older PIO PCI controllers 6 * and indeed the VLB ones. The main differences are that the timing 7 * numbers are now based off PCI clocks not VLB and differ, and that 8 * MWDMA is supported. 9 * 10 * This driver should support Viper-N+, FireStar, FireStar Plus. 11 * 12 * These devices support virtual DMA for read (aka the CS5520). Later 13 * chips support UDMA33, but only if the rest of the board logic does, 14 * so you have to get this right. We don't support the virtual DMA 15 * but we do handle UDMA. 16 * 17 * Bits that are worth knowing 18 * Most control registers are shadowed into I/O registers 19 * 0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz 20 * Virtual DMA registers *move* between rev 0x02 and rev 0x10 21 * UDMA requires a 66MHz FSB 22 * 23 */ 24 25#include <linux/kernel.h> 26#include <linux/module.h> 27#include <linux/pci.h> 28#include <linux/init.h> 29#include <linux/blkdev.h> 30#include <linux/delay.h> 31#include <scsi/scsi_host.h> 32#include <linux/libata.h> 33 34#define DRV_NAME "pata_optidma" 35#define DRV_VERSION "0.3.2" 36 37enum { 38 READ_REG = 0, /* index of Read cycle timing register */ 39 WRITE_REG = 1, /* index of Write cycle timing register */ 40 CNTRL_REG = 3, /* index of Control register */ 41 STRAP_REG = 5, /* index of Strap register */ 42 MISC_REG = 6 /* index of Miscellaneous register */ 43}; 44 45static int pci_clock; /* 0 = 33 1 = 25 */ 46 47/** 48 * optidma_pre_reset - probe begin 49 * @link: ATA link 50 * @deadline: deadline jiffies for the operation 51 * 52 * Set up cable type and use generic probe init 53 */ 54 55static int optidma_pre_reset(struct ata_link *link, unsigned long deadline) 56{ 57 struct ata_port *ap = link->ap; 58 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 59 static const struct pci_bits optidma_enable_bits = { 60 0x40, 1, 0x08, 0x00 61 }; 62 63 if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits)) 64 return -ENOENT; 65 66 return ata_sff_prereset(link, deadline); 67} 68 69/** 70 * optidma_unlock - unlock control registers 71 * @ap: ATA port 72 * 73 * Unlock the control register block for this adapter. Registers must not 74 * be unlocked in a situation where libata might look at them. 75 */ 76 77static void optidma_unlock(struct ata_port *ap) 78{ 79 void __iomem *regio = ap->ioaddr.cmd_addr; 80 81 /* These 3 unlock the control register access */ 82 ioread16(regio + 1); 83 ioread16(regio + 1); 84 iowrite8(3, regio + 2); 85} 86 87/** 88 * optidma_lock - issue temporary relock 89 * @ap: ATA port 90 * 91 * Re-lock the configuration register settings. 92 */ 93 94static void optidma_lock(struct ata_port *ap) 95{ 96 void __iomem *regio = ap->ioaddr.cmd_addr; 97 98 /* Relock */ 99 iowrite8(0x83, regio + 2); 100} 101 102/** 103 * optidma_mode_setup - set mode data 104 * @ap: ATA interface 105 * @adev: ATA device 106 * @mode: Mode to set 107 * 108 * Called to do the DMA or PIO mode setup. Timing numbers are all 109 * pre computed to keep the code clean. There are two tables depending 110 * on the hardware clock speed. 111 * 112 * WARNING: While we do this the IDE registers vanish. If we take an 113 * IRQ here we depend on the host set locking to avoid catastrophe. 114 */ 115 116static void optidma_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode) 117{ 118 struct ata_device *pair = ata_dev_pair(adev); 119 int pio = adev->pio_mode - XFER_PIO_0; 120 int dma = adev->dma_mode - XFER_MW_DMA_0; 121 void __iomem *regio = ap->ioaddr.cmd_addr; 122 u8 addr; 123 124 /* Address table precomputed with a DCLK of 2 */ 125 static const u8 addr_timing[2][5] = { 126 { 0x30, 0x20, 0x20, 0x10, 0x10 }, 127 { 0x20, 0x20, 0x10, 0x10, 0x10 } 128 }; 129 static const u8 data_rec_timing[2][5] = { 130 { 0x59, 0x46, 0x30, 0x20, 0x20 }, 131 { 0x46, 0x32, 0x20, 0x20, 0x10 } 132 }; 133 static const u8 dma_data_rec_timing[2][3] = { 134 { 0x76, 0x20, 0x20 }, 135 { 0x54, 0x20, 0x10 } 136 }; 137 138 /* Switch from IDE to control mode */ 139 optidma_unlock(ap); 140 141 142 143 if (mode >= XFER_MW_DMA_0) 144 addr = 0; 145 else 146 addr = addr_timing[pci_clock][pio]; 147 148 if (pair) { 149 u8 pair_addr; 150 /* Hardware constraint */ 151 if (pair->dma_mode) 152 pair_addr = 0; 153 else 154 pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0]; 155 if (pair_addr > addr) 156 addr = pair_addr; 157 } 158 159 /* Commence primary programming sequence */ 160 /* First we load the device number into the timing select */ 161 iowrite8(adev->devno, regio + MISC_REG); 162 /* Now we load the data timings into read data/write data */ 163 if (mode < XFER_MW_DMA_0) { 164 iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG); 165 iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG); 166 } else if (mode < XFER_UDMA_0) { 167 iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG); 168 iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG); 169 } 170 /* Finally we load the address setup into the misc register */ 171 iowrite8(addr | adev->devno, regio + MISC_REG); 172 173 /* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */ 174 iowrite8(0x85, regio + CNTRL_REG); 175 176 /* Switch back to IDE mode */ 177 optidma_lock(ap); 178 179 /* Note: at this point our programming is incomplete. We are 180 not supposed to program PCI 0x43 "things we hacked onto the chip" 181 until we've done both sets of PIO/DMA timings */ 182} 183 184/** 185 * optiplus_mode_setup - DMA setup for Firestar Plus 186 * @ap: ATA port 187 * @adev: device 188 * @mode: desired mode 189 * 190 * The Firestar plus has additional UDMA functionality for UDMA0-2 and 191 * requires we do some additional work. Because the base work we must do 192 * is mostly shared we wrap the Firestar setup functionality in this 193 * one 194 */ 195 196static void optiplus_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode) 197{ 198 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 199 u8 udcfg; 200 u8 udslave; 201 int dev2 = 2 * adev->devno; 202 int unit = 2 * ap->port_no + adev->devno; 203 int udma = mode - XFER_UDMA_0; 204 205 pci_read_config_byte(pdev, 0x44, &udcfg); 206 if (mode <= XFER_UDMA_0) { 207 udcfg &= ~(1 << unit); 208 optidma_mode_setup(ap, adev, adev->dma_mode); 209 } else { 210 udcfg |= (1 << unit); 211 if (ap->port_no) { 212 pci_read_config_byte(pdev, 0x45, &udslave); 213 udslave &= ~(0x03 << dev2); 214 udslave |= (udma << dev2); 215 pci_write_config_byte(pdev, 0x45, udslave); 216 } else { 217 udcfg &= ~(0x30 << dev2); 218 udcfg |= (udma << dev2); 219 } 220 } 221 pci_write_config_byte(pdev, 0x44, udcfg); 222} 223 224/** 225 * optidma_set_pio_mode - PIO setup callback 226 * @ap: ATA port 227 * @adev: Device 228 * 229 * The libata core provides separate functions for handling PIO and 230 * DMA programming. The architecture of the Firestar makes it easier 231 * for us to have a common function so we provide wrappers 232 */ 233 234static void optidma_set_pio_mode(struct ata_port *ap, struct ata_device *adev) 235{ 236 optidma_mode_setup(ap, adev, adev->pio_mode); 237} 238 239/** 240 * optidma_set_dma_mode - DMA setup callback 241 * @ap: ATA port 242 * @adev: Device 243 * 244 * The libata core provides separate functions for handling PIO and 245 * DMA programming. The architecture of the Firestar makes it easier 246 * for us to have a common function so we provide wrappers 247 */ 248 249static void optidma_set_dma_mode(struct ata_port *ap, struct ata_device *adev) 250{ 251 optidma_mode_setup(ap, adev, adev->dma_mode); 252} 253 254/** 255 * optiplus_set_pio_mode - PIO setup callback 256 * @ap: ATA port 257 * @adev: Device 258 * 259 * The libata core provides separate functions for handling PIO and 260 * DMA programming. The architecture of the Firestar makes it easier 261 * for us to have a common function so we provide wrappers 262 */ 263 264static void optiplus_set_pio_mode(struct ata_port *ap, struct ata_device *adev) 265{ 266 optiplus_mode_setup(ap, adev, adev->pio_mode); 267} 268 269/** 270 * optiplus_set_dma_mode - DMA setup callback 271 * @ap: ATA port 272 * @adev: Device 273 * 274 * The libata core provides separate functions for handling PIO and 275 * DMA programming. The architecture of the Firestar makes it easier 276 * for us to have a common function so we provide wrappers 277 */ 278 279static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev) 280{ 281 optiplus_mode_setup(ap, adev, adev->dma_mode); 282} 283 284/** 285 * optidma_make_bits - PCI setup helper 286 * @adev: ATA device 287 * 288 * Turn the ATA device setup into PCI configuration bits 289 * for register 0x43 and return the two bits needed. 290 */ 291 292static u8 optidma_make_bits43(struct ata_device *adev) 293{ 294 static const u8 bits43[5] = { 295 0, 0, 0, 1, 2 296 }; 297 if (!ata_dev_enabled(adev)) 298 return 0; 299 if (adev->dma_mode) 300 return adev->dma_mode - XFER_MW_DMA_0; 301 return bits43[adev->pio_mode - XFER_PIO_0]; 302} 303 304/** 305 * optidma_set_mode - mode setup 306 * @link: link to set up 307 * 308 * Use the standard setup to tune the chipset and then finalise the 309 * configuration by writing the nibble of extra bits of data into 310 * the chip. 311 */ 312 313static int optidma_set_mode(struct ata_link *link, struct ata_device **r_failed) 314{ 315 struct ata_port *ap = link->ap; 316 u8 r; 317 int nybble = 4 * ap->port_no; 318 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 319 int rc = ata_do_set_mode(link, r_failed); 320 if (rc == 0) { 321 pci_read_config_byte(pdev, 0x43, &r); 322 323 r &= (0x0F << nybble); 324 r |= (optidma_make_bits43(&link->device[0]) + 325 (optidma_make_bits43(&link->device[0]) << 2)) << nybble; 326 pci_write_config_byte(pdev, 0x43, r); 327 } 328 return rc; 329} 330 331static struct scsi_host_template optidma_sht = { 332 ATA_BMDMA_SHT(DRV_NAME), 333}; 334 335static struct ata_port_operations optidma_port_ops = { 336 .inherits = &ata_bmdma_port_ops, 337 .cable_detect = ata_cable_40wire, 338 .set_piomode = optidma_set_pio_mode, 339 .set_dmamode = optidma_set_dma_mode, 340 .set_mode = optidma_set_mode, 341 .prereset = optidma_pre_reset, 342}; 343 344static struct ata_port_operations optiplus_port_ops = { 345 .inherits = &optidma_port_ops, 346 .set_piomode = optiplus_set_pio_mode, 347 .set_dmamode = optiplus_set_dma_mode, 348}; 349 350/** 351 * optiplus_with_udma - Look for UDMA capable setup 352 * @pdev; ATA controller 353 */ 354 355static int optiplus_with_udma(struct pci_dev *pdev) 356{ 357 u8 r; 358 int ret = 0; 359 int ioport = 0x22; 360 struct pci_dev *dev1; 361 362 /* Find function 1 */ 363 dev1 = pci_get_device(0x1045, 0xC701, NULL); 364 if (dev1 == NULL) 365 return 0; 366 367 /* Rev must be >= 0x10 */ 368 pci_read_config_byte(dev1, 0x08, &r); 369 if (r < 0x10) 370 goto done_nomsg; 371 /* Read the chipset system configuration to check our mode */ 372 pci_read_config_byte(dev1, 0x5F, &r); 373 ioport |= (r << 8); 374 outb(0x10, ioport); 375 /* Must be 66Mhz sync */ 376 if ((inb(ioport + 2) & 1) == 0) 377 goto done; 378 379 /* Check the ATA arbitration/timing is suitable */ 380 pci_read_config_byte(pdev, 0x42, &r); 381 if ((r & 0x36) != 0x36) 382 goto done; 383 pci_read_config_byte(dev1, 0x52, &r); 384 if (r & 0x80) /* IDEDIR disabled */ 385 ret = 1; 386done: 387 printk(KERN_WARNING "UDMA not supported in this configuration.\n"); 388done_nomsg: /* Wrong chip revision */ 389 pci_dev_put(dev1); 390 return ret; 391} 392 393static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id) 394{ 395 static const struct ata_port_info info_82c700 = { 396 .flags = ATA_FLAG_SLAVE_POSS, 397 .pio_mask = ATA_PIO4, 398 .mwdma_mask = ATA_MWDMA2, 399 .port_ops = &optidma_port_ops 400 }; 401 static const struct ata_port_info info_82c700_udma = { 402 .flags = ATA_FLAG_SLAVE_POSS, 403 .pio_mask = ATA_PIO4, 404 .mwdma_mask = ATA_MWDMA2, 405 .udma_mask = ATA_UDMA2, 406 .port_ops = &optiplus_port_ops 407 }; 408 const struct ata_port_info *ppi[] = { &info_82c700, NULL }; 409 static int printed_version; 410 int rc; 411 412 if (!printed_version++) 413 dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n"); 414 415 rc = pcim_enable_device(dev); 416 if (rc) 417 return rc; 418 419 /* Fixed location chipset magic */ 420 inw(0x1F1); 421 inw(0x1F1); 422 pci_clock = inb(0x1F5) & 1; /* 0 = 33Mhz, 1 = 25Mhz */ 423 424 if (optiplus_with_udma(dev)) 425 ppi[0] = &info_82c700_udma; 426 427 return ata_pci_bmdma_init_one(dev, ppi, &optidma_sht, NULL, 0); 428} 429 430static const struct pci_device_id optidma[] = { 431 { PCI_VDEVICE(OPTI, 0xD568), }, /* Opti 82C700 */ 432 433 { }, 434}; 435 436static struct pci_driver optidma_pci_driver = { 437 .name = DRV_NAME, 438 .id_table = optidma, 439 .probe = optidma_init_one, 440 .remove = ata_pci_remove_one, 441#ifdef CONFIG_PM 442 .suspend = ata_pci_device_suspend, 443 .resume = ata_pci_device_resume, 444#endif 445}; 446 447static int __init optidma_init(void) 448{ 449 return pci_register_driver(&optidma_pci_driver); 450} 451 452static void __exit optidma_exit(void) 453{ 454 pci_unregister_driver(&optidma_pci_driver); 455} 456 457MODULE_AUTHOR("Alan Cox"); 458MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus"); 459MODULE_LICENSE("GPL"); 460MODULE_DEVICE_TABLE(pci, optidma); 461MODULE_VERSION(DRV_VERSION); 462 463module_init(optidma_init); 464module_exit(optidma_exit); 465